Optics Switching Technology Course Overview

Optics Switching
Technology

© P. Raatikainen

Switching Technology / 2005

L1 - 1

General
•

Lecturer:Pertti Raatikainen, research professor /VTT
email: pertti.raatikainen@vtt.fi

• Exercises:
Kari Seppänen, snr. research scientist /VTT
email: kari.seppänen@vtt.fi
• Information: http://www.netlab.hut.fi/opetus/s38165

© P. Raatikainen


L1 - 2

Goals of the course
• Understand what switching is about
• Understand the basic structure and functions of a
switching system
• Understand the role of a switching system in a
transport network
• Understand how a switching system works
• Understand technology related to switching
• Understand how conventional circuit switching is
related to packet switching
© P. Raatikainen


L1 - 3

Course outline

• Introduction to switching
– switching in general
– switching modes
– transport and switching

• Switch fabrics
– basics of fabric architectures
– fabric structures
– path search, self-routing and sorting

© P. Raatikainen


L1 - 4

Course outline
• Switch implementations
– PDH switches
– ATM switches
– routers

• Optical switching
– basics of WDM technology
– components for optical switching
– optical switching concepts

© P. Raatikainen


L1 - 5

Course requirements
• Preliminary information
– S-38.188 Tietoliikenneverkot or
S-72.423 Telecommunication Systems
(or a corresponding course)

• 13 lectures (á 3 hours) and 7 exercises (á 2 hours)
• Calculus exercises
• Grating
– Calculus 0 to 6 bonus points – valid in exams in 2005
– Examination, max 30 points

© P. Raatikainen


L1 - 6

Course material
• Lecture notes
• Understanding Telecommunications 1, Ericsson & Telia,
Studentlitteratur, 2001, ISBN 91-44-00212-2, Chapters 2-4.
• J. Hui: Switching and traffic theory for integrated broadband networks,
Kluwer Academic Publ., 1990, ISBN 0-7923-9061-X, Chapters 1 - 6.
• H. J. Chao, C. H. Lam and E. Oki: Broadband Packet Switching
technologies – A Practical Guide to ATM Switches and IP routers, John
Wiley & Sons, 2001, ISBN 0-471-00454-5.
• T.E. Stern and K. Bala: Multiwavelength Optical Networks: A Layered
Approach, Addison-Wesley, 1999, ISBN 0-201-30967-X.

© P. Raatikainen


L1 - 7

Additional reading
• A. Pattavina: Switching Theory - Architecture and Performance in
Broadband ATM Networks, John Wiley & Sons (Chichester), 1998,
IBSN 0-471-96338-0, Chapters 2 - 4.
• R. Ramaswami and K. Sivarajan, Optical Networks, A Practical
Perspective, Morgan Kaufman Publ., 2nd Ed., 2002, ISBN 1-55860-6556.

© P. Raatikainen


L1 - 8

Schedule
Day L/E
Topic
18.1.
L
Introduction to switching
25.1.
L
Transmission techniques and multiplexing
27.1. E
Exercise 1
1.2. L
Basic concepts of switch fabrics
8.2. L
Multistage fabric architectures 1
10.2. E
Exercise 2
15.2.
L
Multistage fabric architectures 2
22.2.
L Self- routing and sorting networ ks
24.2. E
Exercise 3
1.3. L
Switch fabric implementations
8.3. L
PDH switches
10.3. E
Exercise 4
15.3.
L
ATM switches
17.3. E
Exercise 5
22.3.
L
Routers
5.4. L
Introduction to optical networks
7.4. E
Exercise 6
12.4.
L
Optical network architectures
19.4.
L
Optical switches
21.4. E
Exercise 7

© P. Raatikainen


L1 - 9

Switching Technology S38.165

http://www.netlab.hut.fi/opetus/s38165

© P. Raatikainen


L1 - 10


• Switching in general
• Switching modes
• Transport and switching

© P. Raatikainen


L1 - 11

Switching in general
ITU-T specification for switching:
“The establishing, on-demand, of an individual
connection from a desired inlet to a desired outlet
within a set of inlets and outlets for as long as is
required for the transfer of information.”

inlet/outlet = a line or a channel
© P. Raatikainen


L1 - 12

Switching in general (cont.)

• Switching implies directing of information flows in
communications networks based on known rules
• Switching takes place in specialized network nodes
• Data switched on bit, octet, frame or packet level
• Size of a switched data unit is variable or fixed

© P. Raatikainen


L1 - 13

Why switching ?
• Switches allow reduction in overall network cost by reducing
number and/or cost of transmission links required to enable a
given user population to communicate
• Limited number of physical connections implies need for
sharing of transport resources, which means
– better utilization of transport capacity
– use of switching

• Switching systems are central components in
communications networks

© P. Raatikainen


L1 - 14

Full connectivity between hosts

Full mesh

© P. Raatikainen

Number of links to/from a host = n-1
Total number of links = n(n-1)/2


L1 - 15

Centralized switching

Number of links to/from a host = 1
Total number of links = n

© P. Raatikainen


L1 - 16

Switching network to connect hosts
Number of links to/from a host = 1
Total number of links depends
on used network topology

© P. Raatikainen


L1 - 17

Hierarchy of switching networks

Local
switching
network

To higher level of hierarchy

Long distance
switching network

© P. Raatikainen


L1 - 18

Sharing of link capacity

Space Division Multiplexing (SDM)
1

1
2

CH n

3

...

...

Physical
link

CH 2

...

3

2

CH 1

Physical
link

n

n

Space to be divided:

- physical cable or twisted pair
- frequency
- light wave

© P. Raatikainen


L1 - 19

Sharing of link capacity (cont.)
Time Division Multiplexing (TDM)
Synchronous transfer mode (STM)
1

...

2

1

n

n-1

1

…

3

2

2

1

...

...

2

n

n

Asynchronous transfer mode (ATM)
1

...

1
1

1

idle

idle

n

2

2

...

n

n
Overhead

© P. Raatikainen

2

1

...

2

k

Payload


L1 - 20

Main building blocks of a switch
Switch control

Input
Interface
Input
Card #1
Interface
Input
Card #1
interface #1

•
•
•
•
•

input signal reception
error checking and recovery
incoming frame disassembly
buffering
routing/switching decision

Switch
fabric

• switching of data units from
input interfaces to destined
output interfaces
• limited buffering

Output
Interface
Output
Card #1
Interface
Output
Card #1
interface #1

• buffering, prioritizing and
scheduling
• outgoing frame assembly
• output signal generation and
transmission

• processing of signaling/connection control information
• configuration and control of input/output interfaces and switch fabric

© P. Raatikainen


L1 - 21

Heterogeneity by switching
• Switching systems allow heterogeneity among terminals
– terminals of different processing and transmission speeds supported
– terminals may implement different sets of functionality

• and heterogeneity among transmission links by providing a
variety of interface types
– data rates can vary
– different link layer framing applied
– optical and electrical interfaces
– variable line coding

© P. Raatikainen


L1 - 22

Heterogeneity by switching (cont.)

…

Analog interface

…

Subscriber
mux
ISDN (2B+D) or E1

E1 or E2

E1, E2 or E3

…

Remote
subscriber
switch

© P. Raatikainen


L1 - 23

Basic types of witching networks
• Statically switched networks
– connections established for longer periods of time
(typically for months or years)
– management system used for connection manipulation

• Dynamically switched networks
– connections established for short periods of time (typically from
seconds to tens of minutes)
– active signaling needed to manipulate connections

• Routing networks
– no connections established - no signaling
– each data unit routed individually through a network
– routing decision made dynamically or statically
© P. Raatikainen


L1 - 24

Development of switching technologies
Broadband,
optical
Broadband,
electronic
SPC, digital switching
SPC, analog switching
Crossbar switch
Step-by-step
Manual
1950

SPC - stored program control
1960

1970

1980

1990

2000

2010

2020

Source: Understanding Telecommunications 1, Ericsson & Telia, Studentlitteratur, 2001.

© P. Raatikainen


L1 - 25

Development of switching tech. (cont.)
• Manual systems
– in the infancy of telephony, exchanges were built up with manually operated switching
equipment (the first one in 1878 in New Haven, USA)

• Electromechanical systems
– manual exchanges were replaced by automated electromechanical switching systems
– a patent for automated telephone exchange in 1889 (Almon B. Strowger)
– step-by-step selector controlled directly by dial of a telephone set
– developed later in the direction of register-controlled system in which number
information is first received and analyzed in a register – the register is used to select
alternative switching paths (e.g. 500 line selector in 1923 and crossbar system in 1937)
– more efficient routing of traffic through transmission network
– increased traffic capacity at lower cost

© P. Raatikainen


L1 - 26

Development of switching tech. (cont.)
• Computer-controlled systems
– FDM was developed round 1910, but implemented in 1950’s (ca. 1000 channels
transferred in a coaxial cable)
– PCM based digital multiplexing introduced in 1970’s – transmission quality improved –
costs reduced further when digital group switches were combined with digital
transmission systems
– computer control became necessary - the first computer controlled exchange put into
service in 1960 (in USA)
– strong growth of data traffic resulted in development of separate data networks and
switches – advent of packet switching (sorting, routing and buffering)
– N-ISDN network combined telephone exchange and packet data switches
– ATM based cell switching formed basis for B-ISDN
– next step is to use optical switching with electronic switch control – all optical switching
can be seen in the horizon
© P. Raatikainen


L1 - 27

Roadmap of Finnish networking
technologies
Circuit switching

Packet sw
UMTS
GSM
NMT-900
NMT-450
WWW

Arpanet

--->

Internet technology
Data networks
ISDN

Digitalization of Exchanges
Digital transmission
Automation of long distance telephony

1955

-60

-65

© P. Raatikainen

-70

-75

-80

-85

-90


-95

2000
L1 - 28

Challenges of modern switching
• Support of different traffic profiles
• constant and variable bit rates, bursty traffic, etc.

• Simultaneous switching of highly different data rates
• from kbits/s rates to Gbits/s rates

• Support of varying delay requirements
• constant and variable delays

• Scalability
• number of input/output links, link bit rates, etc.

• Reliability
• Cost
• Throughput
© P. Raatikainen


L1 - 29

Switching modes


© P. Raatikainen


L1 - 30

Narrowband network evolution
• Early telephone systems used analog technology - frequency division
multiplexing (FDM) and space division switching (SDS)
• When digital technology evolved time division multiplexing (TDM) and
time division switching (TDS) became possible
• Development of electronic components enabled integration of
TDM and TDS => Integrated Digital Network (IDN)
• Different and segregated communications networks were developed
– circuit switching for voice-only services
– packet switching for (low-speed) data services
– dedicated networks, e.g. for video and specialized data services

© P. Raatikainen


L1 - 31

Segregated transport

UNI

UNI

Voice

Voice

Data

Packet switching
network

Data

Data
Video

© P. Raatikainen

Circuit switching
network

Dedicated
network

Data
Video


L1 - 32

Narrowband network evolution (cont.)
• Service integration became apparent to better utilize communications
resources
=> IDN developed to ISDN (Integrated Services Digital Network)
• ISDN offered
– a unique user-network interface to support basic set of narrowband services
– integrated transport and full digital access
– inter-node signaling (based on packet switching)
– packet and circuit switched end-to-end digital connections
– three types of channels (B=64 kbit/s, D=16 kbit/s and H=nx64 kbit/s)

• Three types of long-distance interconnections
– circuit switched, packet switched and signaling connections

• Specialized services (such as video) continued to be supported by
separate dedicated networks
© P. Raatikainen


L1 - 33

Integrated transport

Signaling
network

UNI
Voice
Data

ISDN
switch

Circuit switching
network

UNI
ISDN
switch

Voice
Data

Packet switching
network
Data
Video

© P. Raatikainen

Dedicated
network


Data
Video

L1 - 34

Broadband network evolution
• Progress in optical technologies enabled huge transport capacities
=> integration of transmission of all the different networks
(NB and BB) became possible
• Switching nodes of different networks co-located to configure
multifunctional switches
– each type of traffic handled by its own switching module

• Multifunctional switches interconnected by broadband integrated
transmission (BIT) systems terminated onto network-node interfaces
(NNI)
• BIT accomplished with partially integrated access and segregated
switching

© P. Raatikainen


L1 - 35

Narrowband-integrated access
and broadband-integrated transmission

Signaling
switch

UNI

© P. Raatikainen

Circuit
switch
Packet
switch

Ad-hoc
switch

Data
Video

Circuit
switch
Packet
switch

ISDN
switch

Voice
Data

Signaling
switch

Ad-hoc
switch

Multifunctional
switch

NNI

NNI

Multifunctional
switch


ISDN
switch

Voice
Data

Data
Video
UNI

L1 - 36

Broadband network evolution (cont.)

• N-ISDN had some limitations:
– low bit rate channels
– no support for variable bit rates
– no support for large bandwidth services

• Connection oriented packet switching scheme, i.e., ATM (Asynchronous
Transfer Mode), was developed to overcome limitations of N-ISDN
=> B-ISDN concept
=> integrated broadband transport and switching (no more need for
specialized switching modules or dedicated networks)

© P. Raatikainen


L1 - 37

Broadband integrated transport

Voice
Data
Video

B-ISDN
switch
UNI

© P. Raatikainen

Voice
Data
Video

B-ISDN
switch
NNI

NNI


UNI

L1 - 38

OSI definitions for routing and switching

Routing on L3
L4

L4

L3

L3

L3

L3

L3

L3

L2

L2

L2

L2

L2

L2

Switching on L2
L4

L4

L3

L3

L3

L3

L3

L3

L2

L2

L2

L2

L2

L2

© P. Raatikainen


L1 - 39

Switching modes

• Circuit switching
• Cell and frame switching
• Packet switching
– Routing
– Layer 3 - 7 switching
– Label switching

© P. Raatikainen


L1 - 40

Circuit switching
• End-to-end circuit established for a connection
• Signaling used to set-up, maintain and release circuits
• Circuit offers constant bit rate and constant transport delay
• Equal quality offered to all connections
• Transport capacity of a circuit cannot be shared
• Applied in conventional telecommunications networks (e.g. PDH/PCM
and N-ISDN)

Layer 1

Limited error
detection

Layer 1

Network edge

Limited error
detection

Layer 1

Switching node

© P. Raatikainen

Layer 1

Network edge


L1 - 41

Cell switching

• Virtual circuit (VC) established for a connection
• Data transported in fixed length frames (cells), which carry information
needed for routing cells along established VCs
• Forwarding tables in network nodes

Layer 2 (H)
Layer 2 (L)
Layer 1

Network edge
© P. Raatikainen

Error recovery & flow control
Error & congestion
control
Limited error
detection

Layer 2 (L)

Layer 2 (L)

Layer 1

Layer 1

Switching node

Error & congestion
control
Limited error
detection

Layer 2 (H)
Layer 2 (L)
Layer 1

Network edge

L1 - 42

Cell switching (cont.)

• Signaling used to set-up, maintain and release VCs as well as update
forwarding tables
• VCs offer constant or variable bit rates and transport delay
• Transport capacity of links shared by a number of connections
(statistical multiplexing)
• Different quality classes supported
• Applied, e.g. in ATM networks

© P. Raatikainen


L1 - 43

Frame switching

• Virtual circuits (VC) established usually for virtual LAN connections
• Data transported in variable length frames (e.g. Ethernet frames), which
carry information needed for routing frames along established VCs

LLC
MAC
Layer 1

Network edge
© P. Raatikainen

Error recovery & flow control
Error & congestion
control
Limited error
detection

MAC

MAC

Layer 1

Layer 1

Switching node

Error & congestion
control
Limited error
detection

LLC
MAC
Layer 1

Network edge

L1 - 44

Frame switching (cont.)
• VCs based, e.g., on 12-bit Ethernet VLAN IDs (Q-tag) or 48-bit MAC
addresses
• Signaling used to set-up, maintain and release VCs as well as update
forwarding tables
• VCs offer constant or variable bit rates and transport delay
• Transport capacity of links shared by a number of connections
(statistical multiplexing)
• Different quality classes supported
• Applied, e.g. in offering virtual LAN services for business customers

© P. Raatikainen


L1 - 45

Packet switching

• No special transport path established for a connection
• Variable length data packets carry information used by network nodes
in making forwarding decisions
• No signaling needed for connection setup
Routing & mux
Layer 3
Layer 2
Layer 1

Network edge
© P. Raatikainen

Error recovery
&
flow control

Routing & mux
Layer 3

Layer 3

Layer 2

Layer 2

Layer 1

Layer 1

Switching node

Error recovery
&
flow control

Layer 3
Layer 2
Layer 1

Network edge
L1 - 46

Packet switching (cont.)

• Forwarding tables in network nodes are updated by routing protocols
• No guarantees for bit rate or transport delay
• Best effort service for all connections in conventional packet
switched networks
• Transport capacity of links shared effectively
• Applied in IP (Internet Protocol) based networks

© P. Raatikainen


L1 - 47

Layer 3 - 7 switching
• L3-switching evolved from the need to speed up (IP based) packet
routing
• L3-switching separates routing and forwarding
• A communication path is established based on the first packet
associated with a flow of data and succeeding packets are switched
along the path (i.e. software based routing combined with hardware
based one)
• Notice: In wire-speed routing traditional routing is implemented in
hardware to eliminate performance bottlenecks associated with software
based routing (i.e., conventional routing reaches/surpasses L3-switching
speeds)
© P. Raatikainen


L1 - 48

Layer 3 - 7 switching (cont.)

Layer 7

Layer 7

Layer 4
Layer 3
Layer 2

...

...

Routing info

• In L4 - L7 switching, forwarding decisions are based not only on MAC
address of L2 and destination/source address of L3, but also on
application port number of L4 (TCP/UDP) and on information of layers
above L4

Flow control
Routing

Routing

Layer 1

Network edge

Layer 3

Layer 3

Layer 2

Layer 2

Layer 1

Error recovery
&
flow control

Layer 1

Error recovery
&
flow control

Layer 3
Layer 2
Layer 1

Switching node

© P. Raatikainen

Layer 4

Network edge


L1 - 49

Label switching
• Evolved from the need to speed up connectionless packet switching and
utilize L2-switching in packet forwarding
• A label switched path (LSP) established for a connection
Flow control
Layer 3
Layer 2
Layer 1

Network edge
© P. Raatikainen

Error recovery
&
flow control

Layer 2

Layer 2

Layer 1

Layer 1

Switching node

Error recovery
&
flow control

Layer 3
Layer 2
Layer 1

Network edge

L1 - 50

Label switching (cont.)
• Signaling used to set-up, maintain and release LSPs
• A label is inserted in front of a L3 packet (behind L2 frame header)
• Packets forwarded along established LSPs by using labels in L2
frames
• Quality of service supported
• Applied, e.g. in ATM, Ethernet and PPP
• Generalized label switching scheme (GMPLS) extends MPLS to be
applied also in optical networks, i.e., enables light waves to be used
as LSPs

© P. Raatikainen


L1 - 51

Latest directions in switching
• The latest switching schemes developed to utilize Ethernet based
transport
• Scalability of the basic Ethernet concept has been the major problem,
i.e., 12-bit limitation of VLAN ID
• Modifications to the basic Ethernet frame structure have been proposed
to extend Ethernet’s addressing capability, e.g., Q-in-Q, Mac-in-Mac,
Virtual MAN and Ethernet-over-MPLS
• Standardization bodies favor concepts (such as Q-in-Q and VMAN) that
are backward compatible with the legacy Ethernet frame
• Signaling solutions still need further development

© P. Raatikainen


L1 - 52

Transmission techniques and
multiplexing hierarchies


© P. Raatikainen


L2 - 1

Transmission techniques and multiplexing
hierarchies
• Transmission of data signals
• Timing and synchronization
• Transmission techniques and multiplexing
–
–
–
–
–
–

PDH
ATM
IP/Ethernet
SDH/SONET
OTN
GFP

© P. Raatikainen


L2 - 2

Transmission of data signals
• Encapsulation of user data into layered protocol
structure
• Physical and link layers implement functionality that
have relevance to switching
–
–
–
–
–

multiplexing of transport signals (channels/connections)
medium access and flow control
error indication and recovery
bit, octet and frame level timing/synchronization
line coding (for spectrum manipulation and timing extraction)

© P. Raatikainen


L2 - 3

Encapsulation of user data

User data

TLH

NLH

LLH

PLH

© P. Raatikainen

Transport layer payload

•
•
•
•

error coding/indication
octet & frame synchronization
addressing
medium access & flow control

Network layer payload

Link layer payload

Physical layer


• line coding
• bit level timing
• physical signal generation/
recovery

L2 - 4

Synchronization of transmitted data

• Successful transmission of data requires bit, octet, frame
and packet level synchronism
• Synchronous systems (e.g. PDH and SDH) carry
additional information (embedded into transmitted line
signal) for accurate recovery of clock signals
• Asynchronous systems (e.g. Ethernet) carry additional bit
patterns to synchronize receiver logic

© P. Raatikainen


L2 - 5

Timing accuracy
• Inaccuracy of frequency classified in telecom networks to
– jitter (short term changes in frequency > 10 Hz)
– wander (< 10 Hz fluctuation)
– long term frequency shift (drift or skew)

• To maintain required timing accuracy, network nodes are
connected to a hierarchical synchronization network
– Universal Time Coordinated (UTC): error in the order of 10-13
– Error of Primary Reference Clock (PRC) of the telecom network in the
order of 10-11

© P. Raatikainen


L2 - 6

Timing accuracy (cont.)
• Inaccuracy of clock frequency causes
– degraded quality of received signal
– bit errors in regeneration
– slips: in PDH networks a frame is duplicated or lost due to timing
difference between the sender and receiver

• Based on applied synchronization method, networks are divided
into
– fully synchronous networks (e.g. SDH)
– plesiochronous networks (e.g. PDH), sub-networks have nominally the
same clock frequency but are not synchronized to each other
– mixed networks
© P. Raatikainen


L2 - 7

Methods for bit level timing
• To obtain bit level synchronism receiver clocks must be
synchronized to incoming signal
• Incoming signal must include transitions to keep receiver’s
clock recovery circuitry in synchronism
• Methods to introduce line signal transitions
– Line coding
– Block coding
– Scrambling

© P. Raatikainen


L2 - 8

Line coding
1

1

0

1

0

0

0

0

1

1

0

0

0

0

0

0

1

1

0

1

+V
Uncoded
+V
ADI
+V
ADI RZ
+V
AMI RZ
-V
ADI
- Alternate Digit Inversion
ADI RZ - Alternate Digit Inversion Return to Zero
AMI RZ - Alternate Mark Inversion Return to Zero

© P. Raatikainen


L2 - 9

Line coding (cont.)
• ADI, ADI RZ and codes alike introduce DC balance shift
=> clock recovery becomes difficult
• AMI and AMI RZ introduces DC balance, but lacks effective ability to
introduce signal transitions
• HDB3 (High Density Bipolar 3) code, used in PDH systems, guarantees a
signal transition at least every fourth bit
• 0000 coded by 000V when there is an odd number of pulses since the last violation (V) pulse
• 0000 coded by B00V when there is an even number of pulses since the last violation pulse

1
+V
HDB3
-V

© P. Raatikainen

1

0

1

0

0

0

0

1

1

0

0

0

0

0

0

1

1

0

1

V
B


V

L2 - 10

Line coding (cont.)
• When bit rates increase (> 100 Mbit/s) jitter requirements become tighter
and signal transitions should occur more frequently than in HDB3 coding
• CMI (Coded Mark Inversion) coding was introduced for electronic
differential links and for optical links
• CMI doubles bit rate on transmission link => higher bit rate implies larger
bandwidth and shortened transmission distance

1

1

0

1

0

0

0

0

1

1

0

0

0

0

0

0

1

1

0

1

+V

CMI
-V

© P. Raatikainen


L2 - 11

Block coding
•
•
•
•
•
•

Entire blocks of n bits are replaced by other blocks of m bits (m > n)
nBmB block codes are usually applied on optical links by using on-off
keying
Block coding adds variety of “1”s and “0”s to obtain better clock
synchronism and reduced jitter
Redundancy in block codes (in the form of extra combinations) enables
error recovery to a certain extent
When m>n the coded line signal requires larger bandwidth than the original
signal
Examples: 4B5B (FDDI), 5B6B (E3 optical links) and 8B10B (GbE)

© P. Raatikainen


L2 - 12

Coding examples
4B5B coding
Input
word
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Output
word
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101

© P. Raatikainen

5B6B coding
Other output words
00000
11111
00100
11000
10001
01101
00111
11001
00001
00010
00011
00101
00110
01000
01100
10000

Quiet line symbol
Idle symbol
Halt line symbol
Start symbol
Start symbol
End symbol
Reset symbol
Set Symbol
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid


Input word

Output word

00000
00001
00010
00011
...
11100
11101
11110
11111

101011
101010
101001
111000
...
010011
010111
011011
011100

L2 - 13

Scrambling
• Data signal is changed bit by bit according to a separate repetitive
sequence (to avoid long sequences of “1”s or “0”s)
• Steps of the sequence give information on how to handle bits in the
signal being coded
• A scrambler consists of a feedback shift register described by a
polynomial (xN + … + xm + … + xk + … + x + 1)
• Polynomial specifies from where in the shift register feedback is taken
• Output bit rate is the same as the input bit rate
• Scrambling is not as effective as line coding

© P. Raatikainen


L2 - 14

Scrambler example
SDH/STM-1 uses x7+x6+1 polynomial
Scrambler
x
Preset

0

D

x

1

D

Di

+
x

2

D

x

3

D

x

4

D

x

5

D

x

x

6

D

7

D

Si

+

Xi = Si⊕Di

Xi

Descrambler

Xi

+

x0
Preset

x1

x2

x3

x4

x5

x6

x7

D

D

D

D

D

D

D

D

Si

+

Ri = Si⊕Xi
= Si⊕(Si⊕Di) = Di

Ri =Di

© P. Raatikainen


L2 - 15

Methods for octet and frame level timing

• Frame alignment bit pattern
• Start of frame signal
• Use of frame check sequence

© P. Raatikainen


L2 - 16

Frame alignment sequence
• Data frames carry special frame alignment bit patterns to
obtain octet and frame level synchronism
• Data bits scrambled to avoid misalignment
• Used in networks that utilize synchronous transmission,
e.g. in PDH, SDH and OTN
• Examples
– PDH E1 frames carry bit sequence 0011011 in every other frame
(even frames)
– SDH and OTN frames carry a six octet alignment sequence
(hexadecimal form: F6 F6 F6 28 28 28) in every frame

© P. Raatikainen


L2 - 17

Start of frame signal
• Data frames carry special bit patterns to synchronize
receiver logic
• False synchronism avoided for example by inserting
additional bits into data streams
• Used in synchronous and asynchronous networks, e.g.,
Ethernet and HDLC
• Examples
– Ethernet frames are preceded by a 7-octet preamble field
(10101010) followed by a start-of-frame delimiter octet (10101011)
– HDLC frames are preceded by a flag byte (0111 1110)

© P. Raatikainen


L2 - 18

Frame check sequence
• Data frames carry no special bit patterns for
synchronization
• Synchronization is based on the use of error indication and
correction fields
– CRC (Cyclic Redundancy Check) calculation

• Used in bit synchronous networks such as ATM and GFP
(Generic Framing Procedures)
• Example
– ATM cells streams can be synchronized to HEC (Header Error
Control) field, which is calculated across ATM cell header

© P. Raatikainen


L2 - 19

Transmission techniques

• PDH (Plesiochronous Digital Hierarchy)
• ATM (Asynchronous Transfer Mode)
• IP/Ethernet
• SDH (Synchronous Digital Hierarchy)
• OTN (Optical Transport network)
• GFP (Generic Framing Procedure)

© P. Raatikainen


L2 - 20

Plesiochronous Digital Hierarchy (PDH)
• Transmission technology of the
digitized telecom network
• Basic channel capacity 64 kbit/s
• Voice information PCM coded
• 8 bits per sample
• A or µ law
• sample rate 8 kHz (125 µs)
• Channel associated signaling (SS7)
• Higher order frames obtained by
multiplexing four lower order frames
bit by bit and adding some synchr.
and management info
• The most common switching and
transmission format in the
telecommunication network is PCM 30
(E1)

© P. Raatikainen

139.264 Mbit/s

E4

1920 channels
x 4

34.368 Mbit/s

E3

480 channels
x 4

8.448 Mbit/s

E2

120 channels
x 4

2.048 Mbit/s

E1

...

64 kbit/s

E0

30 channels
x 32

1 channel


L2 - 21

PDH E1-frame structure (even frames)
Multi- frame
F0

F1

...

F14

Voice channels 1 - 15
T0

T1

T2

...

T0

Frame alignment time-slot
C

0

0

1

1

0

1

Frame alignment signal (FAS)
Error indicator
bit (CRC-4)

© P. Raatikainen

...

T15 T16 T17

T28 T29 T30 T31

Voice channel 28

Signaling time-slot
1

F15

0

0

0

Multi-frame
alignment bit
sequence in F0

0

1

A

1

Multi-frame
alarm


1

B1

Polarity

B2

B3

B4

B5

B6

B7

B8

Voice sample
amplitude

L2 - 22

PDH E1-frame structure (odd frames)
Multi- frame
F0

F1

...

F14

T0

T1

T2

...

T0

Frame alignment time-slot
C

1

A

D

Error indicator
bit (CRC-4)

© P. Raatikainen

D

D

D

F15

...

T15 T16 T17

T28 T29 T30 T31

Signaling time-slot
D

Data bits for
management
Far end
alarm indication

a

b

c

Channel 1
signaling
bits

d

a

b

c

c

Channel 16
signaling
bits


Nowadays, time slot 1
used for signaling and time
slot 16 for voice

L2 - 23

PDH-multiplexing
• Tributaries have the same nominal bit rate, but with a
specified, permitted deviation (100 bit/s for 2.048 Mbit/s)
• Plesiochronous = tributaries have almost the same bit rate
• Justification and control bits are used in multiplexed flows
• First order (E1) is octet-interleaved, but higher orders (E2,
…) are bit-interleaved

© P. Raatikainen


L2 - 24

PDH network elements
• concentrator
– n channels are multiplexed to a higher capacity link that carries m
channels (n > m)

• multiplexer
– n channels are multiplexed to a higher capacity link that carries n
channels

• cross-connect
– static multiplexing/switching of user channels

• switch
– switches incoming TDM/SDM channels to outgoing ones

© P. Raatikainen


L2 - 25

Example PDH network elements

...

n input
channels

Concentrator

n>m

Cross-connect

DXC

m output
channels

Switch

Multiplexer

n=m

© P. Raatikainen

m output
channels

3

2

1

4

3

2

1

4

...

n input
channels

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1


L2 - 26

Synchronous digital hierarchy
40 Gbit/s

STM-256

x 4

Major ITU-T SDH standards:
- G.707
- G.783

10 Gbit/s

STM-64

x 4
2.48 Gbit/s

STM-16

x 4

Notice that each frame
transmitted in 125 µs !

622 Mbit/s

STM-4

x 4

STM-1

© P. Raatikainen

155 Mbit/s


L2 - 27

SDH reference model
DXC
STM-n

MPX
R

STM-n

Regeneration
section
Multiplexing
section

STM-n

Regeneration
section

R

STM-n

Tributaries

Tributaries

MPX

Regeneration
section

Multiplexing section
Path layer connection

- DXC
- MPX
-R

© P. Raatikainen

Digital gross-connect
Multiplexer
Repeater


L2 - 28

SDH-multiplexing
•

Multiplexing hierarchy for plesiochronous and synchronous tributaries
(e.g. E1 and E3)

•

Octet-interleaving, no justification bits - tributaries visible and available in
the multiplexed SDH flow

•

SDH hierarchy divided into two groups:
– multiplexing level (virtual containers, VCs)
– line signal level (synchronous transport level, STM)

•

Tributaries from E1 (2.048 Mbit/s) to E4 (139.264 Mbit/s) are
synchronized (using justification bits if needed) and packed in containers
of standardized size

•

Control and supervisory information (POH, path overhead) added to
containers => virtual container (VC)

© P. Raatikainen


L2 - 29

SDH-multiplexing (cont.)
•
•
•
•

Different sized VCs for different tributaries (e.g. VC-12/E1, VC-3/E3,
VC-4/E4)
Smaller VCs can be packed into a larger VC (+ new POH)
Section overhead (SOH) added to larger VC
=> transport module
Transport module corresponds to line signal (bit flow transferred on
the medium)
– bit rate is 155.52 Mbit/s or its multiples
– transport modules called STM-N (N = 1, 4, 16, 64, ...)
– bit rate of STM-N is Nx155.52 Mbit/s
– duration of a module is 125 µs (= duration of a PDH frame)

© P. Raatikainen


L2 - 30

SDH network elements
• regenerator (intermediate repeater, IR)
– regenerates line signal and may send or receive data via
communication channels in RSOH header fields

• multiplexer
– terminal multiplexer multiplexes/demultiplexes PDH and SDH
tributaries to/from a common STM-n
– add-drop multiplexer adds or drops tributaries to/from a common STMn

• digital cross-connect
– used for rearrangement of connections to meet variations of capacity or
for protection switching
– connections set up and released by operator
© P. Raatikainen


L2 - 31

Example SDH network elements
Cross-connect
STM-n

STM-n

STM-n

DXC

STM-n

STM-n

Add-drop multiplexer
STM-n

ADM

Terminal multiplexer

STM-n

ADM

2 - 140 Mbit/s

© P. Raatikainen

STM-n

STM-n

2 - 140 Mbit/s


L2 - 32

Generation of STM-1 frame

Justification

PDH/E1

VC-12

+ POH

+ POH

© P. Raatikainen

STM-1

VC-4

MUX

+ SOH


L2 - 33

STM-n frame
Three main fields:
– Regeneration and multiplexer section overhead (RSOH and MSOH)
– Payload and path overhead (POH)
– AU (administrative) pointer specifies where payload (VC-4 or VC-3) starts
nx9 octets

3

AU-4 PTR

5

© P. Raatikainen

RSOH

1

nx261 octets

MSOH

P
O
H


L2 - 34

Synchronization of payload
• Position of each octet in a STM frame (or VC frame) has a number
• AU pointer contains position number of the octet in which VC starts
• Lower order VC included as part of a higher order VC (e.g. VC-12 as part
of VC-4)
VC-4 no. 0

RSOH

STM-1
no. k

AU-4 PTR

MSOH

VC-4 no. 1

RSOH

STM-1
no. k+1

AU-4 PTR

MSOH

© P. Raatikainen

VC-4 no. 2


L2 - 35

ATM concept in summary
• cell
– 53 octets

• routing/switching
– based on VPI and VCI

• adaptation
– processing of user data into ATM cells

• error control
– cell header checking and discarding

• flow control
– no flow control
– input rate control

• congestion control
– cell discarded (two priorities)
© P. Raatikainen


L2 - 36

ATM protocol reference model
AAL

Convergence sublayer (CS)
Segmentation and reassembly (SAR)
Generic flow control

ATM

VPI/VCI translation
Multiplexing and demultiplexing of cells
Cell rate decoupling
TC

HEC header sequence generation/verification
Cell delineation
Transmission frame adaptation

Phys

PM

Transmission frame generation/recovery

© P. Raatikainen

Timing
Physical medium


L2 - 37

Reference interfaces

NNI

UNI
EX

ATM
network

TE

NNI
UNI
EX
TE

© P. Raatikainen

-

Network-to-Network Interface
User Network Interface
Exchange Equipment
Terminal Equipment


L2 - 38

ATM cell structure
5 octets

48 octets

ATM
ATM
header
header

Cell payload
Cell payload

ATM header for UNI
GFC
GFC
VPI
VPI
VCI
VCI

VCI
VCI
HEC
HEC

VPI
VPI
VCI
VCI
PTI
PTI

CPL
CPL

ATM header for NNI
VPI
VPI
VCI
VCI

VPI
VPI
VCI
VCI
HEC
HEC

© P. Raatikainen

UNI
NNI
VPI
VCI
GFC
PTI
CPL
HEC

- User Network Interface
- Network-to-Network Interface
- Virtual Path Identifier
- Virtual Channel Identifier
- Generic Flow Control
- Payload Type Identifier
- Cell Loss Priority
- Header Error Control

VCI
VCI
PTI
PTI

CPL
CPL

HEC = 8 x (header octets 1 to 4) / (x8 + x2 + x + 1)


L2 - 39

ATM connection types

VCI 1
VCI 2

VPI 1

VPI 1

VCI 1
VCI 2

Physical channel
VCI 1
VCI 2

VPI 2

VPI 2

VCI k
VPI k

© P. Raatikainen

VCI 1
VCI 2

- Virtual Channel Identifier k
- Virtual Path Identifier k


L2 - 40

Physical layers for ATM
• SDH (Synchronous Digital Hierarchy)
– STM-1 155 Mbit/s
– STM-4 622 Mbit/s
– STM-16 2.4 Gbit/s

• PDH (Plesiochronous Digital Hierarchy)
– E1
– E3
– E4

2 Mbit/s
34 Mbit/s
140 Mbit/s

• TAXI 100 Mbit/s and IBM 25 Mbit/s
• Cell based interface
– uses standard bit rates and physical level interfaces
(e.g. E1, STM-1 or STM-4)
– HEC used for framing
© P. Raatikainen


L2 - 41

Transport of data in ATM cells

Network layer

IP packet

Pad 0 - 47 octets
(1+1+ 2) octets

ATM layer

Physical layer

© P. Raatikainen

4 octets

≤ 65 535

ATM
adaptation
layer (AAL)

AAL 5 payload

5
H

P

UU/
CPI/
LEN

CRC

48
Cell payload

P
UU
CPI
LEN

-

H

Cell payload

H

Cell payload

H

Cell payload

Padding octets
AAL layer user-to-user indicator
Common part indicator
Length indicator


L2 - 42

ATM cell encapsulation / SDH
9 octets

3

1

STM-1
frame

261 octets

VC-4
frame

SOH
AU-4 PTR

J1

...

B3

5

...

C2
G1

SOH

F2
H4

...

...
...

Z3
Z4

...

Z5

ATM cell

VC-4 POH

© P. Raatikainen


L2 - 43

ATM cell encapsulation / PDH (E1)
32 octets
TS0

Header

TS16

TS0

TS16

TS0

Header

TS16

TS0
TS0

Header

TS16
TS16

Head.

...
TS0
• frame alignment
• F3 OAM functions
• loss of frame alignment
• performance monitoring
• transmission of FERF and LOC
• performance reporting
© P. Raatikainen


TS16
• reserved for signaling

L2 - 44

Cell based interface
Frame structure for cell base interfaces:
1

27
P
L

IDLE or
PL-OAM

H

ATM layer

2
H

ATM layer

26

...

H

ATM layer

27
P
L

IDLE or
PL-OAM

• PL cells processed on physical layer (not on ATM layer)
• IDLE cell for cell rate adaptation
• PL-OAM cells carry physical level OAM information
(regenerator (F1) and transmission path (F3) level messages)
• PL cell identified by a pre-defined header
• 00000000 00000000 0000000 00000001 (IDLE cell)
• 00000000 00000000 0000000 00001001 (phys. layer OAM)
• xxxx0000 00000000 0000000 0000xxxx (reserved for phys. layer)
H = ATM cell Header, PL = Physical Layer, OAM = Operation Administration and Maintenance
© P. Raatikainen


L2 - 45

ATM network elements
• Gross-connect
– switching of virtual paths (VPs)
– VP paths are statically connected

• Switch
– switching of virtual channel (VCs)
– VC paths are dynamically or statically connected

• DSLAM (Digital Subscriber Line Access Multiplexer)
– concentrates a larger number of sub-scriber lines to a common higher
capacity link
– aggregated capacity of subscriber lines surpasses that of the common
link
© P. Raatikainen


L2 - 46

Ethernet
• Originally a link layer protocol for LANs (10 and 100 MbE)
• Upgrade of link speeds
=> optical versions 1GbE and 10 GbE
=> suggested for long haul transmission
• No connections - each data terminal (DTE) sends data
when ready - MAC is based on CSMA/CD
• Synchronization
– line coding, preamble pattern and start-of-frame delimiter
– Manchester code for 10 MbE, 8B6T for 100 MbE,
8B10B for GbE
© P. Raatikainen


L2 - 47

Ethernet frame
64 - 1518 octets

Preamble

S
F
D

DA

SA

7

1

6

6

T/L

Payload

CRC

2

46 - 1500

4

Preamble - AA AA AA AA AA AA AA (Hex)
SFD - Start of Frame Delimiter AB (Hex)
DA - Destination Address
SA - Source Address
T/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator
CRC - Cyclic Redundance Check
Inter-frame gap 12 octets (9,6 µs /10 MbE)
© P. Raatikainen


L2 - 48

1GbE frame
512 - 1518 octets

Preamble

7

S
F
D

DA

SA

1

6

6

L

2

Payload
46 - 1500

CRC

Extension

4

Preamble - AA AA AA AA AA AA AA (Hex)
SFD - Start of Frame Delimiter AB (Hex)
DA - Destination Address
SA - Source Address
T/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicator
CRC - Cyclic Redundancy Check
Inter-frame gap 12 octets (96 ns /1 GbE)
Extension - for padding short frames to be 512 octets long
© P. Raatikainen


L2 - 49

Ethernet network elements
• Repeater
– interconnects LAN segments on physical layer
– regenerates all signals received from one segment and forwards them onto
the next

• Bridge
– interconnects LAN segments on link layer (MAC)
– all received frames are buffered and error free ones are forwarded to another
segment (if they are addressed to it)

• Hub and switch
– hub connects DTEs with two twisted pair links in a star topology and repeats
received signal from any input to all output links
– switch is an intelligent hub, which learns MAC addresses of DTEs and is
capable of directing received frames only to addressed ports
© P. Raatikainen


L2 - 50

Optical transport network
• Optical Transport Network (OTN), being developed by ITU-T
(G.709), specifies interfaces for optical networks
• Goal to gather for the transmission needs of today’s wide
range of digital services and to assist network evolution to
higher bandwidths and improved network performance
• OTN builds on SDH and introduces some refinements:
– management of optical channels in optical domain
– FEC to improve error performance and allow longer link spans
– provides means to manage optical channels end-to-end in optical
domain (i.e. no O/E/O conversions)
– interconnections scale from a single wavelength to multiple ones
© P. Raatikainen


L2 - 51

OTN reference model
OMPX
OA

OTS

Optical
channels

Optical
channels

OMPX
OA

OTS

OTS

OMS
OCh

- OCh
- OA
- OMS
- OMPX
- OTS
© P. Raatikainen

Optical Channel
Optical Amplifier
Optical Multiplexing Section
Optical Multiplexer
Optical Transport Section

L2 - 52

OTN layers and OCh sub-layers

SONET/
SDH

ATM

Ethernet

IP

OPU
Optical channel payload unit
ODU
Optical channel data unit

Optical channel

OTU
Optical channel transport unit

Optical multiplexing section
(OMSn)
Optical transport section
(OTSn)

© P. Raatikainen


L2 - 53

OTN frame structure
• Three main fields
– Optical channel overhead
– Payload
– Forward error indication field
GbE

IP

FR

SONET/SDH

ATM

GbE

IP

ATM/FR
SONET/SDH
DWDM

Och

Payload

FEC

Client
Digital wrapper
© P. Raatikainen


L2 - 54

OTN frame structure (cont.)
4080 bytes

4 rows

1

16

17

...................................

Och
overhead

1

1

.....

.....

7

8

.....

14

4

...

4080

FEC

15 ... 16

• Frame size remains the same (4x4080)
regardless of line rate
=> frame rate increases as line rate increases
• Three line rates defined:
• OTU1 2.666 Gbit/s

OTU overhead

OPU
overh.

ODU
overhead

3

3825

Payload

Frame alignmt.

2

3824

OTU - Optical transport unit
ODU - Optical data unit
OPU - Optical payload unit
FEC - Forward error correction

© P. Raatikainen


L2 - 55

Generation of OTN frame and signal
OTN frame generation
Client signal

OPU

ODU
+ OPU-OH

OTU
+ OTU-OH
+ FEC

OTN signal generation
Client signal

© P. Raatikainen

…

Client signal

OCh
OMUX

OMS

OTS

OCh


L2 - 56

OTN network elements
• optical amplifier
– amplifies optical line signal

• optical multiplexer
– multiplexes optical wavelengths to OMS signal
– add-drop multiplexer adds or drops wavelengths to/from a common OMS

• optical cross-connect
– used to direct optical wavelengths (channels) from an OMS to another
– connections set up and released by operator

• optical switches ?
– when technology becomes available optical switches will be used for
switching of data packets in the optical domain

© P. Raatikainen


L2 - 57

Generic Framing Procedure (GFP)
• Recently standardized traffic adaptation mechanism especially for
transporting block-coded and packet-oriented data
• Standardized by ITU-T (G.7041) and ANSI (T1.105.02) (the only
standard supported by both organizations)
• Developed to overcome data transport inefficiencies of existing ATM,
POS, etc. technologies
• Operates over byte-synchronous communications channels (e.g.
SDH/SONET and OTN)
• Supports both fixed and variable length data frames
• Generalizes error-control-based frame delineation scheme (successfully
employed in ATM)
– relies on payload length and error control check for frame boundary
delineation
© P. Raatikainen


L2 - 58

GFP (cont.)
• Two frame types: client and control frames
– client frames include client data frames and client management frames
– control frames used for OAM purposes

• Multiple transport modes (coexistent in the same channel) possible
– Frame-mapped GFP for packet data, e.g. PPP, IP, MPLS and Ethernet)
– Transparent-mapped GFP for delay sensitive traffic (storage area
networks), e.g. Fiber Channel, FICON and ESCON

© P. Raatikainen


L2 - 59

GFP frame types

GFP frames

Client frames

Client
data frames

© P. Raatikainen

Control frames

Client
management frames

Idle frames


OA&M frames

L2 - 60

GFP client data frame
• Composed of a frame header and payload
• Core header intended for data link management
– payload length indicator (PLI, 2 octets), HEC (CRC-16, 2 octets)

• Payload field divided into payload header, payload and optional FCS
(CRC-32) sub-fields
• Payload header includes:
– payload type (2 octets) and type HEC (2 octets) sub-fields
– optional 0 - 60 octets of extension header

• Payload:
– variable length (0 - 65 535 octets, including payload header and FCS) for
frame mapping mode (GFP-F) - frame multiplexing
– fixed size Nx[536, 520] for transparent mapping mode (GFP-T) - no frame
multiplexing
© P. Raatikainen


L2 - 61

GFP frame structure

Payload length indicator

Core
header

Core HEC

PFI

EXI

UPI

Type HEC
CID

Payload header

Payload
area

PTI
Payload type

0 – 60 bytes
extension header
(optional)

Spare
Extension HEC MSB
Extension HEC LSB

Payload

[N x 536, 520 bytes
or variable length
packet]

Payload FCS

CID - Channel identifier
FCS - Frame Check Sequence
EXI - Extension Header Identifier
HEC - Header Error Check
PFI - Payload FCS Indicator
PTI - Payload Type Indicator
UPI - User payload Identifier

Source: IEEE Communications Magazine, May 2002

© P. Raatikainen


L2 - 62

GFP
client-dependent

Frame
mapped

Other
client
signals

ESCON

FICON

Fiber
Channel

RPR

MAPOS

IP/PPP

Ethernet

GFP relationship to client signals and
transport paths

Transparent
mapped

GFP
client-independent
SDH/SONET path

ESCON
FICON
IP/PPP
MAPOS
RPR

-

OTN ODUk path

Enterprise System CONnection
Fiber CONnection
IP over Point-to-Point Protocol
Multiple Access Protocol over SONET/SDH
Resilient Packet Ring

Source: IEEE Communications Magazine, May 2002

© P. Raatikainen


L2 - 63

Adapting traffic via GFP-F and GFP-T

GFP-F frame
PLI

cHEC

2 bytes 2 bytes

Payload
header

Client PDU
(PPP, IP, Ethernet, RPR, etc.)

4 bytes

FCS
(optional)
4 bytes

GFP-T frame
PLI

cHEC

2 bytes 2 bytes

FCS
cHEC
PDU
PLI

Payload
header
4 bytes

8x64B/65B superblock #1

#2

... #N-1 #N

FCS
(optional)
4 bytes

- Frame Check Sequence
- Core Header Error Control
- Packet Data Unit
- Payload Length Indicator

© P. Raatikainen


L2 - 64

GFP-T frame mapping
64B/65B code block
8B

8B

8B

8B

8B

8B

8B

8B

8 x 64B/65B code blocks

Superblock (8 x 64B/65B code blocks + CRC-16)
CRC-16

GFP-T frame with five superblocks

Core header and payload header

© P. Raatikainen

FCS (optional)


L2 - 65

Switch Fabrics


© P. Raatikainen


3-1

Switch fabrics
•
•
•
•
•
•

Basic concepts
Time and space switching
Two stage switches
Three stage switches
Cost criteria
Multi-stage switches and path search

© P. Raatikainen


3-2

1

Switch fabrics
•
•
•
•
•

Multi-point switching
Self-routing networks
Sorting networks
Fabric implementation technologies
Fault tolerance and reliability

© P. Raatikainen


3-3

Basic concepts
•
•
•
•
•
•

Accessibility
Blocking
Complexity
Scalability
Reliability
Throughput

© P. Raatikainen


3-4

2

Accessibility

• A network has full accessibility when each inlet can
be connected to each outlet (in case there are no
other I/O connections in the network)
• A network has a limited accessibility when the
above given property does not exist
• Interconnection networks applied in today’s switch
fabrics usually have full accessibility

© P. Raatikainen


3-5

Blocking
• Blocking is defined as failure to satisfy a connection requirement
and it depends strongly on the combinatorial properties of the
switching networks

Network class

Network state

Strict-sense
non-blocking
Non-blocking

Network type

Without blocking
states

Wide-sense
non-blocking
Rearrangeably
non-blocking

Blocking

© P. Raatikainen

With
blocking
state

Others


3-6

3

Blocking (cont.)
•
•
•
•

•

Non-blocking - a path between an arbitrary idle inlet and arbitrary idle
outlet can always be established independent of network state at set-up
time
Blocking - a path between an arbitrary idle inlet and arbitrary idle outlet
cannot be established owing to internal congestion due to the already
established connections
Strict-sense non-blocking - a path can always be set up between any
idle inlet and any idle outlet without disturbing paths already set up
Wide-sense non-blocking - a path can be set up between any idle
inlet and any idle outlet without disturbing existing connections,
provided that certain rules are followed. These rules prevent network
from entering a state for which new connections cannot be made
Rearrangeably non-blocking - when establishing a path between an
idle inlet and an idle outlet, paths of existing connections may have to
be changed (rearranged) to set up that connection

© P. Raatikainen


3-7

Complexity
• Complexity of an interconnection network is expressed by
cost index
• Traditional definition of cost index gives the number of crosspoints in a network
– used to be a reasonable measure of space division switching
systems

• Nowadays cost index alone does not characterize cost of an
interconnection network for broadband applications
– VLSIs and their integration degree has changed the way how
cost of a switch fabric is formed (number of ICs, power
consumption)
– management and control of a switching system has a significant
contribution to cost

© P. Raatikainen


3-8

4

Scalability
• Due to constant increase of transport links and data rates on
links, scalability of a switching system has become a key
parameter in choosing a switch fabric architecture
• Scalability describes ability of a system to evolve with
increasing requirements
• Issues that are usually matter of scalability
–
–
–
–
–
–

number of switching nodes
number of interconnection links between nodes
bandwidth of interconnection links and inlets/outlets
throughput of switch fabric
buffering requirements
number of inlets/outlets supported by switch fabric

© P. Raatikainen


3-9

Reliability
• Reliability and fault tolerance are system measures that have an
impact on all functions of a switching system
• Reliability defines probability that a system does not fail within a
given time interval provided that it functions correctly at the start
of the interval
• Availability defines probability that a system will function at a
given time instant
• Fault tolerance is the capability of a system to continue its
intended function in spite of having a fault(s)
• Reliability measures:
– MTTF (Mean Time To Failure)
– MTTR (Mean Time To Repair)
– MTB (Mean Time Between Failures)
© P. Raatikainen


3 - 10

5

Throughput

• Throughput gives forwarding/switching speed/efficiency of a
switch fabric
• It is measured in bits/s, octets/s, cells/s, packet/s, etc.
• Quite often throughput is given in the range (0 ... 1.0], i.e. the
obtained forwarding speed is normalized to the theoretical
maximum throughput

© P. Raatikainen


3 - 11

Switch fabrics
•
•
•
•
•
•

Basic concepts
Two stage switches
Cost criteria

© P. Raatikainen


3 - 12

6

Switching mechanisms
• A switched connection requires a mechanism that
attaches the right information streams to each other
• Switching takes place in the switching fabric, the
structure of which depends on network’s mode of
operation, available technology and required capacity
• Communicating terminals may use different physical
links and different time-slots, so there is an obvious
need to switch both in time and in space domain
• Time and space switching are basic functions of a
switch fabric
© P. Raatikainen


3 - 13

Space division switching
• A space switch directs traffic from input links to output links
• An input may set up one connection (1, 3, 6 and 7), multiple
connections (4) or no connection (2, 5 and 8)
INPUTS

OUTPUTS

1
2
3
4
5
6
7
8

1
2
3
4
5
6

m INPUT LINKS

© P. Raatikainen

INTERCONNECTION
NETWORK

n OUTPUT LINKS


3 - 14

7

Crossbar switch matrix

m INPUT LINKS

• Crossbar matrix introduces the basic structure of a space switch
• Information flows are controlled (switched) by opening and closing
cross-points
• m inputs and n outputs => mn cross-points (connection points)
• Only one input can be connected to an output at a time, but an input
can be connected to multiple outputs (multi-cast) at a time
1
2
3
4
5
6
7
8

MULTI-CAST

A CLOSED CROSS-POINT
1

2

3

4

5

6

n OUTPUT LINKS

© P. Raatikainen


3 - 15

An example space switch
• m x1 -multiplexer used to implement a space switch
• Every input is fed to every output mux and mux control signals
are used to select which input signal is connected through
each mux
mux/connection control
1
2
m
mx1

1
© P. Raatikainen

mx1

2

mx1

m

3 - 16

8

Time division multiplexing
• Time-slot interchanger is a device, which buffers m incoming timeslots, e.g. 30 time-slots of an E1 frame, arranges new transmit
order and transmits n time-slots
• Time-slots are stored in buffer memory usually in the order they
arrive or in the order they leave the switch - additional control logic
is needed to decide respective output order or the memory slot
where an input slot is stored
TIME-SLOT INTERCHANGER

Time-slot 1

INPUT CHANNELS
6

5

4

3

2

1

OUTPUT CHANNELS

Time-slot 2

5

Time-slot 3

1

3

2

6

4

Time-slot 4
Time-slot 5
Time-slot 6

© P. Raatikainen

BUFFER SPACE FOR TIME-SLOTS


3 - 17

Time-slot interchange

BUFFER FOR m
INPUT/OUTPUT SLOTS

(3)
8

(2)
7

6

5

(4) (1,6) (5)
4

3

2

1

1
2
3
4
5
6

6

5

4

3

2

1

n OUTPUT LINKS

m INPUT LINKS

DESTINATION OUTPUT #

7
8

© P. Raatikainen


3 - 18

9

Time switch implementation example 1
• Incoming time-slots are written cyclically into switch memory
• Output logic reads cyclically control memory, which contains a pointer for
each output time-slot
• Pointer indicates which input time-slot to insert into each output time-slot

…

3

2

1

Cyclic read

Switch
memory
1
2
3

Control
memory
1
2
3

write
address (3)

.
.
.

k

.
.
.

Outgoing frame buffer
n …

j

…

2

1

Cyclic write

.
.
.

read
address (k)

m

j (k)

.
.
.

n

read/write
address (j)

Incoming frame buffer
m

Time-slot counter & R/W control

© P. Raatikainen


3 - 19

Time switch implementation example 2
• Incoming time-slots are written into switch memory by using write-addresses
read from control memory
• A write address points to an output slot to which the input slot is addressed
• Output time-slots are read cyclically from switch memory

…

3

2

read
address (3)

Cyclic read

1

Control
memory
1
2
3 (k)

write
address (k)

Switch
memory
1
2
3

.
.
.

.
.
.

k

m

n

.
.
.

Outgoing frame buffer
n …

j

…

2

1

Cyclic write

read/write
address (2)

Incoming frame buffer
m

Time-slot counter & R/W control

© P. Raatikainen


3 - 20

10

Properties of time switches
• Input and output frame buffers are read and written at wire-speed,
i.e. m R/Ws for input and n R/Ws for output
• Interchange buffer (switch memory) serves all inputs and outputs
and thus it is read and written at the aggregate speed of all inputs
and outputs
=> speed of an interchange buffer is a critical parameter in time
switches and limits performance of a switch
• Utilizing parallel to serial conversion memory speed requirement
can be cut
• Speed requirement of control memory is half of that of switch
memory (in fact a little moor than that to allow new control data to
be updated)

© P. Raatikainen


3 - 21

Time-Space analogy
• A time switch can be logically converted into a space switch by
setting time-slot buffers into vertical position => time-slots can be
considered to correspond to input/output links of a space switch
• But is this logical conversion fair ?

1

…

3

2

© P. Raatikainen

1

n

…

3

2

1


2
3
…

m

3

m

Time switch

1

2

…

Space switch

m

3 - 22

11

Space-Space analogy
• A space switch carrying time multiplexed input and output signals can be
logically converted into a pure space switch (without cyclic control) by
distributing each time-slot into its own space switch
1

1

…

1

1
2

1
2
…

…

m

n

n

1
2

…

m

2
…

2

2

m

1
2
…

Inputs and outputs are
time multiplexed signals
(K time-slots)

n

…

© P. Raatikainen

m

1
2
…

K

…

To switch a time-slot, it is enough
to control one of the K boxes

1
2

n


3 - 23

1

1
2

1
2

m

…

2

…

K multiplexed
input signals
on each link

An example conversion

m

n
mxn
1
2

KxK

nxm

1

1

1

m
1
2

2

2

2

m

…

…

K

n

K

m

© P. Raatikainen

1
2
m

…

1
2

1
2
m

1
2
m


3 - 24

12

Properties of space and time switches
Space switches

Time switches

• number of cross-points (e.g.
AND-gates)
- m input x n output = mn
- when m=n => n2
• output bit rate determines the
speed requirement for the
switch components
• both input and output lines
deploy “bus” structure
=> fault location difficult

© P. Raatikainen

• size of switch memory (SM)
and control memory (CM)
grows linearly as long as
memory speed is sufficient, i.e.
- SM = 2 x number of time-slots
- CM = 2 x number of time-slots
• a simple and cost effective
structure when memory speed
is sufficient
• speed of available memory
determines the maximum
switching capacity


3 - 25

Switch fabrics
•
•
•
•
•
•

Basic concepts
Two stage switches
Cost criteria

© P. Raatikainen


3 - 26

13

A switch fabric as a combination of
space and time switches
• Two stage switches
•
•
•
•

Time-Time (TT) switch
Time-Space (TS) switch
Space-Time (SP) switch
Space-Apace (SS) switch

• TT-switch gives no advantage compared to a single
stage T-switch
• SS-switch increases blocking probability

© P. Raatikainen


3 - 27

A switch fabric as a combination of
space and time switches (cont.)
• ST-switch gives high blocking probability (S-switch can
develop blocking on an arbitrary bus, e.g. slots from two
different buses attempting to flow to a common output)
• TS-switch has low blocking probability, because T-switch
allows rearrangement of time-slots so that S-switching can
be done blocking free
TS-switch

ST-switch

TS n
TS n

n

© P. Raatikainen

1
2

1
2

n

n

…
…

TS n

…

…

…
…

1
2

TS 1
TS 2
TS 1
TS 1
TS 2
TS 2

…

…

TS 1
TS 2
TS 1
TS 1
TS 2
TS 2

TS n

TS n
TS n


1
2
n

3 - 28

14

Time multiplexed space (TMS) switch
• Space divided inputs and each of them
carry a frame of three time-slots
• Input frames on each link are
synchronized to the crossbar
• A switching plane for each
time-slot to direct incoming
TS3
es
slots to destined output
ram
4
gf
links of the
in
2
3
om
Inc
corresponding
3
2
1
4
1
time-slot

Outputs
1

1

e
ac
Sp
3
4

2

3

4

2

4x4 plane for slot 1

TS2 TS1
1

T
i
m
e

1

2

2
3
4


Output link address

1
2
3

Cross-point closed

© P. Raatikainen

4



3 - 29

Connection conflicts in a TMS switch
• Space divided inputs and each of them
carry a frame of three time-slots
• Input frames on each link are
synchronized to the crossbar
• A switching plane for each
time-slot to direct incoming
TS3
s
me
slots to destined output
4
fra
ing
2
3
links of the
om
Inc
3
2
1
corresponding
4
1
time-slot
Conflict solved
by time-slot
interchange

Outputs
1

e
ac
Sp
3
4

2

3

4

2


TS2 TS1
1

1

4

T
i
m
e

1

2

2
3
4

1
2

Connection
conflict

3
4


Cross-point closed

© P. Raatikainen


3 - 30

15

TS switch interconnecting TDM links

1

OUTPUTS OF 4x4 TMS

SL
O
T

2

PL
AN
E

FO
R

SL
OT

SPACE

FO
R

1

TIME

PL
AN
E

2
3

FO
R

SL
O
T

3

• Time division switching
applied prior to space
switching
• Incoming time-slots can
always be rearranged such
that output requests become
conflict free for each slot of
a frame, provided that the
number of requests for each
output is no more than the
number of slots in a frame

© P. Raatikainen

PL
AN
E

3x3 TSI


3 - 31

SS equivalent of a TS-switch
3x3
S-SWITCH
PLANES

4x4
S-SWITCH
PLANES

4 PLANES

4

O

UT
P

UT
S

3 INPUTS

3 PLANES

© P. Raatikainen


3 - 32

16

Connections through SS-switch
Example connections:
- (1, 3, 1) => (2, 1, 2)
- (1, 4, 2) => (2, 3, 4)

Coordinate (X, Y, Z)
stage
plane
input/output port

3x3
S-SWITCH
PLANES

4x4
S-SWITCH
PLANES

(2, 1, 2)

4 PLANES

(1, 3, 1)

(1, 4, 2)
(2, 3, 4)

© P. Raatikainen


3 - 33

Switch fabrics
•
•
•
•
•
•

Basic concepts
Two stage switches
Cost criteria

© P. Raatikainen


3 - 34

17

• Basic TS-switch sufficient for switching time-slots onto addressed
outputs, but slots can appear in any order in the output frame
• If a specific input slot is to carry data of a specific output slot then a
time-slot interchanger is needed at each output
=> any time-slot on any input can be connected to any time-slot on any output
=> blocking probability minimized

• Such a 3-stage configuration is named TST-switching
(equivalent to 3-stage SSS-switching)

TS 1
TS 1
TS 2
TS 2

TS n

TS n
TS n

TS 1
TS 2

…

TS 2

…
…

© P. Raatikainen

TS 1

…

n

…
…

1
2

TS 1
TS 1
TS 2
TS 2

…

…

TST-switch:

TS n

TS n
TS n

1
2

n


3 - 35

SSS presentation of TST-switch

3x3
T- or S-SWITCH
PLANES

4x4
S-SWITCH
PLANES

3x3
T- or S-SWITCH
PLANES

4 PLANES

4 PLANES

INPUTS

© P. Raatikainen

3 HORIZONTAL
PLANES

OUTPUTS


3 - 36

18

Three stage switch combinations
• Possible three stage switch combinations:
• Time-Time-Time (TTT) ( not significant, no connection from
PCM to PCM)
• Time-Time-Space (TTS) (=TS)
• Time-Space-Time (TST)
• Time-Space-Space (TSS)
• Space-Time-Time (STT) (=ST)
• Space-Time-Space (STS)
• Space-Space-Time (SST) (=ST)
• Space-Space-Space (SSS) (not significant, high probability
of blocking)

• Three interesting combinations TST, TSS and STS
© P. Raatikainen


3 - 37

Time-Space-Space switch
• Time-Space-Space switch can be applied to increase switching
capacity
…

…

n

…
…

1
2

TS n

n

TS 1
TS 2

…

TS 1
TS 1
TS 2
TS 2

…
…

n

1
2

TS n
TS n

…

1
2

TS 1
TS 2

TS 1
TS 1
TS 2
TS 2

1
2

TS n

TS n
TS n

© P. Raatikainen

n


3 - 38

19

Space-Time-Space switch

• Space-Time-Space switch has a high blocking probability (like
ST-switch) - not a desired feature in public networks

…

© P. Raatikainen

…

n

…
…

1
2

TS 1
TS 2

TS 1
TS 1
TS 2
TS 2

TS n

TS n
TS n


1
2
n

3 - 39

Graph presentation of space switch
• A space division switch can be presented by a graph G = (V, E)
- V is the set of switching nodes
- E is the set of edges in the graph
• An edge e ∈E is an ordered pair (u,v) ∈V
- more than one edge can exist between u and v
- edges can be consider to be bi-directional
• V includes two special sets (T and R) of nodes not considered
part of switching network
- T is a set of transmitting nodes having only outgoing edges
(input nodes to switch)
- R is a set of receiving node having only incoming edges (output
nodes from switch)
© P. Raatikainen


3 - 40

20

Graph presentation of space
switch (cont.)
• A connection requirement is specified for each t ∈T by subset Rt∈R
to which t must be connected
- subsets Rt are disjoint for different t
- in case of multi-cast Rt contains more than one element for each t
• A path is a sequence of edges (t,a), (a,b), (b,c), … ,(f,g), (g,r) ∈E,
∈
t ∈T, r∈R and a,b,c,…,f,g are distinct elements of V - (T+R)
• Paths originating from different t may not use the same edge
• Paths originating from the same t may use the same edges

© P. Raatikainen


3 - 41

Graph presentation example
INPUT NODES t

t1
t2
t3

s1

OUTPUT NODES r

u1

s2

v2
u2

s4
s5

v3

r1
r2
r3

...

...

s3

v1

v4
u3

t15

v5
r15

V = (t1, t2 ,... t15, s1, s2 ,... s5 , u1, u2 , u3 , v1, v2 ,... v5 , r1, r2 ,... r15)
E = {(t1, s1), ...(t15 , s5), (s1, u1), (s1, u2) ,... (s5, u3), (u1, v1 ), (u1, v2 ), ... (u3, v5 ),
(v1, r1 ), (v1, r2 ),... (v5, r15)}
© P. Raatikainen


3 - 42

21

SSS-switch and its graph presentation

INPUTS t
3x3
S-SWITCH
PLANES

5
PLANE
S

5x5
S-SWITCH
PLANES

OUTPUTS r

3x3
S-SWITCH
PLANES

5
PLANES
INPUTS

3 HORIZONTAL
PLANES

© P. Raatikainen

OUTPUTS


3 - 43

Graph presentation of connections
INPUTS t

OUTPUTS r

A TREE

A PATH

© P. Raatikainen


3 - 44

22

Switch Fabrics


© P. Raatikainen


4-1

Switch fabrics
•
•
•
•
•
•

Basic concepts
Two stage switches
Cost criteria

© P. Raatikainen


4-2

1

Cost criteria for switch fabrics

•
•
•
•
•
•
•

Number of cross-points
Fan-out
Logical depth
Blocking probability
Complexity of switch control
Total number of connection states
Path search

© P. Raatikainen


4-3

Cross-points
•

Number of cross-points gives the number of on-off gates
(usually “and-gates”) in space switching equivalent of a fabric
• minimization of cross-point count is essential when cross-point
technology is expensive (e.g. electro-mechanical and optical
cross-points)
• Very Large Scale Integration (VLSI) technology implements
cross-point complexity in Integrated Circuits (ICs)
=> more relevant to minimize number of ICs than number of
cross-points
• Due to increasing switching speeds, large fabric constructions
and increased integration density of ICs, power consumption has
become a crucial design criteria
- higher speed => more power
- large fabrics => long buses, fan-out problem and more driving power
- increased integration degree of ICs => heating problem

© P. Raatikainen


4-4

2

Fan-out and logical depth
•

VLSI chips can hide cross-point complexity, but introduce
pin count and fan-out problem
•
•
•
•

•

length of interconnections between ICs can be long lowering
switching speed and increasing power consumption
parallel processing of switched signals may be limited by the
number of available pins of ICs
fan-out gives the driving capacity of a switching gate, i.e. number
of inputs (gates/cross-points) that can be connected to an output
long buses connecting cross-points may lower the number of gates
that can be connected to a bus

Logical depth gives the number of cross-points a signal
traverses on its way through a switch
•

large logical depth causes excessive delay and signal deterioration

© P. Raatikainen


4-5

Blocking probability
•
•
•

Blocking probability of a multi-stage switching network
difficult to determine
Lee’s approximation gives a coarse measure of blocking
Assume uniformly distributed load
•
•

Probability that an input is
engaged is a = λS where
- λ = input rate on an input link
- S = average holding time of a link
© P. Raatikainen

n

1
2

nxk


kxn

1
n

...

•

equal load in each input
load distributed uniformly among
intermediate stages (and their
outputs) and among outputs
1
of the switch

k

4-6

3

Blocking probability (cont.)
•

•

•

Under the assumption of uniformly distributed load,
probability that a path between any two switching blocks
≥
is engaged is p = an/k (k≥n)
Probability that a certain path from an input block to an
output block is engaged is 1 - (1-p)2 where the last term is
the probability that both (input and output) links are
disengaged
Probability that all k paths between an input switching
block and an output switching block are engaged is
B = [1 - (1- an/k )2 ]k
which is known as Lee’s approximation
© P. Raatikainen


4-7

Control complexity
•

Give a graph G , a control algorithm is needed to find and set up
paths in G to fulfill connection requirements

•

Control complexity is defined by the hardware (computation and
memory) requirements and the run time of the algorithm

•

Amount of computation depends on blocking category and degree of
blocking tolerated

•

In general, computation complexity grows exponentially as a function
of the number of terminal

•

There are interconnection networks that have a regular structure for
which control complexity is substantially reduced

•

There are also structures that can be distributed over a large number
of control units
© P. Raatikainen


4-8

4

Management complexity
•
•

Network management involves adaptation and maintenance of a
switching network after the switching system has been put in place
Network management deals with
• failure events and growth in connectivity demand
• changes of traffic patterns from day to day
• overload situations
• diagnosis of hardware failures in switching system, control system
as well as in access and trunk network
- in case of failure, traffic is rerouted through redundant built-in
hardware or via other switching facilities
- diagnosis and failure maintenance constitute a significant part of
software of a switching system
•

In order for switching cost to grow linearly in respect to total traffic,
switching functions (such as control, maintenance, call processing and
interconnection network) should be as modular as possible

© P. Raatikainen


4-9

Example 1
•

A switch with
•
•
•
•

a capacity of N simultaneous calls
average occupancy on lines during busy hour is X Erlangs
Y % requirement for internal use
notice that two (one-way) connections are needed for a call

requires a switch fabric with M = 2 x [(100+Y)/100] x(N/X) inputs
and outputs.
•

If N = 20 000, X = 0.72 and Y = 10%
=> M = 2 x 1.1 x 20 000/0.72 = 61 112
=> corresponds to 2038 E1 links

1

2

2
M

© P. Raatikainen


1

M

4 - 10

5

Amount of traffic in Erlangs
Erlang defines the amount of traffic flowing through a
communication system - it is given as the aggregate holding time of
all channels of a system divided by the observation time period
• Example 1:
- During an hour period three calls are made (5 min, 15 min and 10
min) using a single telephone channel => the amount of traffic
carried by this channel is (30 min/60 min) = 0.5 Erlang
• Example 2:
- a telephone exchange supports 1000 channels and during a busy
hour (10.00 - 11.00) each channel is occupied 45 minutes on the
average => the amount of traffic carried through the switch during
the busy hour is (1000x45 min / 60 min) = 75 Erlangs
•

© P. Raatikainen


4 - 11

Erlang’s first formula
Erlang 1st formula

An
n!
E1 (n, A) =
A2
An
+ +
1+ A+
2!
n!
Erlang 1st formula applies to systems fulfilling conditions
- a failed call is disconnected (loss system)
- full accessibility
- time between subsequent calls vary randomly
- large number of sources
E1(5, 2.7) implies that we have a system of 5 inlets and offered
load is 2.7 Erlangs - blocking calculated using the formula is 8.5 %
Tables and diagrams (based on Erlang’s formula) have been
produced to simplify blocking calculations

•

•
•

© P. Raatikainen


4 - 12

6

Example 2
•

An exchange for 2000 subscribers is to be installed and it is

required that the blocking probability should be below 10 %.
If E2 links are used to carry the subscriber traffic to
telephone network, how many E2 links are needed ?
- average call lasts 6 min
- a subscriber places one call during a 2-hour busy period
(on the average)
• Amount of offered traffic is (2000x6 min /2x60 min) = 100 Erl.
• Erlang 1st formula gives for 10 % blocking and load of 100 Erl.
that n = 97
=> required number of E1 links is ceil(97/30) = 4

© P. Raatikainen


4 - 13

Example 3
•
•
•

Suppose driving current of a switching gate (cross-point) is 100 mA
and its maximum input current is 8 mA
How many output gates can be connected to a bus, driven by one
input gate, if the capacitive load of the bus is negligibly small ?
Fan-out = floor[100/8] = 12
c

c
• How many output gates can be connected
to a bus driven by one input gate if load of
the bus corresponds to 15 % of the load of
a gate input) ?
• Fan-out = floor[100/(1.15x8)] = 10
© P. Raatikainen


c
1

c
2

…

M

4 - 14

7

Switch fabrics
•
•
•
•
•
•

Basic concepts
Two stage switches
Cost criteria

© P. Raatikainen


4 - 15

Multi-stage switching
•

Large switch fabrics could be constructed by using a
single NxN crossbar, interconnecting N inputs to N
outputs
- such an array would require N2 cross-points
- logical depth = 1
- considering the limited driving power of electronic or optical
switching gates, large N means problems with signal quality (e.g.
delay, deterioration)

•
•

Multi-stage structures can be used to avoid above
problems
Major design problems with multi-stages
- find a non-blocking structure
- find non-conflicting paths through the switching network

© P. Raatikainen


4 - 16

8

Multi-stage switching (cont.)
•
•
•
•
•
•
•
•

Let’s take a network of K stages
Stage k (1≤k≤K) has rk switch blocks (SB)
Switch block j (1≤j≤ rk) in stage k is denoted by S(j,k)
Switch j has mk inputs and nk outputs
Input i of S(j,k) is represented by e(i,j,k)
Output i of S(j,k) is represented by o(i,j,k)
Relation o(i,j,k)= e(i’,j’,k+1) gives interconnection between output i
and input i’ of switch blocks j and j’ in consecutive stages k and k+1
Special class of switches:
• nk = rk+1 and mk = rk-1
• each SB in each stage connected to each SB in the next stage

© P. Raatikainen


4 - 17

Clos network
mk = number of inputs in a SB at stage k
nk = number of outputs in a SB at stage k
rk = number of SBs at stage k
• parameter m1, n3, r1, r2, r3
chosen freely
• other parameters determined
uniquely by n1 = r2, m2 = r1,
n2 = r3, m3 = r2

m2 = r1 = 3

n2 = r3 = 4 m = r = 5
3
2

n1 = r2 = 5

n3 = 2
m1 = 3

r1 = 3

SB = Switch Block
© P. Raatikainen

r2 = 5


r3 = 4

4 - 18

9

Graph presentation of a Clos network
m2 = r1 = 3

n2 = r3 = 4
m3 = r2 = 5

n1 = r2 = 5

4x4 switch

m1 = 3
n3 = 2

1
2
3
4

1
2
3
4

r1 = 3
r2 = 5

r3 = 4

Every SB in stage k is connected to all rk+1 SBs in the following
stage k+1 with a single link.
© P. Raatikainen


4 - 19

Path connections in a 3-stage network
•
•
•

An input of SB x may be connected to an output of SB y via a
middle stage SB a
Other inputs of SB x may be connected to other outputs of SB y
via other middle stage SBs (b, c, …)
Paull’s connection matrix is used
1ST STAGE
2ND STAGE
3RD STAGE
to represent paths in three
SBs
SBs
SBs
stage switches
SB a

SB x

SB b

SB y

SB c

© P. Raatikainen


4 - 20

10

Paull’s matrix
•
•
•

Middle stage switch blocks (a, b, c) connecting 1st stage SB x to
3rd stage SB y are entered into entry (x,y) in r1 x r3 matrix
Each entry of the matrix may have 0, 1 or several middle stage SBs
A symbol (a,b,..) appears as many times in the matrix as there are
connections through it
1

Stage 3 switch blocks
. . .
. . .
y

2

r3

2
. . .
x

a, b, c

. . .

Stage 1 switch blocks

1

r1
© P. Raatikainen


4 - 21

Paull’s matrix (cont.)
Conditions for a legitimate point-to-point connection
matrix:
1 Each row has at most m1 symbols, since there can be as many
paths through a 1st stage SB as there are inputs to it
2 Each column has at most n3 symbols, since there can be as
many paths through a 3rd stage SB as there are outputs from it
1

2

. . .

1
2
Rows

. . .

At most min(m1, r2)
symbols in row x

y

. Columns
. .

r3

At most min(n3, r2)
distinct symbols in
row y

x

. . .

r1
© P. Raatikainen


4 - 22

11

Paull’s matrix (cont.)
Conditions of a legitimate point-to-point connection
matrix (cont.):
3 Symbols in each row must be distinct, since only one edge
connects a 1st stage SB to a 2nd stage SB
=> there can be at most r2 different symbols
4 Symbols in each column must be distinct, since only one edge
connects a 2nd stage SB to a 3rd stage SB and an edge does
not carry signals from several inputs
=> there can be at most r2 different symbols
In case of multi-casting, conditions 1 and 3 may not be valid,
because a path from the 1st stage may be directed via several
2nd stage switch blocks. Conditions 2 and 4 remain valid.
© P. Raatikainen


4 - 23

Strict-sense non-blocking Clos
Definitions:
• T’ is a subset of set T of transmitting terminals
• R’ is a subset of set R of receiving terminals
• Each element of T’ is connected by a legitimate multi-cast tree to
a non-empty and disjoint subset R’
• Each element of R’ is connected to one element of T’
A network is strict sense non-blocking if any t ∈T- T’ can establish
a legitimate multi-cast tree to any subset R - R’ without changes to
the previously established paths.
A rearrangeable network satisfies the same conditions, but allows
changes to be made to the previously established paths.
© P. Raatikainen


4 - 24

12

Clos theorem
Clos theorem:
A Clos network is strict-sense non-blocking if and only if the
number of 2nd stage switch blocks fulfills the condition

r2 ≥ m1 + n3 - 1
•

A symmetric Clos network with m1 = n3 = n is strict-sense nonblocking if

r2 ≥ 2n - 1

© P. Raatikainen


4 - 25

Proof of Clos theorem
Proof 1:
•

Let’s take some SB x in the 1st stage and some SB y in the 3rd
stage, which both have maximum number of connection minus one.
=> x has m1 -1 and y has n3 -1 connections

•

One additional connection should be established between x and y

•

In the worst case, existing connections of x and y occupy distinct
2nd stage SBs
=> m1 -1 SBs for paths of x has and n3 -1 SBs for paths of y

•

To have a connection between x and y an additional SB is needed
in the 2nd stage
=> required number of SBs is (m1 -1) + (n3 -1) + 1 = m1 + n3 -1

© P. Raatikainen


4 - 26

13

Visualization of proof
1

2

...
m1-1
1

m3

x
n1

1

y

1

2

...
n3-1

© P. Raatikainen


4 - 27

Paull’s matrix and proof of Clos theorem
Proof 2:
•

A connection from an idle input of a 1st stage SB x to an idle
output of a 3rd stage SB y should be established

•

m1-1 symbols can exist already in row x, because there are m1
inputs to SB x.

•

n3-1 symbols can exist already in row y, because there are n3
outputs to SB y.

•

In the worst case, all the (m1-1 + n3-1) symbol are distinct

•

To have an additional path between x and y, one more SB is
needed in the 2nd stage
=> m1 + n3 -1 SBs are needed

© P. Raatikainen


4 - 28

14

Procedure for making connections
•
•
•
•
•

Keep track of symbols used by row x using an occupancy vector ux
(which has r2 entries that represent SBs of the 2nd stage)
Enter “1” for a symbol in ux if it has been used in row x, otherwise
enter “0”
Likewise keep track of symbols used by column y using an
occupancy vector uy
To set up a connection between SB x and SB y look for a position j
in ux and uy which has “0” in both vectors
Amount of required computation
0
0 1
ux 0 1 1
is proportional to r2
1

2

3

j

r2

common “0”

uy
© P. Raatikainen

1
1

1
2

0
3

0
j

1


0
r2

4 - 29

Rearrangeable networks
Slepian-Duguid theorem:
A three stage network is rearrangeable if and only if
r2 ≥ max(m1, n3)
A symmetric Clos network with m1 = n3 = n is rearrangeably nonblocking if
r2 ≥ n

Paull’s theorem:
The number of circuits that need to be rearranged is at most
min(r1, r3) -1
© P. Raatikainen


4 - 30

15

Connection rearrangement by
Paull’s matrix
•

If there is no common symbol (position j) found in ux and uy, we look
for symbols in ux that are not in uy and symbols in uy not found in ux
=> a new connection can be set up only by rearrangement

•

Let’s suppose there is symbol a in ux (not in uy) and symbol b in uy
(not in ux) and let’s choose either one as a starting point

•

Let it be a then b is searched from the column in which a resides (in
row x) - let it be column j1 in which b is found in row i1

•

In row i1 search for a - let this position be column j2 n

•

This procedure continues until symbol a or b cannot be found in the
column or row visited
0
1
1 1
ux 1 1
1

uy
© P. Raatikainen

2

a

b

1
1

1
2

1

0

a

b

r2
1

1
r2


4 - 31

Connection rearrangement by Paull’s
matrix (cont.)
•

•
•

At this point connections identified can be rearranged by replacing
symbol a (in rows x, i1, i2, ...) by b and symbol b (in columns y, j1,
j2, ...) by a
a and b still appear at most once in any row or column
2nd stage SB a can be used to connect x and y
1

j1

y

j3

j2

1

r3

j1

y

j3

j2

r3

1

1
i1
x

a

a

i2

a b

i1

a

x

b

b

© P. Raatikainen

a

i2

b a
b

b
r1

b

r1

4 - 32

16

Example of connection rearrangement
by Paull’s matrix
•
•

Let’s take a three-stage network 24x25 with r1=4 and r3=5
Rearrangeability condition requires that r2=6
- let these SBs be marked by a, b, c, d, e and f
=> m1 = 6, n1 = 6, m2 = 4, n2 = 5, m3 = 6, n3 = 5
6x6
1
2

4x5

1

6x5

1(a)

1
2

1

6

5

1
2

2

2(b)

1
2

2

6

5

…

…

…

4

1
2

6(f)

5

1
2

6

5

© P. Raatikainen


4 - 33

by Paull’s matrix (cont.)

•
•

•

In the network state shown below, a new connection is to be
established between SB1 of stage 1 and SB1 of stage 3
No SBs available in stage 2 to allow a new connection
Slepian-Duguid theorem => a three stage network is rearrangeable
if and only if r2 ≥ max(m1, n3)
- m1 = 6, n3 = 5, r2 = 6 => condition fulfilled
SBs c and d are selected to operate rearrangement
1
1
1st stage SBs

•

f

2

a,b

3rd stage SBs
2
3
4
5

3
4

a
d

b,e

c

u1-1

c

c
d

Occupancy vectors of SB1/stage 1
and SB1/stage 3

e,f
a

b,f

1
b

1
c

0
d

1
e

1
f

u3-1

1
a

1
b

0
c

1
d

0
e

0
f

d

c

1
a

© P. Raatikainen


4 - 34

17


•

Start rearrangement procedure from symbol c in row 1 and
column 5
5 connection rearrangements are needed to set up the required
connection - Paull’s theorem !!!

1st stage SBs

1
1

f

2

a,b

3rd stage SBs
2
3
4
5

3

a
d
c

4

d

b,e

c

c
e,f
c

d
a

© P. Raatikainen

b,f

1
1st stage SBs

•

1

c,f

2

a,b

3rd stage SBs
2
3
4
5

3
4

a

c

b,e

d

d e,f
d

d

c

c
a

b,f


4 - 35

•

Paull’s theorem states that the number of circuits that need to be
rearranged is at most min(r1, r3) -1 = 3
=> there must be another solution

•

Start rearrangement procedure from d in row 4 and column 1
=> only one connection rearrangement is needed

1

f

2

a,b

3rd stage SBs
2
3
4
5

3
4

© P. Raatikainen

a
d
c

d

b,e

c

c
e,f
c

d
a

b,f

1
1st stage SBs

1st stage SBs

1

1

c,f

2

a,b

3rd stage SBs
2
3
4
5

3
4


a
c
d

c

b,e

d

d
e,f

d

c
a

b,f

4 - 36

18

Recursive construction of switching
networks
•

To reduce cross-point complexity of three stage switches individual
stages can be factored further

•

Suppose we want to construct an NxN switching network and let
N = pxq

•

A rearrangeably non-blocking Clos network is constructed
recursively by connecting a pxp, qxq and pxp rearrangeably nonblocking switch together in respective order
=> under certain conditions result may be a strict-sense nonblocking network

•

A strict-sense non-blocking network is constructed recursively by
connecting a p(2p - 1), qxq and p(2p - 1) strict-sense non-blocking
switch together in respective order
=> result may be a rearrangeable non-blocking network

© P. Raatikainen


4 - 37

3-dimensional construction of a
rearrangeably non-blocking network
q PLANES

p PLANES

pxp

q PLANES

pxp

qxq

Number of cross-points for the rearrangable construction is
p2q + q2p + p2q = 2 p2q + q2p
© P. Raatikainen


4 - 38

19

3-dimensional construction of a strictsense non-blocking network
q PLANES

px(2p-1)

p PLANES
q PLANES
(2p-1)xp

qxq

Number of cross-points for the strictly non-blocking construction is
p(2p - 1)q + q2 (2p - 1) + p (2p - 1)q = 2p(2p - 1) q + q2 (2p - 1)
© P. Raatikainen


4 - 39

Recursive factoring of switching
networks
•

N can be factored into p and q in many ways and these can be
factored further

•

Which p to choose and how should the sub-networks be factored
further ?

•

Doubling in the 1st and 3rd stages suggests to start with the smallest
factor and recursively factor q = N/p using the next smallest factor
=> this strategy works well for rearrangeable networks
=> for strict-sense non-blocking networks width of the network is
doubled
=> not the best strategy for minimizing cross-point count

•

Ideal solution: low complexity, minimum number of cross-points and
easy to construct => quite often conflicting goals
© P. Raatikainen


4 - 40

20

Recursive factoring of a rearrangeably
non-blocking network

N INPUTS

N/2 x N/2
SWITCH

N/2 x N/2
SWITCH

© P. Raatikainen

N OUTPUTS

• Special case N = 2n, n being a positive integer
=> a rearrangeable network can be constructed by factoring N into
p = 2 and q = N/2
=> resulting network is a Benes network
=> each stage consists of N/2 switch blocks of size 2x2
• Factor q relates to the multiplexing factor (number of time-slots on inputs)
=> recursion continued until speed of signals low enough for real
implementations


4 - 41

Benes network
Inverse baseline network

N INPUTS

N OUTPUTS

Baseline network

Number of stages in a Benes network
K = 2log2N - 1
© P. Raatikainen


4 - 42

21

Benes network (cont.)
•

Benes network is recursively constructed of 2x2 switch blocks and it
is rearrangeably non-blocking (see Clos theorem)

•

First half of Benes network is called baseline network

•

Second half of Benes network is a mirror image (inverse) of the first
half and is called inverse baseline network

•

Number of switch stages is K = 2log2N - 1

•

Each stage includes N/2 2x2 switching blocks (SBs) and thus
number of SBs of a Benes network is
Nlog2N - (N/2) = N(log2N - ½)

•

Each 2x2 SB has 4 cross-points and number of cross-points in a
Benes network is
4(N/2)(2log2N-1) = 4Nlog2N - 2N ∼ 4Nlog2N
© P. Raatikainen


4 - 43

16 INPUTS

16 OUTPUTS

Illustration of recursively factored
Benes network

© P. Raatikainen


4 - 44

22

Switch Fabrics


© P. Raatikainen


5-1

Recursive factoring of a strict-sense
non-blocking network
•

A strict-sense non-blocking network can be constructed recursively,
but the size of network (number of cross-points) crows fast as a
function of the number of inputs, namely CNlog2N

•

Instead of starting with the smaller factor for p let’s use switch
blocks of N x N

•

Let N = 2n and n = 2l then we are factoring square switches with
number of inputs and outputs being power of 2
=> condition for a strict-sense non-blocking network states that
there are r2 ≥ 2x2n/2 - 1 second stage SBs

•

•

Let choose r2 = 2x2n/2 then sizes of the
- 1st stage switches are 2n/2 x 2n/2+1
- 3rd stage switches are 2n/2+1 x 2n/2
Each of these can be made of two SBs each of size 2n/2 x 2n/2
© P. Raatikainen


5-2

1

Recursive factoring of a strict-sense
non-blocking network (cont.)
•

2nd stage switches are of size 2n/2 x 2n/2

•

The three stages consist of 6x2n/2 SBs, each of size 2n/2 x 2n/2

•

Let F(2n ) be the cross-point complexity of an NxN switch then

•

F(2n) = 6x2n/2F(2n/2 )
= 6lx2n/2+n/4+…+1F(21)
< 6lx2nF(2)
= N(log2N)2.58F(2)
= 4N(log2N)2.58

•

The difference between rearrangeable and strict-sense nonblocking networks lies in the exponent for the log2N term

© P. Raatikainen


5-3

Strict-sense non-blocking network with
smaller number of cross-points
•

Strict-sense non-blocking networks with smaller number of crosspoints than F(2n) = 4N(log2N)2.58 can be constructed

•

One alternative is to use Cantor network, which is constructed
using Benes networks, multiplexers and demultiplexers
•

i-th input of Cantor network connected to j-th input of j-th
Benes network using j-th output of a 1xm demultiplexer

•

i-th output of j-th Benes network connected to i-th output of
Cantor network using j-th input of a mx1 multiplexer

•

When N is known, number of required Benes planes to have a
strict-sense non-blocking Cantor network is m = log2N

•

Since a Benes network has a cross-point count of 4Nlog2N, number
of cross-points of a Cantor network is roughly 4N(log2N)2 (when
ignoring cross-points of the multiplexers and demultiplexers
© P. Raatikainen


5-4

2

Cantor network
1 TO LOG(N)
MULTIPLEXERS

N INPUTS

N OUTPUTS

1 TO LOG(N)
DEMULTIPLEXERS

© P. Raatikainen


5-5

Cantor network strict-sense
non-blocking
Proof:
•

Markings
• m number of parallel Benes networks
• k number of stage in a Benes network
• A(k) number of reachable 2x2 SBs without rearrangements in
stage k (1≤k≤log2N) starting from an input of a Cantor network

•

Reachable 2x2 SBs in consecutive stages
• A(1) = m
• A(2) = 2A(1) - 1
• A(3) = 2A(2) - 2
• A(k) = 2A(k-1) - 2k-2 = 22A(k-2) - 2x2k-2 = 2k-1A(1) - (k-1)x2k-2
• A(log2N) = 2log2N-1m - (log2N -1) 2log2N-2
= ½ Nm - ¼ (log N -1)N
2
© P. Raatikainen


5-6

3

Cantor network strict-sense
non-blocking (cont.)
•

Cantor network is symmetrical at the middle
=> the same number of center stage nodes are reachable by an
output of a Cantor network

•

Total number of SBs in center stages is Nm/2 (m Benes networks)

•

If the number of center stage SBs reached by an input and an
output exceeds Nm/2 then there must be a SB reachable from both

•

Hence strict-sense non-blocking is achieved if
2 [1 Nm - 1 (log 2 N - 1)N ] >
2
4

Nm
2

=> m > log2N - 1
Notice that a strict-sense non-blocking Cantor network is
constructed of log2N rearrangeably non-blocking Benes networks
© P. Raatikainen


5-7

N INPUTS

N OUTPUTS

Visualization of proof

© P. Raatikainen


5-8

4

Optics Switching Technology Course Overview

Optics Switching Technology Course Overview

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