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# Understanding powerfactor

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### Understanding powerfactor

1. 1. ® APPLICATION NOTE UNDERSTANDING POWER FACTOR by L. WuidartIF YOU THINK THAT POWER FACTOR IS Figure 1: Full Wave Bridge Rectifier Waveforms.ONLY COS ϕ, THINK AGAIN !The big majority of Electronics designers do not Imainsworry about Power Factor (P.F.) VdcP.F. is something you learnt one day at school in Vmains Loadyour Electrotechnics course"as being cos ϕ.This conventional definition is only valid when Vdcconsidering IDEAL Sinusoidal signals for bothcurrent and voltage waveforms.But the reality is something else, because most off- Vmainsline power supplies draw a non-sinusoidal current! tMany off-line systems have a typical front-end Imains 0 T/2 Tsection made by a rectification bridge and an in-put filter capacitor. D95IN223This front-end section acts as a peak detector(see figure 1). IEC555-2 only defines the current harmonic con-A current flows to charge the capacitor only when tent limits of mains supplied equipments.the istantaneous AC voltage exceeds the voltageon the capacitor. THEORETICAL MEANINGA single phase off-line supply draws a currentpulse during a small fraction of the half-cycle du- The power factor (P.F.) is defined by:ration. P REALPOWERBetween those current peaks, the load draws the P.F. = =energy stored inside the input capacitor. The S TOTAL APPARENT POWERphase lag ϕ but also the harmonic content of sucha typical pulsed current waveform produce non Ideal Sinusoidal Signalsefficient extra RMS currents, affecting then thereal power available from the mains. Both current and voltage waveforms are assumed to be IDEAL SINUSOIDAL waveforms. If theSo, P.F. is much more than simply cos ϕ! phase difference between the input voltage andThe P.F. value measures how much the mains ef- the current waveforms is defined as the phase lagficiency is affected by BOTH phase lag ϕ AND angle or displacement angle, the correspondingharmonic content of the input current. graphical representation of power vectors gives:In this context, the standard European project The corresponding power give: P = VRMS IRMS Cos ϕ ϕ Then, by definition: S = VRMS IRMS Q = VRMS IRMS Sin ϕ total apparent power reactive or quadrature power P P.F. = Cosϕ S D95IN224AAN824/1003 1/5
2. 2. APPLICATION NOTENon-ideal sinusoidal current waveform As ϕ1 is the displacement angle between the in-Assume that the mains voltage is an IDEAL put voltage and the in-phase component of theSINUSOIDAL voltage waveform. fundamental current:Its RMS value is: I1RMS P = I1RMS Cosϕ1 Vpeak and VRMS =  √ 2 P = VRMS ⋅ I1RMS ⋅ Cosϕ1If the current has a periodic non-ideal sinusoidal S = VRMS ⋅ IRMS totalwaveform, the FOURIER transform can be ap-plied Then, the Power Factor can be calculated as: IRMS total =  I2 + I2 1RMS + I2 2RMS +....+ I2 nRMS √ O P I1RMS ⋅ Cosϕ1 P.F. = =Where IO is the DC component of the current, S IRMS totalI1rms the fundamental of the RMS current andI2RMS ....InRMS the harmonics One can introduce the k factor byFor a pure AC signal: IO = 0 I1RMS k= = CosΘThe fundamental of the RMS current has an in- IRMS totalphase component I1RMSP and a quadrature com-ponent I1RMSQ. Θ is the distortion angle. The k factor is linked toSo, the RMS current can be espressed as: the harmonic content of the current. If the har- monic content of IRMS total is approaching zero, k------> 1.  I P+I Q+∑ I √ ∞ 2 2 2 IRMS total = 1RMS 1RMS nRMS Conclusion n=2 Finally P.F. can be expressed by:Then, the Real Power is given by: P.F. = CosΘ ⋅ Cos ϕ1 P = VRMS ⋅ I1RMS P So, the power vectors representation becomes In-phase P = Real Power = VRMS · I1RMS Cos ϕ1 ϕ1 Q = Reactive Power S1 = App are = VRMS · I1RMS Sin ϕ1 S θ nt fu -T =V nda ot m enta quadrature al ap MR S · I1 l po RM wer pa S re nt Po we r- V RM S ·I RM S to ta D = Distortion Power l = VRMS √ ∑∞n=2 I2nRMS D95IN225A ϕ1 is the "conventional" displacement angle (phase lag) between the in-phase fundamental I and V Θ is the distortion angle linked to the harmonic content of the current. Both of reactive (Q) and distortion (D) powers produce extra RMS currents, giving extra losses so that then the mains supply network efficiency is decreased. Improving P.F. means to improve both of factors i.e.: ϕ1 → 0 ⇒ Cos ϕ1 → 1 ⇒ reduce phase lag between I and V Θ → 0 ⇒ Cos Θ → 1 ⇒ reduce harmonic content of I2/5
3. 3. APPLICATION NOTEPRACTICAL MEANING The Electricity distribution company benefitThe unity power factor beneficiaries Both of reactive (Q) power and distortion (D)Both of the user and the Electricity distribution power produce extra RMS currents.company take advantage from a unity power fac- The resulting extra losses significantly decreasetor. Moreover, adding a PFC brings components the mains supply network efficiency. This leads tocost reduction in the downstream converter. oversize the copper area of distribution power wires (see figure 3)The user’s benefit The distortion power is linked to the current har- monic content. Delivering power at other frequen-At minimum line voltage (85VAC), a standard cies than the line frequency causes a lot of draw-115VAC well socket should be able to deliver the backs.nominal 15A to a common load.In similar conditions, a "non-corrected power fac- The current distortion disturbs the zero crossingtor" SMPS (typical value of 0.6) drops the avail- detection systems, generates overcurrent in theable current from 15A to only 9A. neutral line and resonant overvoltages.For example, from one wall socket, four 280W In Europe, the standard EN 60555 and the inter-computers each equipped with P.F.C. can be national project IEC 555-2 limit the current har-supplied instead of two with no P.F.C. monic content of mains supplied equipments.Figure 2: Reactive and distortion power produce extra RMS currents leading to copper area oversize. Without P.F.C. 115VAC/15A With P.F.C. D95IN227Figure 3: Reactive and distortion power produce extra RMS currents leading to copper area oversize. 3/5
4. 4. APPLICATION NOTEComponents cost reduction in the down- ered by the PFC preregulator.stream converter The PFC provides an automatic mains selectionFor the same output power capability, a conven- on a widerange voltage from 85VAC up totional converter using a input mains voltage dou- 265VAC. Compared to the conventional doublerbler, is penalized by a 1,8 times higher primary front-end section, the same "hold-up" time can beRMS current than with a PFC preregulator. achieved with a 6 times smaller bulk storage ca- pacitor.Consequently, the PFC allows to select powerMOSFET’s switches with up to 3 times higher on To get 10ms hold-up time, a 100W converter inresistance (rds on) in the downstream converter doubler operation requires a series combination(see figure 4). of two 440µF capacitos instead of one 130µF with PFC.The converter transformer size can be optimizednot only because the copper area is smaller butalso, due to the regulated DC bulk voltage deliv- General commentsFigure 4: Power MOSFET On-resistance (rds on) For new developments, SMPS designers will have to consider the IEC 555-2 standard.is 3 times higher by using a PFC. In the practice, this leads to use a PFC is com- pensated by significant component cost reduction without P.F.C. with P.F.C. in the downstream converter. The PFC also provides additional functions such as automatic mains voltage selection and a con- stant output voltage. Nevertheless, size a nd cost optimization of PFC has to take the RFI filter section into account. A PFC circuit generates more high frequency in- terferences to the mains than a conventional rec- tifier front-end section (see figure 5). rds on rds onX3 The PFC use requires thus additional filtering. For this reason, modulation techniques and mode of operation for the PFC have to be carefully adapted to the application requirement.Figure 5: A Power Factor Converter generates higher frequency interferences to the mains than a conventional rectifier front-end lower sym. attenuation filter Ci 220µF Usaual SMPS structure higher sym. attenuation filter Ci 0.1µF P.F.C. structure D95IN2264/5
5. 5. APPLICATION NOTEInformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication aresubject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics productsare not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia – Belgium - Brazil - Canada - China – Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 5/5