SIMPLIFIED SECURED WIRELESS RAILWAY / AIRWAY FOR RESERVATION

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RAILWAY / AIRWAY FOR RESERVATION"

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SIMPLIFIED SECURED WIRELESS RAILWAY / AIRWAY FOR RESERVATION

  1. 1. SIMPLIFIED SECURED WIRELESS RAILWAY / AIRWAY FOR RESERVATION A MAJOR PROJECT Submitted in partial fulfillment of the Requirements for the award of the Degree of BACHELOR OF TECHNOLOGY IN ELECTRONICS AND COMMUNICATION ENGINEERING By P. NAYAN LALIT 107R1A0441 D. RAKESH KUMAR 107R1A0412 K. SNEHA 107R1A0420 Under the esteemed guidance of Mr. D. SREEKANTH M.Tech, AMIETE Assistant Professor DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING CMR TECHNICAL CAMPUS (AFFILIATED TO JNTU, HYDERABAD) KANDLAKOYA (V), MEDCHAL, HYDERABAD - 501401 2014
  2. 2. CMR TECHNICAL CAMPUS (AFFLIATED TO JNTU, HYDERABAD) KANDLAKOYA (V), MEDCHAL, HYDERABAD – 501401 CERTIFICATE This is to certify that the project report entitled “SIMPLIFIED SECURED WIRELESS RAILWAY / AIRWAY FOR RESERVATION” that is being submitted by P. NAYAN LALIT, D. RAKESH KUMAR and K. SNEHA bearing Roll No.s: 107R1A0441, 107R1A0412 and 107R1A0420 in partial fulfillment for the award of the Degree of BACHELOR OF TECHNOLOGY in ELECTRONICS AND COMMUNICATION ENGINEERING to the Jawaharlal Nehru Technological University is a record of bonafide work carried out by them under my guidance and supervision. The results embodied in this report have not been submitted to any other university or institute for the award of any degree or diploma. D. SREEKANTH M.Tech, AMIETE G. SRIKANTH M.Tech, Ph.D* Assistant Professor Associate Professor INTERNAL GUIDE HEAD OF THE DEPARTMENT Dr. A. RAJI REDDY M.Tech, Ph.D EXTERNAL EXAMINER DIRECTOR
  3. 3. ACKNOWLEDGEMENT We are expressing our sincere thanks to Dr. A. RAJI REDDY, Director of CMR Technical Campus for his kind co-operation and valuable suggestions during our study period. It is a great honor to express our gratitude to Mr. G. SRIKANTH, Head of The Electronics and Communications Engineering Department. It’s an immense pleasure to thank our internal guide Mr. D. SREEKANTH, for supporting us throughout our project. His/her inspiring remarks, simulating guidance, valuable suggestions and influencing encouragement helped us greatly in the completion of our project. We would like to express our sense of gratitude to our project coordinator Mrs. B. RAGINI REDDY for supporting us throughout our project. Finally, we would like to thank our parents and friends who provided us a lot of moral support and encouragement in many ways for the completion of this project work. P. NAYAN LALIT D. RAKESH KUMAR K. SNEHA
  4. 4. i ABSTRACT In the New era of technology all system has to be updated, Indian Railway is the 2nd largest Rail Network in India it is the backbone of public and goods transport in India. Bulk of long distance traffic is carried by the Indian Railway. We think to implement biometrics in our research and then decided to use fingerprint module also for the add-on for user flexibility using GSM module for Communication purpose of sending and receiving message. In our Project Research we are trying to minimize railway Reservation Fraud and give more facility to traveler and improve society. Also simplify the Reservation System in that we will take fingerprint of the person who goes for reservation/ticket booking and help a lot humanitarian by this innovative technology. Why we have adopted Finger Print Technology because Fingerprints are imprints formed by friction ridges of the skin and thumbs. They are generally used for security based application because of their immutability and individuality. Immutability refers to the permanent and unchanging character of the pattern on each finger. The person who goes for reservation has Standalone module which contains Finger Print Module verifies the person’s identity. Using GSM before the journey message will be send to the user with information. At time of journey Ticket checker will verify fingerprint with previously stored data using stand alone module as a part of verification. By this more number of papers will be saved by that can help Railway in increasing their income by saving cost of paper. No need to carry identity proof. Due to this complicated and bulky reservation and transport system can be corrected.
  5. 5. ii CONTENTS Title Certificates Acknowledgement Abstract i Contents ii List of Figures iv List of Tables vi CHAPTER 1: INTRODUCTION 01 1.1 Introduction 01 1.2 Overview of the Project 05 1.3 Block Diagram 06 1.4 Organization of Thesis 06 CHAPTER 2: DESCRIPTION OF HARDWARE COMPONENTS 08 2.1 Introduction to LPC2103 08 2.1.1 LPC2103 08 2.1.2 Features 08 2.1.3 Pin Description of LPC2103 11 2.1.4 Block Diagram 12 2.1.5 Architectural Overview 17 2.1.6 Functional Description 18 2.1.7 GPIO 24 2.2 Power Supply 29 2.3 IC 7805 34 2.4 LCD 35 2.5 MAX-232 38 2.6 Keypad 42
  6. 6. iii CHAPTER 3: GSM AND FINGER PRINT MODULE 45 3.1 Introduction to GSM 45 3.1.1 Working and Specifications of GSM 46 3.1.2 Architecture and Building Blocks 47 3.1.3 Ciphering Codes 50 3.2. Introduction to KY-M6 Fingerprint Sensor Module 53 3.2.1 Specifications 54 CHAPTER 4: CIRCUIT OPERATION & FLOW CHART 55 4.1 Schematic Diagram 55 4.1.1 Operation and Procedure 56 4.2 Flowchart Représentation 57 CHAPTER 5: SOFTWARE DEVELOPMENT 58 5.1 Introduction 58 5.2 Tools used 58 5.2.1 LPC 2103 Compiler & LPC2103 Macro Assembler 59 5.2.2 Start µVision 59 5.2.3 Building an Application in µVision 60 5.2.4 Flash Magic 68 CHAPTER 6 : RESULT 71 CHAPTER 7 : ADVANTAGES, CONCLUSION & FUTURE SCOPE 72 REFERENCES 74 APPENDIX – A SOURCE CODE 75
  7. 7. iv LIST OF FIGURES Figure 1.1- Block Diagram of Proposed System 07 Figure 2.1- Pin Diagram LPC2103 11 Figure 2.2- Block Diagram LPC2103 12 Figure 2.3- The LPC2101/2102/2103 memory map 19 Figure 2.4- Block Diagram Power Supply 29 Figure 2.5- Transformer 29 Figure 2.6- Half Wave Rectifier 30 Figure 2.7- Full Wave Rectifier 30 Figure 2.8- Bridge Rectifier 21 Figure 2.9- Center Tapped Rectifier 32 Figure 2.10- Voltage Regulator 34 Figure 2.11- Circuit Diagram of power supply 34 Figure 2.12- 2x16 Line Alphanumeric LCD Display 36 Figure 2.13- Architecture of LCD with Controller 37 Figure 2.14- MAX 232 38 Figure 2.15- TTL/CMOS Serial Logic Waveform 38 Figure 2.16- RS-232 Logic Waveform 39 Figure 2.17- RS-232 Level Converter 39 Figure 2.18- MAX 232 to RS232 Internal Connection 39 Figure 2.19- RS 232 Port 41 Figure 2.20- Finger Print Module 42 Figure 2.21- Finger Print Internal Architecture 42 Figure 3.1- GSM Modem 45 Figure 3.2- Representation of a GSM signal using TDMA & FDMA with respect to the transmitted power 46 Figure 3.3- The basic blocks of the whole GSM system 48 Figure 3.4- Transmitter for the voice signal 49 Figure 3.5- Receiver for the Voice signal 50 Figure 3.6- Signaling between Air and Abis Interface 51
  8. 8. v Figure 3.7- Finger Print Module 53 Figure 4.1- Schematic Diagram 55 Figure 4.2- FlowChart 57 Figure 5.1- Keil Software- internal stages 58 Figure 6.1- Snapshot of the working project 58
  9. 9. vi LIST OF TABLES Table 2.1- Ordering Information 10 Table 2.2- Ordering Options 10 Table 2.3- Pin Description 13 Table 2.4- Specifications of IC7805 35 Table 2.5- Pins of LCD 36 Table 3.1- Abbreviations Signaling Schemes and Ciphering Codes Used 48 Table 3.2- Specifications of Finger Print Module 54
  10. 10. 1 Chapter 1 INTRODUCTION 1.1 INTRODUCTION An Embedded System is a combination of computer hardware and software, and perhaps additional mechanical or other parts, designed to perform a specific function. A good example is the microwave oven. Almost every household has one, and tens of millions of them are used every day, but very few people realize that a processor and software are involved in the preparation of their lunch or dinner. This is in direct contrast to the personal computer in the family room. It too is comprised of computer hardware and software and mechanical components (disk drives, for example). However, a personal computer is not designed to perform a specific function rather; it is able to do many different things. Many people use the term general-purpose computer to make this distinction clear. As shipped, a general-purpose computer is a blank slate; the manufacturer does not know what the customer will do wish it. One customer may use it for a network file server another may use it exclusively for playing games, and a third may use it to write the next great American novel. Frequently, an embedded system is a component within some larger system. For example, modern cars and trucks contain many embedded systems. One embedded system controls the anti-lock brakes, other monitors and controls the vehicle’s emissions, and a third displays information on the dashboard. In some cases, these embedded systems are connected by some sort of a communication network, but that is certainly not a requirement. At the possible risk of confusing you, it is important to point out that a general- purpose computer is itself made up of numerous embedded systems. For example, my computer consists of a keyboard, mouse, video card, modem, hard drive, floppy drive, and sound card-each of which is an embedded system. Each of these devices contains a processor and software and is designed to perform a specific function. For example, the modem is designed to send and receive digital data over analog telephone line. That’s it and all of the other devices can be summarized in a single sentence as well.
  11. 11. 2 If an embedded system is designed well, the existence of the processor and software could be completely unnoticed by the user of the device. Such is the case for a microwave oven, VCR, or alarm clock. In some cases, it would even be possible to build an equivalent device that does not contain the processor and software. This could be done by replacing the combination with a custom integrated circuit that performs the same functions in hardware. However, a lot of flexibility is lost when a design is hard-cooled in this way. It is much easier, and cheaper, to change a few lines of software than to redesign a piece of custom hardware. Real Time Systems: One subclass of embedded is worthy of an introduction at this point. As commonly defined, a real-time system is a computer system that has timing constraints. In other words, a real-time system is partly specified in terms of its ability to make certain calculations or decisions in a timely manner. These important calculations are said to have deadlines for completion. And, for all practical purposes, a missed deadline is just as bad as a wrong answer. The issue of what if a deadline is missed is a crucial one. For example, if the real- time system is part of an airplane’s flight control system, it is possible for the lives of the passengers and crew to be endangered by a single missed deadline. However, if instead the system is involved in satellite communication, the damage could be limited to a single corrupt data packet. The more severe the consequences, the more likely it will be said that the deadline is “hard” and thus, the system is a hard real-time system. Real-time systems at the other end of this discussion are said to have “soft” deadlines. All of the topics and examples presented in this book are applicable to the designers of real-time system who is more delight in his work. He must guarantee reliable operation of the software and hardware under all the possible conditions and to the degree that human lives depend upon three system’s proper execution, engineering calculations and descriptive paperwork. Application Areas: Nearly 99 per cent of the processors manufactured end up in embedded systems. The embedded system market is one of the highest growth areas as these systems are
  12. 12. 3 used in very market segment- consumer electronics, office automation, industrial automation, biomedical engineering, wireless communication, data communication, telecommunications, transportation, military and so on. Consumer Appliances: At home we use a number of embedded systems which include digital camera, digital diary, DVD player, electronic toys, microwave oven, remote controls for TV and air-conditioner, VCO player, video game consoles, video recorders etc. Today’s high- tech car has about 20 embedded systems for transmission control, engine spark control, air-conditioning, navigation etc. Even wristwatches are now becoming embedded systems. The palmtops are powerful embedded systems using which we can carry out many general-purpose tasks such as playing games and word processing. Industrial Automation: Today a lot of industries use embedded systems for process control. These include pharmaceutical, cement, sugar, oil exploration, nuclear energy, electricity generation and transmission. The embedded systems for industrial use are designed to carry out specific tasks such as monitoring the temperature, pressure, humidity, voltage, current etc., and then take appropriate action based on the monitored levels to control other devices or to send information to a centralized monitoring station. In hazardous industrial environment, where human presence has to be avoided, robots are used, which are programmed to do specific jobs. The robots are now becoming very powerful and carry out many interesting and complicated tasks such as hardware assembly. Medical Electronics: Almost every medical equipment in the hospital is an embedded system. These equipments include diagnostic aids such as ECG, EEG, blood pressure measuring devices, X-ray scanners; equipment used in blood analysis, radiation, colonscopy, endoscopy etc. Developments in medical electronics have paved way for more accurate diagnosis of diseases.
  13. 13. 4 Computer Networking: Computer networking products such as bridges, routers, Integrated Services Digital Networks (ISDN), Asynchronous Transfer Mode (ATM), X.25 and frame relay switches are embedded systems which implement the necessary data communication protocols. For example, a router interconnects two networks. The two networks may be running different protocol stacks. The router’s function is to obtain the data packets from incoming pores, analyze the packets and send them towards the destination after doing necessary protocol conversion. Most networking equipments, other than the end systems (desktop computers) we use to access the networks, are embedded systems. Telecommunications: In the field of telecommunications, the embedded systems can be categorized as subscriber terminals and network equipment. The subscriber terminals such as key telephones, ISDN phones, terminal adapters, web cameras are embedded systems. The network equipment includes multiplexers, multiple access systems, Packet Assemblers Dissemblers (PADs), sate11ite modems etc. IP phone, IP gateway, IP gatekeeper etc. are the latest embedded systems that provide very low-cost voice communication over the Internet. Wireless Technologies: Advances in mobile communications are paving way for many interesting applications using embedded systems. The mobile phone is one of the marvels of the last decade of the 20’h century. It is a very powerful embedded system that provides voice communication while we are on the move. The Personal Digital Assistants and the palmtops can now be used to access multimedia services over the Internet. Mobile communication infrastructure such as base station controllers, mobile switching centers are also powerful embedded systems. Security: Security of persons and information has always been a major issue. We need to protect our homes and offices; and also the information we transmit and store. Developing embedded systems for security applications is one of the most lucrative businesses nowadays. Security devices at homes, offices, airports etc. for authentication
  14. 14. 5 and verification are embedded systems. Encryption devices are nearly 99 per cent of the processors that are manufactured end up in~ embedded systems. Embedded systems find applications in . every industrial segment- consumer electronics, transportation, avionics, biomedical engineering, manufacturing, process control and industrial automation, data communication, telecommunication, defense, security etc. Used to encrypt the data/voice being transmitted on communication links such as telephone lines. Biometric systems using fingerprint and face recognition are now being extensively used for user authentication in banking applications as well as for access control in high security buildings. Finance: Financial dealing through cash and cheques are now slowly paving way for transactions using smart cards and ATM (Automatic Teller Machine, also expanded as Any Time Money) machines. Smart card, of the size of a credit card, has a small micro- controller and memory; and it interacts with the smart card reader! ATM machine and acts as an electronic wallet. Smart card technology has the capability of ushering in a cashless society. Well, the list goes on. It is no exaggeration to say that eyes wherever you go, you can see, or at least feel, the work of an embedded system. 1.2 OBJECTIVE OF THE PROJECT In the New era of technology all system has to be updated, Indian Railway is the 2nd largest Rail Network in India it is the backbone of public and goods transport in India. Bulk of long distance traffic is carried by the Indian Railway. we think to implement biometrics in our research and then decided to use fingerprint module also for the add-on for user flexibility using GSM module for Communication purpose of sending and receiving message. In our Project Research we are trying to minimize railway Reservation Fraud and give more facility to traveler and improve society. Also simplify the Reservation System in that we will take fingerprint of the person who goes for reservation/ticket booking and help a lot humanitarian by this innovative technology. Why we have adopted Finger Print Technology because Fingerprints are imprints formed by friction ridges of the skin and thumbs. They are generally used for security based application because of their
  15. 15. 6 immutability and individuality. Immutability refers to the permanent and unchanging character of the pattern on each finger. Finger Print Module verifies the person’s identity. Using GSM before the journey message will be send to the user with information. At time of journey Ticket checker will verify fingerprint with previously stored data using standalone module as a part of verification. By this more number of papers will be saved by that can help Railway in increasing their income by saving cost of paper. No need to carry identity proof. Due to this complicated and bulky reservation and transport system can be corrected. 1.3 BLOCK DESIGN PROPOSAL FOR THE SYSTEM Fig 1: Block Diagram of Proposed System ENROLL ARM7/ CORTEX GSM RAILWAY STATION FOR RESERVATION KEY PAD FINGER PRINT MODULE LCD VERIFY VERIFICATION PURPOSE MAX 232
  16. 16. 7 1.4 ORGANISZATION OF THESIS Chapter 1 provides brief history of the project, describes major capabilities Chapter 2 describes the hardware component used in this project Chapter 3 provides information on the two important components “GSM and Finger Print Module.” Chapter 4 provides the circuit operation and flow chart design of the project Chapter 5 provides the information on the software kit used and the procedure how to use it Chapter 6 provides the snapshots of the final result Chapter 7 describes the advantages & application of the project Chapter 8 includes the conclusion and future scope
  17. 17. 8 Chapter 2 LPC2103 MICROCONTROLLER 2.1 INTRODUCTION TO LPC2103 2.1.1 LPC2103 The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, the LPC2101/2102/2103 are ideal for applications where miniaturization is a key requirement. A blend of serial communications interfaces ranging from multiple UARTs, SPI to SSP and two I2 C-buses, combined with on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication gateways and protocol converters. The superior performance also makes these devices suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved 10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2.1.2 Features  16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package.  2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.  ISP/IAP via on-chip boot loader software. Single flash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms.
  18. 18. 9  Embedded ICE RT offers real-time debugging with the on-chip Real Monitor software.  The 10-bit A/D converter provides eight analog inputs, with conversion times as overhead.  Two 32-bit timers/external event counters with combined seven capture and seven compare channels.  Two 16-bit timers/external event counters with combined three capture and seven compare channels.  Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz clock input.  Multiple serial interfaces including two UARTs (16C550), two Fast I2 C-buses (400 kbit/s), SPI and SSP with buffering and variable data length capabilities.  Vectored interrupt controller with configurable priorities and vector addresses.  Up to thirty-two 5 V tolerant fast general purpose I/O pins.  Up to 13 edge or level sensitive external interrupt pins available.  70 MHz maximum CPU clock available from programmable on-chip PLL with a possible input frequency of 10  On-chip integrated oscillator operates with an external crystal in the range from 1 MHz to 25 MHz.  Power saving modes include Idle mode, Power-down mode with RTC active, and Power-down mode.  Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization.  Processor wake-up from Power-down mode via external interrupt or RTC.
  19. 19. 10 Ordering Information Table 2.1: Ordering Information Type number Package Description Version Name LPC2101FBD48 LQFP48 plastic low profile quad flat package; 48 leads; SOT313-2 LPC2102FBD48 LQFP48 plastic low profile quad flat package; 48 leads; SOT313-2 LPC2103FBD48 LQFP48 plastic low profile quad flat package; 48 leads; SOT313-2 LPC2103FA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2 Ordering Options Table 2.2: Ordering Options Type number Flash RAM ADC Temperature memory range ( C) LPC2101FBD48 8 kB 2 kB 8 inputs LPC2102FBD48 16 kB 4 kB 8 inputs LPC2103FBD48 32 kB 8 kB 8 inputs LPC2103FA44 32 kB 8 kB 8 inputs
  20. 20. 11 2.1.3 Pin Description Fig 2.1: Pin Diagram LPC2103
  21. 21. 12 2.1.4 Block Diagram Of LPC 2103 Fig 2.2: Block Diagram LPC2103
  22. 22. 13 Table 2.3: Pin Description Symbol LQFP48 PLCC44 Type Description P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. A total of 31 pins of the Port 0 can be used as general purpose bidirectional digital I/Os while P0.31 is an output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block. P0.0/TXD0/ 13 [1] 18 [1] I/O P0.0 Ñ General purpose Input/output digital pin (GPIO). MAT3.1 O TXD0 Ñ Transmitter output for UART0. O MAT3.1 Ñ PWM output 1 for Timer 3. P0.1/RXD0/ 14 [2] 19 [2] I/O P0.1 Ñ General purpose Input/output digital pin (GPIO). MAT3.2 I RXD0 Ñ Receiver input for UART0. O MAT3.2 Ñ PWM output 2 for Timer 3. P0.2/SCL0/ 18 [3] 22 [3] I/O P0.2 Ñ General purpose Input/output digital pin (GPIO). CAP0.0 I/O SCL0 Ñ I 2 C0 clock Input/output. Open-drain output (for I 2 C-bus compliance). I CAP0.0 Ñ Capture input for Timer 0, channel 0. P0.3/SDA0/ 21 [3] 25 [3] I/O P0.3 Ñ General purpose Input/output digital pin (GPIO). MAT0.0 I/O SDA0 Ñ I 2 C0 data input/output. Open-drain output (for I 2 C-bus compliance). O MAT0.0 Ñ PWM output for Timer 0, channel 0. P0.4/SCK0/ 22 [4] 26 [4] I/O P0.4 Ñ General purpose Input/output digital pin (GPIO). CAP0.1 I/O SCK0 Ñ Serial clock for SPI0. SPI clock output from master or input to slave. I CAP0.1 Ñ Capture input for Timer 0, channel 1. P0.5/MISO0/ 23 [4] 27 [4] I/O P0.5 Ñ General purpose Input/output digital pin (GPIO). MAT0.1 I/O MISO0 Ñ Master In Slave OUT for SPI0. Data input to SPI master or data output from SPI slave. O MAT0.1 Ñ PWM output for Timer 0, channel 1. P0.6/MOSI0/ 24 [4] 28 [4] I/O P0.6 Ñ General purpose Input/output digital pin (GPIO). CAP0.2 I/O MOSI0 Ñ Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave. I CAP0.2 Ñ Capture input for Timer 0, channel 2. P0.7/SSEL0/ 28 [2] 31 [2] I/O P0.7 Ñ General purpose Input/output digital pin
  23. 23. 14 (GPIO). MAT2.0 I SSEL0 Ñ Slave Select for SPI0. Selects the SPI interface as a slave. O MAT2.0 Ñ PWM output for Timer 2, channel 0. P0.8/TXD1/ 29 [4] 32 [4] I/O P0.8 Ñ General purpose Input/output digital pin (GPIO). MAT2.1 O TXD1 Ñ Transmitter output for UART1. O MAT2.1 Ñ PWM output for Timer 2, channel 1. P0.9/RXD1/ 30 [2] 33 [2] I/O P0.9 Ñ General purpose Input/output digital pin (GPIO). MAT2.2 I RXD1 Ñ Receiver input for UART1. O MAT2.2 Ñ PWM output for Timer 2, channel 2. z 35 [4] 38 [4] I/O P0.10 Ñ General purpose Input/output digital pin (GPIO). CAP1.0/AD0.3 O RTS1 Ñ Request to Send output for UART1. I CAP1.0 Ñ Capture input for Timer 1, channel 0. I AD0.3 Ñ ADC 0, input 3. P0.11/CTS1/ 36 [3] 39 [3] I/O P0.11 Ñ General purpose Input/output digital pin (GPIO). CAP1.1/AD0.4 I CTS1 Ñ Clear to Send input for UART1. I CAP1.1 Ñ Capture input for Timer 1, channel 1. I AD0.4 Ñ ADC 0, input 4. P0.12/DSR1/ 37 [4] 40 [4] I/O P0.12 Ñ General purpose Input/output digital pin (GPIO). MAT1.0/AD0.5 I DSR1 Ñ Data Set Ready input for UART1. O MAT1.0 Ñ PWM output for Timer 1, channel 0. I AD0.5 Ñ ADC 0, input 5. P0.13/DTR1/ 41 [4] 43 [4] I/O P0.13 Ñ General purpose Input/output digital pin (GPIO). MAT1.1 O DTR1 Ñ Data Terminal Ready output for UART1. O MAT1.1 Ñ PWM output for Timer 1, channel 1. P0.14/DCD1/ 44 [3] 2 [3] I/O P0.14 Ñ General purpose Input/output digital pin (GPIO). SCK1/EINT1 I DCD1 Ñ Data Carrier Detect input for UART1. I/O SCK1 Ñ Serial Clock for SPI1. SPI clock output from master or input to slave. I EINT1 Ñ External interrupt 1 input. P0.15/RI1/ 45 [4] 3 [4] I/O P0.15 Ñ General purpose Input/output digital pin (GPIO). EINT2 I RI1 Ñ Ring Indicator input for UART1. I EINT2 Ñ External interrupt 2 input. P0.16/EINT0/ 46 [2] 4 [2] I/O P0.16 Ñ General purpose Input/output digital pin (GPIO). MAT0.2 I EINT0 Ñ External interrupt 0 input.
  24. 24. 15 O MAT0.2 Ñ PWM output for Timer 0, channel 2. P0.17/CAP1.2/ 47 [1] 5 [1] I/O P0.17 Ñ General purpose Input/output digital pin (GPIO). SCL1 I CAP1.2 Ñ Capture input for Timer 1, channel 2. I/O SCL1 Ñ I 2 C1 clock Input/output. Open-drain output (for I 2 C-bus compliance). P0.18/CAP1.3/ 48 [1] 6 [1] I/O P0.18 Ñ General purpose Input/output digital pin (GPIO). SDA1 I CAP1.3 Ñ Capture input for Timer 1, channel 3. I/O SDA1 Ñ I 2 C1 data Input/output. Open-drain output (for I 2 C-bus compliance). P0.19/MAT1.2/ 1 [1] 7 [1] I/O P0.19 Ñ General purpose Input/output digital pin (GPIO). MISO1 O MAT1.2 Ñ PWM output for Timer 1, channel 2. I/O MISO1 Ñ Master In Slave Out for SSP. Data input to SPI master or data output from SSP slave. P0.20/MAT1.3/ 2 [2] 8 [2] I/O P0.20 Ñ General purpose Input/output digital pin (GPIO). MOSI1 O MAT1.3 Ñ PWM output for Timer 1, channel 3. I/O MOSI1 Ñ Master Out Slave for SSP. Data output from SSP master or data input to SSP slave. P0.21/SSEL1/ 3 [4] 9 [4] I/O P0.21 Ñ General purpose Input/output digital pin (GPIO). MAT3.0 I SSEL1 Ñ Slave Select for SPI1. Selects the SPI interface as a slave. O MAT3.0 Ñ PWM output for Timer 3, channel 0. P0.22/AD0.0 32 [4] 35 [4] I/O P0.22 Ñ General purpose Input/output digital pin (GPIO). I AD0.0 Ñ ADC 0, input 0. P0.23/AD0.1 33 [1] 36 [1] I/O P0.23 Ñ General purpose Input/output digital pin (GPIO). I AD0.1 Ñ ADC 0, input 1. P0.24/AD0.2 34 [1] 37 [1] I/O P0.24 Ñ General purpose Input/output digital pin (GPIO). I AD0.2 Ñ ADC 0, input 2. P0.25/AD0.6 38 [1] 41 [1] I/O P0.25 Ñ General purpose Input/output digital pin (GPIO). I AD0.6 Ñ ADC 0, input 6. P0.26/AD0.7 39 [1] n.c. I/O P0.26 Ñ General purpose Input/output digital pin (GPIO). I AD0.7 Ñ ADC 0, input 7. P0.27/TRST/ 8 [4] 13 [4] I/O P0.27 Ñ General purpose Input/output digital pin (GPIO). CAP2.0 I TRST Ñ Test Reset for JTAG interface.
  25. 25. 16 I CAP2.0 Ñ Capture input for Timer 2, channel 0. P0.28/TMS/ 9 [4] 14 [4] I/O P0.28 Ñ General purpose Input/output digital pin (GPIO). CAP2.1 I TMS Ñ Test Mode Select for JTAG interface. I CAP2.1 Ñ Capture input for Timer 2, channel 1. P0.29/TCK/ 10 [4] 15 [4] I/O P0.29 Ñ General purpose Input/output digital pin (GPIO). CAP2.2 I TCK Ñ Test Clock for JTAG interface. I CAP2.2 Ñ Capture input for Timer 2, channel 2. P0.30/TDI/ 15 [4] 20 [4] I/O P0.30 Ñ General purpose Input/output digital pin (GPIO). MAT3.3 I TDI Ñ Test Data In for JTAG interface. O MAT3.3 Ñ PWM output 3 for Timer 3. P0.31/TDO 16 [4] 21 [4] O P0.31 Ñ General purpose output only digital pin (GPIO). O TDO Ñ Test Data Out for JTAG interface. RTXC1 20 [5] 24 [5] I Input to the RTC oscillator circuit. RTXC2 25 [5] 29 [5] O Output from the RTC oscillator circuit. RTCK 26 [5] n.c. I/O Returned test clock output: Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. X1 11 16 I Input to the oscillator circuit and internal clock generator circuits. X2 12 17 O Output from the oscillator amplifier. DBGSEL 27 30 I Debug select: When LOW, the part operates normally. When HIGH, debug mode is entered. Input with internal pull-down. 6 11 I External reset input: A LOW on this pin resets the device, RST causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. V SS 7, 19, 43 1, 12, 23 I Ground: 0 V reference. V SSA 31 34 I Analog ground: 0 V reference. This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. V DDA 42 44 I Analog 3.3 V power supply: This should be nominally the same voltage as VDD(3V3) but should be isolated to
  26. 26. 17 minimize noise and error. This voltage is used to power the on-chip PLL. This pin also provides a voltage reference level for the ADC. V DD(1V8) 5 10 I 1.8 V core power supply: This is the power supply voltage for internal circuitry. V DD(3V3) 17, 40 42 I 3.3 V pad power supply: This is the power supply voltage for the I/O ports. VBAT 4 n.c. I RTC power supply: 3.3 V on this pin supplies the power to the RTC.  5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.  5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.  Open-drain 5 V tolerant digital I/O I2 C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output functionality.  5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled.  Pad provides special analog functionality. 2.1.5 Architectural Overview The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its
  27. 27. 18 successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:  The standard 32-bit ARM set.  A 16-bit Thumb set. The Thumb sets 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMÕs performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2101/2102/2103 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30 % over Thumb mode. 2.1.6 Functional Description On-Chip flash Program Memory The LPC2101/2102/2103 incorporate a 8 kB, 16 kB or 32 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. The entire flash memory is available for user code as the bootloader On-Chip Static Ram On-chip static RAM may be used for code and/or data storage. The SRAM may
  28. 28. 19 be accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/2102/2103 provide 2 kB, 4 kB or 8 kB of static RAM. Memory Map The LPC2101/2102/2103 memory map incorporates several distinct regions, as shown in Figure 4. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. Fig 2.3: The LPC2101/2102/2103 memory map Interrupt Controller The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
  29. 29. 20 combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non- vectored IRQs. The default routine can read another VIC register to see what IRQs are active. Interrupt Sources Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Pin Connect Block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module with its pin select registers defines the functionality of the microcontroller in a given hardware environment. After reset all pins of Port 0 are configured as input with the following exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality. The pins associated with
  30. 30. 21 the I2 C0 interface are open-drain. Fast General Purpose Parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins.  LPC2101/2102/2103 introduce accelerated GPIO functions over prior LPC2000 devices:  GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.  Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.  All GPIO registers are byte addressable.  Entire port value can be written in one instruction. Features  Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port.  Direction control of individual bits.  Separate control of output set and clear.  All I/O default to inputs after reset. 10-Bit A/D Converter The LPC2101/2102/2103 contain one analog to digital converter. It is a single 10-bit successive approximation analog to digital converter with eight channels. Features  Measurement range of 0 V to 3.3 V.  Each converter capable of performing more than 400,000 10-bit samples per second.
  31. 31. 22  Burst conversion mode for single or multiple inputs.  Optional conversion on transition on input pin or Timer Match signal.  Every analog input has a dedicated result register to reduce interrupt overhead. UARTs The LPC2101/2102/2103 each contain two UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/2102/2103 include a fractional baud rate generator for both UARTs. Standard baud rates such as 115200 can be achieved with any crystal frequency above 2 MHz. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs. UART1 is equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). I 2 C-BUS Serial I/O Controllers The LPC2101/2102/2103 each contain two I2 C-bus controllers. The I2 C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line (SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the capability to both receive and send information such as serial memory. Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2 C-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2 C-bus implemented in LPC2101/2102/2103 supports bit rates up to 400 kbit/s (Fast I2 C). Features  Compliant with standard I2 C-bus interface.  Easy to configure as Master, Slave, or Master/Slave.  Programmable clocks allow versatile rate control.
  32. 32. 23  Bidirectional data transfer between masters and slaves.  Multi-master bus (no central master).  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.  Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.  Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.  The I2 C-bus can also be used for test and diagnostic purposes. SPI Serial I/O Controller The LPC2101/2102/2103 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. SSP Serial I/O Controller The LPC2101/2102/2103 each contain one SSP. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. However, only a single master & a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits flowing from the master to the slave and from the slave to the master. Often only one of these data streams carries meaningful data. Features  Compatible with Motorola SPI, 4-wire TIÕs SSI and National Semiconductors Microwire buses.  Synchronous Serial Communication.  Master or slave operation.
  33. 33. 24  8-frame FIFOs for both transmit and receive.  Four bits to 16 bits per frame. 2.1.7 GPIO General Purpose 32-Bit Timers/External Event Counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ÔorÕ and ÔandÕ, as well as ÔbroadcastÕ functions among them. The LPC2101/2102/2103 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts. Features  A 32-bit timer/counter with a programmable 32-bit prescaler.  External event counter or timer operation.  Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.  Four 32-bit match registers that allow:  Continuous operation with optional interrupt generation on match.  Stop timer on match with optional interrupt generation.  Reset timer on match with optional interrupt generation.  Four external outputs per timer/counter corresponding to match registers, with the following capabilities:  Set LOW on match.
  34. 34. 25 General Purpose 16-Bit Timers/External Event Counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes three capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ÔorÕ and ÔandÕ, as well as ÔbroadcastÕ functions among them. The LPC2101/2102/2103 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts. Features  Two 16-bit timer/counters with a programmable 16-bit prescaler.  External event counter or timer operation.  Three 16-bit capture channels that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.  Four 16-bit match registers that allow:  Continuous operation with optional interrupt generation on match.  Stop timer on match with optional interrupt generation.  Reset timer on match with optional interrupt generation.  Four external outputs per timer/counter corresponding to match registers, with the following capabilities:  Set LOW on match.  Set HIGH on match.  Toggle on match.
  35. 35. 26  Do nothing on match. Watchdog Timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ÔfeedÕ (or reload) the watchdog within a predetermined amount of time. Crystal Oscillator On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 Mhz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected. PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, Reset and Wake-Up Timer Reset has two sources on the LPC2101/2102/2103: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the wake-up timer (see wake-up timer
  36. 36. 27 description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization.When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined reset values. The wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. Code Security This feature of the LPC2101/2102/2103 allow an application to control whether it can be debugged or protected from observation. If after reset on-chip bootloader detects a valid checksum in flash and reads 0x8765 4321 from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be protected from observation. Once debugging is disabled, it can only be enabled by performing a full chip erase using the ISP. External Interrupt Inputs The LPC2101/2102/2103 include up to three edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events
  37. 37. 28 can be processed as three independent interrupt signals. The External Interrupt Inputs can optionally be used to wake-up the processor from Power-down mode. Additionally all 10 capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode. Memory Mapping Control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts. Power Control The LPC2101/2102/2103 supports two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip RTC will enable the microcontroller to have the RTC active during Power-down mode. Power-down current is increased with RTC active. However, it is significantly lower than in Idle mode. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during active and Idle mode.
  38. 38. 29 2.2 POWER SUPPLY All digital circuits require regulated power supply. In this article we are going to learn how to get a regulated positive supply from the mains supply. Fig 2.4 Block Diagram Power Supply Transformer Fig 2.5: Transformer A transformer consists of two coils also called as “WINDINGS” namely PRIMARY & SECONDARY. They are linked together through inductively coupled electrical conductors also called as CORE. A changing current in the primary causes a change in the Magnetic Field in the core & this in turn induces an alternating voltage in the secondary coil. If load is applied to the secondary then an alternating current will flow through the load. If we consider an ideal condition then all the energy from the primary circuit will be transferred to the secondary circuit through the magnetic field. So
  39. 39. 30 The secondary voltage of the transformer depends on the number of turns in the Primary as well as in the secondary. Rectifier A rectifier is a device that converts an AC signal into DC signal. For rectification purpose we use a diode, a diode is a device that allows current to pass only in one direction i.e. when the anode of the diode is positive with respect to the cathode also called as forward biased condition & blocks current in the reversed biased condition. Rectifier can be classified as follows: 1) Half Wave rectifier. This is the simplest type of rectifier as you can see in the diagram a half wave rectifier consists of only one diode. Fig 2.6: Half Wave Rectifier When an AC signal is applied to it during the positive half cycle the diode is forward biased & current flows through it. But during the negative half cycle diode is reverse biased & no current flows through it. Since only one half of the input reaches the output, it is very inefficient to be used in power supplies.
  40. 40. 31 2) Full wave rectifier. Fig 2.7: Full Wave Rectifier Half wave rectifier is quite simple but it is very inefficient, for greater efficiency we would like to use both the half cycles of the AC signal. This can be achieved by using a center tapped transformer i.e. we would have to double the size of secondary winding & provide connection to the center. So during the positive half cycle diode D1 conducts & D2 is in reverse biased condition. During the negative half cycle diode D2 conducts & D1 is reverse biased. Thus we get both the half cycles across the load. One of the disadvantages of Full Wave Rectifier design is the necessity of using a center tapped transformer, thus increasing the size & cost of the circuit. This can be avoided by using the Full Wave Bridge Rectifier. 3) Bridge Rectifier. Fig 2.8: Bridge Rectifier As the name suggests it converts the full wave i.e. both the positive & the negative half cycle into DC thus it is much more efficient than Half Wave Rectifier & that too without using a center tapped transformer thus much more cost effective than Full Wave Rectifier.
  41. 41. 32 Full Bridge Wave Rectifier consists of four diodes namely D1, D2, D3 and D4. During the positive half cycle diodes D1 & D4 conduct whereas in the negative half cycle diodes D2 & D3 conduct thus the diodes keep switching the transformer connections so we get positive half cycles in the output. Figure 2.9: Center Tapped Rectifier If we use a center tapped transformer for a bridge rectifier we can get both positive & negative half cycles which can thus be used for generating fixed positive & fixed negative voltages. Filter Capacitor Even though half wave & full wave rectifier give DC output, none of them provides a constant output voltage. For this we require to smoothen the waveform received from the rectifier. This can be done by using a capacitor at the output of the rectifier this capacitor is also called as “FILTER CAPACITOR” or “SMOOTHING CAPACITOR” or “RESERVOIR CAPACITOR”. Even after using this capacitor a small amount of ripple will remain. We place the Filter Capacitor at the output of the rectifier the capacitor will charge to the peak voltage during each half cycle then will discharge its stored energy slowly through the load while the rectified voltage drops to zero, thus trying to keep the voltage as constant as possible. If we go on increasing the value of the filter capacitor then the Ripple will decrease. But then the costing will increase. The value of the Filter capacitor depends on the current consumed by the circuit, the frequency of the waveform & the accepted ripple.
  42. 42. 33 Where, Vr= accepted ripple voltage.( should not be more than 10% of the voltage) I= current consumed by the circuit in Amperes. F= frequency of the waveform. A half wave rectifier has only one peak in one cycle so F=25hz Whereas a full wave rectifier has Two peaks in one cycle so F=100hz. Voltage Regulator A Voltage regulator is a device which converts varying input voltage into a constant regulated output voltage. Voltage regulator can be of two types 1) Linear Voltage Regulator Also called as Resistive Voltage regulator because they dissipate the excessive voltage resistively as heat. 2) Switching Regulators. They regulate the output voltage by switching the Current ON/OFF very rapidly. Since their output is either ON or OFF it dissipates very low power thus achieving higher efficiency as compared to linear voltage regulators. But they are more complex & generate high noise due to their switching action. For low level of output power switching regulators tend to be costly but for higher output wattage they are much cheaper than linear regulators. The most commonly available Linear Positive Voltage Regulators are the 78XX series where the XX indicates the output voltage. And 79XX series is for Negative Voltage Regulators.
  43. 43. 34 Fig 2.10: Voltage Regulator After filtering the rectifier output the signal is given to a voltage regulator. The maximum input voltage that can be applied at the input is 35V.Normally there is a 2-3 Volts drop across the regulator so the input voltage should be at least 2-3 Volts higher than the output voltage. If the input voltage gets below the Vmin of the regulator due to the ripple voltage or due to any other reason the voltage regulator will not be able to produce the correct regulated voltage. Figure 2.11: Circuit Diagram of power supply 2.3 IC 7805: 7805 is an integrated three-terminal positive fixed linear voltage regulator. It supports an input voltage of 10 volts to 35 volts and output voltage of 5 volts. It has a current rating of 1 amp although lower current models are available. Its output voltage is fixed at 5.0V. The 7805 also has a built-in current limiter as a safety feature. 7805 is manufactured by many companies, including National Semiconductors and Fairchild Semiconductors. The 7805 will automatically reduce output current if it gets too hot.The last two digits represent the voltage; for instance, the 7812 is a 12-volt regulator. The 78xx series of regulators is designed to work in complement with the 79xx series of negative voltage
  44. 44. 35 regulators in systems that provide both positive and negative regulated voltages, since the 78xx series can't regulate negative voltages in such a system. The 7805 & 78 is one of the most common and well-known of the 78xx series regulators, as it's small component count and medium-power regulated 5V make it useful for powering TTL devices. Below is the table showing the specifications of IC 7805 Table 2.4 Specifications Of IC7805 2.4 LIQUID CRYSTAL DISPLAY (LCD) To display interactive messages we are using LCD Module. We examine an intelligent LCD display of two lines,16 characters per line that is interfaced to the controllers. The protocol (handshaking) for the display is as shown. Whereas D0 to D7th bit is the Data lines, RS, RW and EN pins are the control pins and remaining pins are +5V, -5V and GND to provide supply. Where RS is the Register Select, RW is the Read Write and EN is the Enable pin. The display contains two internal byte-wide registers, one for commands (RS=0) and the second for characters to be displayed (RS=1). It also contains a user-programmed RAM area (the character RAM) that can be programmed to generate any desired character that can be formed using a dot matrix. To distinguish between these two data areas, the hex command byte 80 will be used to signify that the display RAM address 00h will be chosen.Port1 is used to furnish the command or data type, and ports 3.2 to3.4 SPECIFICATIONS IC 7805 Vout 5V Vein - Vout Difference 5V - 20V Operation Ambient Temp 0 - 125°C Output Imax 1A
  45. 45. 36 furnish register select and read/write levels. The display takes varying amounts of time to accomplish the functions as listed. LCD bit 7 is monitored for logic high (busy) to ensure the display is overwritten. Liquid Crystal Display also called as LCD is very helpful in providing user interface as well as for debugging purpose. The most common type of LCD controller is HITACHI 44780 which provides a simple interface between the controller & an LCD. These LCD's are very simple to interface with the controller as well as are cost effective. Figure 2.12: 2x16 Line Alphanumeric LCD Display The most commonly used ALPHANUMERIC displays are 1x16 (Single Line & 16 characters), 2x16 (Double Line & 16 character per line) & 4x20 (four lines & Twenty characters per line). The LCD requires 3 control lines (RS, R/W & EN) & 8 (or 4) data lines. The number on data lines depends on the mode of operation. If operated in 8-bit mode then 8 data lines + 3 control lines i.e. total 11 lines are required. And if operated in 4-bit mode then 4 data lines + 3 control lines i.e. 7 lines are required. How do we decide which mode to use? It’s simple if you have sufficient data lines you can go for 8 bit mode & if there is a time constrain i.e. display should be faster then we have to use 8-bit mode because basically 4- bit mode takes twice as more time as compared to 8-bit mode. Table 2.5: Pins of LCD Pin Symbol Function 1 Vss Ground 2 Vdd Supply Voltage 3 Vo Contrast Setting 4 RS Register Select 5 R/W Read/Write Select 6 En Chip Enable Signal 7-14 DB0-DB7 Data Lines 15 A/Vee Gnd for the backlight 16 K Vcc for backlight
  46. 46. 37 When RS is low (0), the data is to be treated as a command. When RS is high (1), the data being sent is considered as text data which should be displayed on the screen. When R/W is low (0), the information on the data bus is being written to the LCD. When RW is high (1), the program is effectively reading from the LCD. Most of the times there is no need to read from the LCD so this line can directly be connected to Gnd thus saving one controller line. The ENABLE pin is used to latch the data present on the data pins. A HIGH - LOW signal is required to latch the data. The LCD interprets and executes our command at the instant the EN line is brought low. If you never bring EN low, your instruction will never be executed. Fig 2.13: Architecture of LCD with Controller Commands Used In LED
  47. 47. 38 2.5 MAX 232 Fig 2.14: MAX 232 RS-232 Waveform Fig 2.15: TTL/CMOS Serial Logic Waveform The diagram above shows the expected waveform from the UART when using the common 8N1 format. 8N1 signifies 8 Data bits, No Parity and 1 Stop Bit. The RS-232 line, when idle is in the Mark State (Logic 1). A transmission starts with a start bit which is (Logic 0). Then each bit is sent down the line, one at a time. The LSB (Least Significant Bit) is sent first. A Stop Bit (Logic 1) is then appended to the signal to make up the transmission. The data sent using this method, is said to be framed. That is the data is framed between a Start and Stop Bit. RS-232 Voltage Levels  +3 to +25 volts to signify a "Space" (Logic 0)  -3 to -25 volts for a "Mark" (logic 1).  Any voltage in between these regions (i.e. between +3 and -3 Volts) is undefined. The data byte is always transmitted least-significant-bit first.
  48. 48. 39 The bits are transmitted at specific time intervals determined by the baud rate of the serial signal. This is the signal present on the RS-232 Port of your computer, shown below. Fig 2.16: RS-232 Logic Waveform RS-232 Level Converter Standard serial interfacing of microcontroller (TTL) with PC or any RS232C Standard device , requires TTL to RS232 Level converter . A MAX232 is used for this purpose. It provides 2-channel RS232C port and requires external 10uF capacitors. The driver requires a single supply of +5V. Fig 2.17: RS-232 Level Converter MAX-232 includes a Charge Pump, which generates +10V and -10V from a single 5v supply.
  49. 49. 40 Serial Communication When a processor communicates with the outside world, it provides data in byte sized chunks. Computers transfer data in two ways: parallel and serial. In parallel data transfers, often more lines are used to transfer data to a device and 8 bit data path is expensive. The serial communication transfer uses only a single data line instead of the 8 bit data line of parallel communication which makes the data transfer not only cheaper but also makes it possible for two computers located in two different cities to communicate over telephone. Serial data communication uses two methods, asynchronous and synchronous. The synchronous method transfers data at a time while the asynchronous transfers a single byte at a time. There are some special IC chips made by many manufacturers for data communications. These chips are commonly referred to as UART (universal asynchronous receiver-transmitter) and USART (universal synchronous asynchronous receiver transmitter). The AT89C51 chip has a built in UART. In asynchronous method, each character is placed between start and stop bits. This is called framing. In data framing of asynchronous communications, the data, such as ASCII characters, are packed in between a start and stop bit. We have a total of 10 bits for a character: 8 bits for the ASCII code and 1 bit each for the start and stop bits. The rate of serial data transfer communication is stated in bps or it can be called as baud rate. To allow the compatibility among data communication equipment made by various manufacturers, and interfacing standard called RS232 was set by the Electronics industries Association in 1960. Today RS232 is the most widely used I/O interfacing standard. This standard is used in PCs and numerous types of equipment. However, since the standard was set long before the advent of the TTL logic family, its input and output voltage levels are not TTL compatible. In RS232, a 1 bit is represented by -3 to -25V, while a 0 bit is represented +3 to +25 V, making -3 to +3 undefined. For this reason, to connect any RS232 to a microcontroller system we must use voltage converters such as MAX232 to connect the TTL logic levels to RS232 voltage levels and vice versa. MAX232 ICs are commonly referred to as line drivers.
  50. 50. 41 Fig 2.18: MAX 232 to RS232 Internal Connection The RS232 cables are generally referred to as DB-9 connector. In labeling, DB-9P refers to the plug connector (male) and DB-9S is for the socket connector (female). The simplest connection between a PC and microcontroller requires a minimum of three pin, TXD, RXD, and ground. Many of the pins of the RS232 connector are used for handshaking signals. They are bypassed since they are not supported by the UART chip. Fig 2.19: RS 232 Port IBM PC/ compatible computers based on x86(8086, 80286, 386, 486 and Pentium) microprocessors normally have two COM ports. Both COM ports have RS232 type connectors. Many PCs use one each of the DB-25 and DB-9 RS232 connectors. The COM ports are designated as COM1 and COM2. We can connect the serial port to the COM 2 port of a PC for serial communication experiments. We use a DB9 connector in our arrangement.
  51. 51. 42 2.7 KEY PAD Fig 2.24: Finger Print Module Interfacing Keypad Circuit: If the application is so time sensitive that the delays associated with de bouncing and awaiting an all up cannot be tolerated then some form of interrupt must be used so that the main program can run unhindered. A compromise may be made by polling the keyboard as the main program loops, but all time delays are don using timers so that the main program does not wait for a software delay. The get key program can be modified to use a timer to generate the delays associated with the key down de bounce time and the all up delay. The challenge associated with this approach is to have the program remember which delay is being timed out. Remembering which delay is in progress can be handled using a flag bit or one timer can be used to generate the key down de bounce delay and another timer to generate the key up delay. The two timer approach is examined in the example given in this section. The important feature of this approach is that the main program will check a flag to see whether there is any Keyboard activity. If the flag is set then the program finds the key stored in a ram location and resets the flag. The getting of the key is transparent to the main program it is done in the interrupt program. As you have seen interfacing switches to microcontroller normally the port pin is high but when a switch is pressed the controller pin gets a Low signal and we come to know that a switch has been pressed. One end of switch is connected to the port pin whereas the other end is connected to the Ground.
  52. 52. 43 In case of matrix Keypad both the ends of switches are connected to the port Pin.Over here we have considered a 4x3 matrix keypad i.e. four rows and three columns. So in all twelve switches have been interfaced using just seven lines. The adjoining figure shows the diagram of a matrix keypad and how it is interfaced with the controller. Fig 2.25: Finger Print Internal Architecture As you can see no pin is connected to ground, over here the controller pin itself provides the ground. We pull one of the Column Pins low & check the row pins if any of the Pin is low then we come to know which switch is pressed. Suppose we make column 1 pin low and while checking the rows we get Row 3 is low then we come to know switch 7 has been pressed. Algorithm for Keypad 1. Start. 2. Make All Pins High. 3. Make Column 1 pin low. 4. Check if Row 1 is low, if yes then Switch 1 has been pressed. 5. Check if Row 2 is low, if yes then Switch 4 has been pressed. 6. Check if row 3 is low if yes then Switch 7 has been pressed. 7. Check if row 4 is low if yes then Switch 10 has been pressed. 8. Make Column 1 Pin high & Column 2 Pin Low. 9. Check if Row 1 is low, if yes then Switch 2 has been pressed. 10. Check if Row 2 is low, if yes then Switch 5 has been pressed. 11. Check if row 3 is low if yes then Switch 8 has been pressed.
  53. 53. 44 12. Check if row 4 is low if yes then Switch 11 has been pressed. 13. Make Column 2 Pin high & Column 3 Pin Low. 14. Check if Row 1 is low, if yes then Switch 3 has been pressed. 15. Check if Row 2 is low, if yes then Switch 6 has been pressed. 16. Check if row 3 is low if yes then Switch 9 has been pressed. 17. Check if row 4 is low if yes then Switch 12 has been pressed. 18. Make column 3 pin high 19. Stop
  54. 54. 45 Chapter 3 GSM AND FINGER PRINT MODULE 3.1 INTRODUCTION TO GSM The words, “Mobile Station” (MS) or “Mobile Equipment” (ME) are used for mobile terminals supporting GSM services. A call from a GSM mobile station to the PSTN is called a “mobile originated call” (MOC) or “Outgoing call”, and a call from a fixed network to a GSM mobile station is called a “mobile Terminated call” (MTC) or “incoming call”. Fig 3.1: GSM Modem What Is GSM? GSM (Global System for Mobile communications) is an open, digital cellular technology used for transmitting mobile voice and data services. What Does GSM Offer? GSM supports voice calls and data transfer speeds of up to 9.6 kbit/s, together with the transmission of SMS (Short Message Service). GSM operates in the 900MHz and 1.8GHz bands in Europe and the 1.9GHz and 850MHz bands in the US. The 850MHz band is also used for GSM and 3G in Australia, Canada and many South American countries. By having harmonized spectrum across most of the globe, GSM’s international roaming capability allows users to access the same services when travelling
  55. 55. 46 abroad as at home. This gives consumers seamless and same number connectivity in more than 218 countries. Terrestrial GSM networks now cover more than 80% of the world’s population. GSM satellite roaming has also extended service access to areas where terrestrial coverage is not available History In 1980’s the analog cellular telephone systems were growing rapidly all throughout Europe, France and Germany. Each country defined its own protocols and frequencies to work on. For example UK used the Total Access Communication System (TACS), USA used the AMPS technology and Germany used the C-netz technology. None of these systems were interoperable and also they were analog in nature. In 1982 the Conference of European Posts and Telegraphs (CEPT) formed a study group called the GROUPE SPECIAL MOBILE (GSM) The main area this focused on was to get the cellular system working throughout the world, and ISDN compatibility with the ability to incorporate any future enhancements. In 1989 the GSM transferred the work to the European Telecommunications Standards Institute (ETSI.) the ETS defined all the standards used in GSM. 3.1.1 Basics of working and specifications of GSM The GSM architecture is nothing but a network of computers. The system has to partition available frequency and assign only that part of the frequency spectrum to any base transreceiver station and also has to reuse the scarce frequency as often as possible. GSM uses TDMA and FDMA together. Graphically this can be shown below – Fig 3.2: Representation of a GSM signal using TDMA & FDMA with respect to the transmitted power.
  56. 56. 47 Some of the Technical Specifications of GSM are listed below – Multiple Access Method TDMA / FDMA Uplink frequencies (MHz) 933-960 (basic GSM) Downlink frequencies (MHz) 890-915 (basic GSM) Duplexing FDD Channel spacing, kHz 200 Modulation GMSK Portable TX power, maximum / average (mW) 1000 / 125 Power control, handset and BSS Yes Speech coding and rate (kbps) RPE-LTP / 13 Speech Channels per RF channel: 8 Channel rate (kbps) 270.833 Channel coding Rate 1/2 convolution Frame duration (ms) 4.615 GSM was originally defined for the 900 Mhz range but after some time even the 1800 Mhz range was used for cellular technology. The 1800 MHz range has its architecture and specifications almost same to that of the 900 Mhz GSM technology but building the Mobile exchanges is easier and the high frequency Synergy effects add to the advantages of the 1800 Mhz range. 3.1.2 Architecture and Building Blocks  GSM is mainly built on 3 building blocks. (Ref Fig. 3.3)  GSM Radio Network – This is concerned with the signaling of the system. Hand- overs occur in the radio network. Each BTS is allocated a set of frequency channels.
  57. 57. 48  GSM Mobile switching Network – This network is concerned with the storage of data required for routing and service provision.  GSM Operation and Maintenance – The task carried out by it include Administration and commercial operation , Security management, Network configuration, operation, performance management and maintenance tasks. Fig 3.3: The basic blocks of the whole GSM system Explanations of some of the abbreviations used – Table 3.1: abbreviations Signaling Schemes and Ciphering Codes Used Public Land Mobile Network(PLMN) The whole GSM system Mobile System (MS) The actual cell phone that we use Base Transceiver Station (BTS) Provides connectivity between network and mobile station via the Air- interface BaseStationController(BSC) Controls the whole subsystem. Transcoding Rate & Adaption Unit (TRAU) This is instrumental in compressing the Data that is passed on to the network, is a part of the BSS. Mobile Services Switching Center The BSC is connected to the MSC. The MSC
  58. 58. 49 (MSC) routes the incoming and outgoing calls and assigns user cannels on the A- interface. Home Location Register (HLR) This register stores data of large no of users. It is like a database that manages data of all the users. Every PLMN will have atleast one HLR. Visitor Location Resigter (VLR) This contains part of data so that the HLR is not overloaded with inquiries. If a subscriber moves out of VLR area the HLR requests removal of data related to that user from the VLR. Equipment Identity Register (EIR) The IMEI no. is allocated by the manufacturer and is stored on the network in the EIR. A stolen phone can be made completely useless by the network/s if the IMEI no is known. GSM is digital but voice is inherently analog. So the analog signal has to be converted and then transmitted. The coding scheme used by GSM is RPE-LTP (Rectangular pulse Excitation – Long Term Prediction) Fig 3.4: Transmitter for the voice signal
  59. 59. 50 Fig 3.5: Receiver for the Voice signal The voice signal is sampled at 8000 bits/sec and is quantized to get a 13 bit resolution corresponding to a bit rate of 104 kbits/sec. This signal is given to a speech coder (codec) that compresses this speech into a source-coded speech signal of 260 bit blocks at a bit rate of 13 kbit/sec. The codec achieves a compression ratio of 1:8. The coder also has a Voice activity detector (VAD) and comfort noise synthesizer. The VAD decides whether the current speech frame contains speech or pause, this is turn is used to decide whether to turn on or off the transmitter under the control of the Discontinuous Transmission (DTX). This transmission takes advantage of the fact that during a phone conversation both the parties rarely speak at the same time. Thus the DTX helps in reducing the power consumption and prolonging battery life. The missing speech frames are replaced by synthetic background noise generated by the comfort noise synthesize in a Silence Descriptor (SID) frame. Suppose a loss off speech frame occurs due to noisy transmission and it cannot be corrected by the channel coding protection mechanism then the decoder flags such frames with a bad frame indicator (BFI) In such a case the speech frame is discarded and using a technique called error concealment which calculates the next frame based on the previous frame. 3.1.3 Ciphering Codes MS Authentication algorithm’s These algorithms are stored in the SIM and the operator can decide which one it prefers using.
  60. 60. 51 A3/8 The A3 generates the SRES response to the MSC’s random challenge, RAND which the MSC has received from the HLR. The A3 algorithm gets the RAND from the MSC and the secret key Ki from the SIM as input and generated a 32- bit output, the SRES response. The A8 has a 64 bit Kc output. A5/1 (Over the Air Voice Privacy Algorithm) The A5 algorithm is the stream cipher used to encrypt over the air transmissions. The stream cipher is initialized for every frame sent with the session key Kc and the no. of frames being decrypted / encrypted. The same Kc key is used throughout the call but different 22-bit frame is used. Two Main Interfaces The two main interfaces are the AIR and the ABIS interface. The figure shows the signaling between them. AIR INTERFACE – signaling between MS and BTS ABIS INTERFACE – signaling between BTS and BSC Fig 3.6: Signaling between Air and Abis Interface Air Interface The air interface is like the physical layer in the model. The signaling schemes used in the AIR interface are as follows – 1) Broadcast Control Channel(BCCH) This channel broadcasts a series of information elements to the MS, such as radio channel configuration, synchronization information etc. 2) Frequency Correction Channel (FCCH)
  61. 61. 52 This channel contains information about the correction in transmission frequency broadcasted to MS. 3) Synchronization Channel (SCH) It broadcasts data for the frame synchronization of a MS and information to identify a BSC. 4) Common Control Channel (BCH) This is a point to multi-point signaling channel to deal with access management functions. Consists of 3 channels – 5) Random Access Channel (RACH) It is the Uplink portion, accessed from the mobile stations in a cell to ask for a dedicated signaling channel for 1 transaction. 6) Access Grant Channel (AGCH) It is the downlink portion used to assign a dedicated signaling channel. 7) Notification Channel (NCH) It is used to inform mobile stations about incoming calls and broadcast calls. 8) Dedicated Control Channel (DCCH) It is a Bi-directional point to point signaling channel. Consists of 3 channels – 9) Stand Alone Dedicated Control Channel (SDDCH) – Used for signaling between the BSS and MS when there is no active connection between them. 10) Slow Associated Control Channel (SACCH) – This channel had to continuously transfer data because it is considered as proof of existence of a physical radio connection. 11) Fast Associated Control Channel (FACCH) – This channel is used to make additional band-width available for signaling
  62. 62. 53 3.2. INTRODUCTION TO KY-M6 FINGERPRINT SENSOR MODULE Fig 3.7: Finger Print KY-M6 Fingerprint Sensor Module adopts optic fingerprint sensor, which consists of high-performance DSP and Flash and is able to conduct fingerprint image processing, template generation, template matching, fingerprint searching, template storage, etc. Compared with similar products from other suppliers, KY-M6 proudly boasts of following features: 1. Proprietary Intellectual Property Optic fingerprint enrollment device, KY-M6 hardware as well as fingerprint algorithm are all developed by Key Power Security. 2. Wide Application Range Of Fingerprints With Different Quality Self-adaptive parameter adjustment mechanism is used in the course of fingerprint enrollment. This ensures good image quality for even dry or wet fingers, thus it has wider application range. 3. Immense Improved Algorithm KY-M6 Fingerprint algorithm is specially written according to optic imaging theory. The algorithm is good for low-quality fingers due to its excellent correction and tolerance features.
  63. 63. 54 4. Flexible Application User can easily set KY-M6 Module to different working modes depending on complexity of application systems. User can conduct secondary development with high efficiency and reliability. 5. Easy To Use and Expand It is not necessary for user to have professional knowledge in the field of fingerprint verification. User can develop powerful fingerprint verification application systems with the command set provided by KY-M6. 6. Low Power Consumption Sleep/awake control interface makes KY-M6 suitable for occasions that require low power consumption. 7. Different Security Levels User can set different security level according to different application environment. 8. Applications KY-M6 can be used on all fingerprint verification systems, such as Safety cabinet, door lock, Complicated door-guard system, Fingerprint IC card Identification Terminal, Fingerprint identification and verification system associated with PC. 3.2.1 Specifications Table 3.1: Specifications of Finger Print Module Item Index Parameter Condition 1 Power supply 5V 2 Working current 170mA 3 Peak value current 200mA 4 Fingerprint input time < 250ms 5 1:1 matching time < 600ms Matching features + matching fingerprint 6 1:900 searching time < 2s 7 Fingerprint capacity 160 Can be extended 8 FAR (False Acceptance Rate) < 0. 001 % 9 FRR (False Rejection Rate) < 1.5 % 10 Fingerprint template size 512bytes
  64. 64. 55 Chapter 4 CIRCUITS OPERATION AND FLOW CHART Fig 4.1: Schematic Diagram
  65. 65. 56 4.1.1 OPERATION & PROCEDURE  Switch on the circuit  Wait till the GSM modem catches signal and the rest of the circuit set the preferences to zero  The SIM will be registered  After the SIM is registered , the reservation process begins  Select on the keypad whether to start ticket reservation or ticket verification  Press 1 for reservation , 2 for verification  Select the desired place of travel and enter the correct number on the keypad  After entering the desired location , place the finger on the finger print module  The module will check whether the finger print already exists in the database  If yes , it will show the previously allocated id no of the finger print  If no it will generate a new id and store it in the database.  Once the generation of the id is finished, the LCD screen will display “ID registered successfully " .we can remove the finger from the finger print module now . this process will take a maximum of 10 seconds .  After completing the enrollment of the finger print , we have to make a call to the SIM placed in the GSM module  The call will get automatically disconnected after it gets connected and the passenger gets all the details of the ticket to his cell phone which was used to call the SIM in the GSM modem
  66. 66. 57 4.2 FLOWCHART INITIALIZING ARM7, GSM AND FINGERPRINT MODULES ENROLL FINGERPRINT STORE FINGERPRINT VERIFY FINGERPRINT START RESERVATON PROCESS SEND MESSAGE TO PASSENGER THROUGH GSM STOP NO NO YES YES START Fig 4.2: Flowchart of proposed model
  67. 67. 58 Chapter 5 SOFTWARE DEVELOPMENT 5.1 INTRODUCTION: In this chapter the software used and the language in which the program code is defined is mentioned and the program code dumping tools are explained. The chapter also documents the development of the program for the application. This program has been termed as “Source code”. Before we look at the source code we define the two header files that we have used in the code. 5.2 TOOLS USED: Fig 5.1 Keil Software- internal stages
  68. 68. 59 Keil development tools for the 8051 Microcontroller Architecture support every level of software developer from the professional applications 5.2.1 LPC2103 Compiler & LPC2103 Macro Assembler: Source files are created by the µVision IDE and are passed to the C51 Compiler or A51 Macro Assembler. The compiler and assembler process source files and create replaceable object files. The Keil C51 Compiler is a full ANSI implementation of the C programming language that supports all standard features of the C language. In addition, numerous features for direct support of the 8051 architecture have been added. 5.2.2 µVISION What is µVision3? µVision3 is an IDE (Integrated Development Environment) that helps you write, compile, and debug embedded programs. It encapsulates the following components:  A project manager.  A make facility.  Tool configuration.  Editor.  A powerful debugger.  To help you get started, several example programs (located in the C51Examples, C251Examples, C166Examples, and ARM...Examples) are provided.  HELLO is a simple program that prints the string "Hello World" using the Serial Interface.  MEASURE is a data acquisition system for analog and digital systems.  TRAFFIC is a traffic light controller with the RTX Tiny operating system.  SIEVE is the SIEVE Benchmark.  DHRY is the Dhrystone Benchmark.  WHETS is the Single-Precision Whetstone Benchmark. Additional example programs not listed here are provided for each device architecture.
  69. 69. 60 5.2.3 Building an Application in µVision To build (compile, assemble, and link) an application in µVision2, you must:  Select Project -(forexample,166EXAMPLESHELLOHELLO.UV2).  Select Project - Rebuild all target files or Build target.  µVision2 compiles, assembles, and links the files in your project.  Click on the Keil uVision Icon on Desktop  The following fig will appear The following pictures are the snapshot of the working process on µVision Step1: open the NEW µVision project which is in the project option in the tool bar.
  70. 70. 61 Step2: save the project with the required name and click save button Step:3 select the device from NXP options the window which comes after saving the project.
  71. 71. 62 Step 4: select the LPC 2103 from the NXP options Step 5: click yes in the startup code of LPC 2103 window
  72. 72. 63 Step 6: select the new file from the file options to write the C code Step 7: a new text file will open which we have to write the following code
  73. 73. 64 Step 8 : write the code require for your applications Step 9: save the text file as .C file
  74. 74. 65 Step 10: Add the saved .C file p by right clicking the Source Group Option1 and u will get drop down window in that select Add Files to Group Step 11: select the saved .c file from the window which is showing to add the file by clicking the add tab.
  75. 75. 66 Step 12: thus .C file is added to the Source Group is clearly seen Step 13: press the icon that shows Rebuilt Target which proceeds for the Linking if the .Cfile.
  76. 76. 67 Step 14:Re-built All Target files for complete process of assembling->Compiling - >linking-> generating .hex file Step 15: press the start/stop debug icon for debugging of the code which written. Following are debugging windows press F11 for step by step debug Window 1 Window 2
  77. 77. 68 5.2.4 Flash Magic: Features:  Straightforward and intuitive user interface  Five simple steps to erasing and programming a device and setting any options desired  Programs Intel Hex Files  Automatic verifying after programming  Fills unused flash to increase firmware security  Ability to automatically program checksums. Using the supplied checksum calculation routine your firmware can easily verify the integrity of a Flash block, ensuring no unauthorized or corrupted code can ever be executed  Program security bits  Check which Flash blocks are blank or in use with the ability to easily erase all blocks in use  Read the device signature  Read any section of Flash and save as an Intel Hex File  Reprogram the Boot Vector and Status Byte with the help of confirmation features that prevent accidentally programming incorrect values  Displays the contents of Flash in ASCII and Hexadecimal formats  Single-click access to the manual, Flash Magic home page and NXP Microcontrollers home page  Ability to use high-speed serial communications on devices that support it. Flash Magic calculates the highest baud rate that both the device and your PC can use and switches to that baud rate transparently  Command Line interface allowing Flash Magic to be used in IDEs and Batch Files  Manual in PDF format  supports half-duplex communications  Verify Hex Files previously programmed  Save and open settings
  78. 78. 69  Able to reset Rx2 and 66x devices (revision G or higher)  Able to control the DTR and RTS RS232 signals when connected to RST and /PSEN to place the device into Boot ROM and Execute modes automatically. An example circuit diagram is included in the Manual. This is essential for ISP with target hardware that is hard to access.  This enables us to send commands to place the device in Boot ROM mode, with support for command line interfaces. The installation includes an example project for the Keil and Raisonance 8051 compilers that show how to build support for this feature into applications.  Able to play any Wave file when finished programming.  built in automated version checker - helps ensure you always have the latest version.  Powerful, flexible Just in Time Code feature. Write your own JIT Modules to generate last minute code for programming. Uses include:  Serial number generation  Copy protection and copy authorization  Storing program date and time - manufacture date  Storing program operator and location  Lookup table generation  Language tables or language selection  Centralized record keeping  Obtaining latest firmware from the Corporate Web site or project intranet Requirements: Flash Magic works on any versions of Windows, except Windows 95. 10Mb of disk space is required. As mentioned earlier, we are automating two different routines in our project and hence we used the method of polling to continuously monitor those tasks and act accordingly
  79. 79. 70 Chapter 6 RESULT Fig 6.1 Snapshot of the Working Project
  80. 80. 71 Chapter 7 ADVANTAGES, CONCLUSION AND FUTURE SCOPE ADVANTAGES  Cant tamper with finger print  Reduce third party bookings  Reduce anti social activities in public transport systems.  Bring down the amount of paper i.e. eco friendly DISADVANTAGES  Foreign particles on the finger print may cause a mismatch  Scanners can't recognize if the fingerprint is on a real finger or an artificial one, so it is possible to trick the scanner by using a gelatin print mold over a real finger. APPLICATIONS  Finger print modules can be used wherever there can be a chance of a third party intervention such as bank transactions , house security systems ,etc CONCLUSION Security issues in any public transport systems have to be tackled with efficient technology which will reduce the stress on the working security of the system . So the finger print modules which are used in our project provide a way to reduce the security threats in the system. Moreover in the modern era , we use efficient technologies which are also eco friendly and our project reduces a huge amount of paper work at the reservation counters . Involvement of third party bookings can be reduced by a huge extent. FUTURE SCOPE This system can be introduced in all public transport systems which facilitate long distance travelling. Finger print scanning and biometric scanners can be used in the long run to increase the security of the passengers travelling and reduce activities of anti social elements. This system can also reduce the paperwork and ensure that all third party bookings are avoided.
  81. 81. 72 REFERENCES [1] Steven Holzner (Author), "Visual Basic 6 Black Book: The Only Book You'll Need on Visual Basic" [Paperback], Coriolis Group Books (1998) [2] E. Balagurusamy (Author), "Programming In Ansi C, 5E", Vol 5 Tata McGraw- Hill Education", 2011 [3] Mazidi," The 8051 Microcontroller And Embedded Systems Using Assembly And C, 2/E ",vol 2, Pearson Education India, (2007) [4] Richard Grier (Author), "Visual Basic Programmer's Guide to Serial Communications" [5] "Fingerprint." Wikipedia. Wikipedia, the Free Encyclopedia. 15 Sep. 2008. < http://en.wikipedia.org/wiki/Fingerprint>. [6] "Secugen" SecuGen Corporation November 04, 2012<www.secugen. com> [7] "EIKO" Eikon Technologies <www.eikontech.net>, October 21, 2012 [8] "ROBOKITS",Robokits India Pvt Ltd<www.robokits.com>, December 02, 2012 [9] "Product ID 751." Adafruit Industry, Unique & DIY Fun Kits November 12, 2012 < http://adafruit.com >. [10] "Probots",Global System for Mobile Communication November 02,2012 [11] ARM-systemonchip-architecture by Steve furber. [12] ARM-user manual UM10114. [13] ARM System Developers Guide by Andrew N.SLOSS [14] "Power Electronics” by M D Singh and K B Khanchandan [15] "Linear Integrated Circuits” by D Roy Choudary & Shail Jain [16] "Electrical Machines” by S K Bhattacharya [17] "Electrical Machines II” by B L Thereja
  82. 82. 73 APPENDIX – A SOURCE CODE A.1 SOURCE CODE FOR LCD #define LCD_Data (0xFF)<<16 #define RS (0xFFFFFFFF)<<31 #define EN (1<<30) unsigned char LCD_C=0,LCD_D=1,Wr_Data=1; void Delay(unsigned int ); void Lcd_Init(void); int Lcd_Data_Chr(unsigned char ,unsigned char ,unsigned char ,unsigned char); int Lcd_Data_Str(unsigned char ,unsigned char ,unsigned char temp[]); int Lcd_Wr(unsigned char ); void Lcd_Init(void) { unsigned char LCD_2_LINE=0x38; unsigned char LCD_CLEAR=0X01; unsigned char DISPLAY_ON=0X0E; unsigned char LCD_CURSOR_OFF=0x0C; Lcd_Data_Chr(0,0,0,LCD_2_LINE); Lcd_Data_Chr(0,0,0,DISPLAY_ON); Lcd_Data_Chr(0,0,0,LCD_CURSOR_OFF); Lcd_Data_Chr(0,0,0,LCD_CLEAR); } Lcd_Data_Chr(unsigned char RS1 ,unsigned char line,unsigned char position,unsigned char temp1) { unsigned char x;
  83. 83. 74 if(RS1==0) { Set_Port0s= (temp1<<16)&LCD_Data; Lcd_Wr(LCD_C); Clear_Port0s=LCD_Data; } if(RS1==1) { if(line==1) { x=0x7f+position; Set_Port0s= (x<<16)&LCD_Data; Lcd_Wr(LCD_C); Clear_Port0s=LCD_DatA } if(line==2) { x=0xbf+position; Set_Port0s= (x<<16)&LCD_Data; Lcd_Wr(LCD_C); Clear_Port0s=LCD_Data; } Set_Port0s= (temp1<<16)&LCD_Data; Lcd_Wr(LCD_D); Clear_Port0s=LCD_Data; Delay(2); }
  84. 84. 75 } Lcd_Data_Str(unsigned char line1,unsigned char position,unsigned char temp[]) { unsigned int p; unsigned char t; if(line1==1) { p=0x7f+position; Lcd_Data_Chr(0,0,0,(Set_Port0s=(p<<16)&LCD_Data)); } if(line1==2) { p=0xbf+position; Lcd_Data_Chr(0,0,0,(Set_Port0s=(p<<16)&LCD_Data)); } while(temp[t]!='0') { Set_Port0s= (temp[t]<<16)&LCD_Data; Lcd_Wr(LCD_D); t++; Clear_Port0s=LCD_Data; Delay(3); } } Lcd_Wr(unsigned char r) { if(r==1)
  85. 85. 76 { Set_Port0s= RS; Set_Port0s= EN; Delay(1); Clear_Port0s= EN; } if(r==0) { Clear_Port0s= RS; Set_Port0s= EN; Delay(1); Clear_Port0s= EN; } } void Delay(unsigned int time) { unsigned int i,j; for(i=0;i<time;i++) for(j=0;j<25000;j++); } A.2 SOURCE CODE FOR FINGER PRINT MODULE AND GSM #include<LPC2103.H> #include<string.h> #define GPIO_Port0s_IODIR IODIR #define Set_Port0s IOSET
  86. 86. 77 #define Clear_Port0s IOCLR #define Port0_Set IOPIN #define Restg 0 #define Restd 1 #define Enroll (1<<28) #define Identify (1<<29) #define Buzzer (1<<24) #include "LCD.c" #include "Serial_Uart0.c" #include "Serial_Uart1.c" #include "fpm_ky_m8.c" #include "GSM.c" #include "keypad_4x3.c" #include "App.c" int PinStatus_Port(unsigned char ,unsigned int); void Registering_Mobile_NO(void); void Passwd_Break_Message_Sending(void); void Strng_Cmp(void); unsigned char x,key_count; main() { GPIO_Port0s_IODIR= ~(coloums); GPIO_Port0s_IODIR = (LCD_Data|RS|EN|Buzzer|rows); //output=1 // input=0 Clear_Port0s= Buzzer; Lcd_Init(); Init_UART0 (9600); Init_UART1 (9600);
  87. 87. 78 Init_UART0_Interrupt(); FP_Init(); GSM_S900(); Project_Label(); Lcd_Data_Chr(0,0,0,LCD_CLEAR); Lcd_Data_Str(1,1,"1.Tkt Selection "); Lcd_Data_Str(2,1,"2.Tkt Verifying "); while(1) { KeyPad_value=0; KeyPad_value=Keypad_Reading(); while(1) { if(KeyPad_value=='1') // if zero get in is meaning { KeyPad_value=0; Lcd_Data_Chr(0,0,0,LCD_CLEAR); Lcd_Data_Str(2,1,"Ticket Selection"); Lcd_Data_Str(1,1,"You Have Opted "); Delay(500); Selection_Of_Flights(); Lcd_Data_Chr(0,0,0,LCD_CLEAR); Lcd_Data_Str(1,1,"1.Tkt Selection "); Lcd_Data_Str(2,1,"2.Tkt Verifying "); break; } else if(KeyPad_value=='2')

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