Charged pump plls


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  • Charge Pump plls
  • Charge Pump plls
  • Charged pump plls

    1. 1. Presented to :- Ravitesh Mishra04/03/13 Kamlesh Keswani A.P. B.C.E. 1 Mandideep
    2. 2. 04/03/13 Kamlesh Keswani 2
    3. 3. Charge pump pllsThe pll is one of the key building blocks in many communication systems ; providing ameans for maintaining timing integrity and clock synchronization. The Pll can be used invarious applications such as timing extraction from data streams. Jitter mitigation andfrequency synthesisThe CP-PLL derives its name from the fact that the phase detectors (PD) output is acurrent source as opposed to a voltage source and “pumps” current into and out of theloop filter. This form of pll is popular because it is adaptable to integration inmicrocircuit devices. 04/03/13 Kamlesh Keswani 3
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    5. 5. Charge pump pllsThe basic Pll consist of four fundamentalcomponents :•Phase detector, PD• loop filter, z(s)• Voltage controller Oscillator, VCO• Divider, (1/n) The phase detector (PD) compares the inputsignal fi with a reference, or feedback signal fr,to produce an error signal error signal Øe thatis proportional to the phase differencebetween fi and fr. 04/03/13 Kamlesh Keswani 5
    6. 6. The loop-filter extracts the low frequencycontent Øz of the phase error signal Øe, whichis fed to a voltage-controlled oscillator (VCO).The VCO produces an outputfrequency ƒv proportional to the lowfrequency error signal Øz. The outputsignal ƒv is typically divided by a 1/n counterproducing the reference signal ƒr. 04/03/13 Kamlesh Keswani 6
    7. 7. Charge pump pllsThe reference signal fr is fed back tothe phase detector, forming aclosed-loop system. Using negativefeedback, the loop ensures that theinput frequency fiequals thereference frequency ƒr and also thatthe phase of ƒi and ƒr are fixed withrespect to each other. However, theabsolute phase difference betweenƒiand ƒr need not be zero. Note thedivider inside the loop serves as afrequency multiplier04/03/13 Kamlesh Keswani 7
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    9. 9. One implementation of the VCO (Fig. 3.1)suitable for ASIC design consists of a seriesconnected Voltage to Current Converter(V2CC) and a Current ControlledOscillator (CCO).The V2CC takes the control voltage vc andconverts it to a proportional bias current ibias.The bias current is fed to the CCO whichgenerates an output frequency proportionalto the bias current. 04/03/13 Kamlesh Keswani 9
    10. 10. A representative implementation of a V2CC isshown in Fig. 3-2. The operational amplifieradjusts the gate voltage of Q1 such that thecurrent flowing through Q1 is The current mirror consisting of Q2 and Q3 develops the Pbias and Nbias voltages respectively. These bias voltages are used to set the bias current in the CCO. 04/03/13 Kamlesh Keswani 10
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    12. 12. The charge-pump (Fig 3-8) consists of a set ofcurrent sources with magnitudesof IP1 and IP2 amps respectively. In most casesthe current sources are symmetricalthus IP1 = IP2 = IP.One source is connected to thepositive supply rail while the other isconnected to the negative supply rail.The sources are separated by twoswitches S1 andS2. The output of thephase detector provides the gatingsignals U (up) and D(down) whichturn on S1 and S2 respectively. 04/03/13 Kamlesh Keswani 12
    13. 13. The phase detector is designed suchthat switches are never onsimultaneously.When U is high and D islow then S1 is on and S2 is off whichcauses current to flow out of the pumpand into the loop-filter. When U is lowand D is high then Q1 is off and Q2 is onwhich causes current to flow out ofloop-filter and into the pump. 04/03/13 Kamlesh Keswani 13
    14. 14. A representative CMOS charge-pump circuit isshown in Fig. 3-9 and is similar to the outputstage of the current starved inverter (Fig 3-5). The VPBIAS andVNBIAS voltages set thepositive and negative charge-pump currentsrespectively. 04/03/13 Kamlesh Keswani 14
    15. 15. The charge-pump PLL (CP-PLL) is anextension of the basic PLL requiring theaddition of a charge-pump between thephase detector and loop-filter. A specificembodiment (Fig 2-3) uses a three-statephase detector (3PD) which is used forthe analysis going forward. Each of theblocks is discussed in the followingsections.04/03/13 Kamlesh Keswani 15
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    17. 17. In the PLL the phase diffrence between therefrence signal often from a crystaloscillator and the output signal is tranlatedinto two signals- Up and DN.The two signal control switches to steercurrent into or out of the capacitor, causinga voltage across the capacitor to increaseor decrrease.In each cycle the time during which theswitch is turned on is proportional to thephase diffrence, hence the chargedelivered is dependend on the phasediffrence also. 04/03/13 Kamlesh Keswani 17
    18. 18. The voltage on the capacitor is used to tune a voltage control oscillator (VCO) generating a desired output signal frequency. The use of the charge pump naturally adds a pole at the origin in the loop transfer function of PLL, since the charge pump current is driven into capacitor to generate a voltage (V=I/ (sC)).04/03/13 Kamlesh Keswani 18
    19. 19. The additional pole at the origin isdesirable because when consideringthe close loop transfer function of pll ,this pole at the origin integrate theerror signal and cause the system totrack the input with one more order.The charge pump in the pll design isconstructed in integrated circuit ICtechnology, consisting of pull up, pulldown transistors and on chipcapacitors.A resistor is also adder to stablise theclose loop pll04/03/13 Kamlesh Keswani 19
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    21. 21. Phase-locked loops are widely used for synchronization purposes; inspace communications for coherent demodulation and threshold extension, bitsynchronization, and symbol synchronization. Phase-locked loops can also be usedto demodulate frequency-modulated signals. In radio transmitters, a PLL is used tosynthesize new frequencies which are a multiple of a reference frequency, with thesame stability as the reference frequency.Other applications include:*Demodulation of both FM and AM signals*Recovery of small signals that otherwise would be lost in noise (lock-in amplifier)*Recovery of clock timing information from a data stream such as from a disk drive*Clock multipliers in microprocessors that allow internal processor elements to runfaster than external connections, while maintaining precise timing relationshipsDTMF decoders, modems, and other tone decoders, for remotecontrol and telecommunications 04/03/13 Kamlesh Keswani 21
    22. 22. Clock recovery Some data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLLs oscillator. Typically, some sort of redundant encoding is used, such as 8b/10b encoding04/03/13 Kamlesh Keswani 22
    23. 23. Clock generation Many electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of megahertz.04/03/13 Kamlesh Keswani 23
    24. 24. Spread spectrumAll electronic systems emit some unwanted radio frequency energy. Various regulatoryagencies (such as the FCC in the United States) put limits on the emitted energy andany interference caused by it. The emitted noise generally appears at sharp spectralpeaks (usually at the operating frequency of the device, and a few harmonics). Asystem designer can use a spread-spectrum PLL to reduce interference with 04/03/13 Kamlesh Keswani 24
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