VHDL Entity

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VHDL Entity

  1. 1. VHDL ENTITY VHDL 1. ver.8a
  2. 2. In this chapter <ul><li>Learn the basic structure of a VHDL file, especially </li></ul><ul><ul><li>What is an entity? </li></ul></ul><ul><ul><li>What is entity declaration? </li></ul></ul><ul><ul><li>What is an architecture body? </li></ul></ul>VHDL 1. ver.8a
  3. 3. What is an entity? Overall structure of a VHDL file VHDL 1. ver.8a Entity Library declaration Entity declaration Architecture body
  4. 4. What are they? VHDL 1. ver.8a Entity declaration Architecture body A VHDL file Library declaration, e.g. IEEE library Defines Input/Output pins The processing Entity
  5. 5. An example a comparator in VHDL VHDL 1. ver.8a The comparator chip: eqcomp4 a3 a2 a1 a0 equals b3 b2 b1 b0 equals VHDL for programmable logic , Skahill, Addison Wesley A=[a3,a2,a1,a0] B=[b3,b2,b1,b0]
  6. 6. An example of a comparator <ul><li>1 entity eqcomp4 is </li></ul><ul><li>2 port ( a, b : in std_logic_vector( 3 downto 0 ); </li></ul><ul><li>3 equals : out std_logic); </li></ul><ul><li>4 end eqcomp4 ; </li></ul><ul><li>5 </li></ul><ul><li>6 architecture dataflow1 of eqcomp4 is </li></ul><ul><li>7 begin </li></ul><ul><li>8 equals <= ' 1 ' when ( a = b ) else ' 0 ’; </li></ul><ul><li>9-- “comment” equals is active high </li></ul><ul><li>10 end dataflow1 ; </li></ul>VHDL 1. ver.8a Entity declaration: define IOs Architecuture body: functional definition
  7. 7. How to read it <ul><li>1 entity eqcomp4 is </li></ul><ul><li>2 port ( a, b : in std_logic_vector( 3 downto 0 ); </li></ul><ul><li>3 equals : out std_logic); </li></ul><ul><li>4 end eqcomp4 ; </li></ul><ul><li>5 </li></ul><ul><li>6 architecture dataflow1 of eqcomp4 is </li></ul><ul><li>7 begin </li></ul><ul><li>8 equals <= ' 1 ' when ( a = b ) else ' 0 ’; </li></ul><ul><li>9-- “comment” equals is active high </li></ul><ul><li>10 end dataflow1 ; </li></ul>VHDL 1. ver.8a Port defines the I/O pins. Entity enclosed by the entity name – eqcomp4 (entered by the user) <ul><li>Architecture body enclosed by the architecture name dataflow1 </li></ul><ul><li>Std_logic means it is a digital pin. </li></ul><ul><li>A bus, use downto to define it. </li></ul><ul><li>E.g. in std_logic_vector( 3 downto 0 ); </li></ul>
  8. 8. Entity declaration Define Input/Output (IO) pins VHDL 1. ver.8a Entity Library declaration Entity declaration Architecture body
  9. 9. Entity declaration: define the IO pins of the chip <ul><li>entity eqcomp4 is </li></ul><ul><li>port ( a, b: in std_logic_vector( 3 downto 0 ); </li></ul><ul><li>equals: out std_logic); </li></ul><ul><li>end eqcomp4 ; </li></ul>VHDL 1. ver.8a The comparator chip: eqcomp4 a3 a2 a1 a0 equals b3 b2 b1 b0 Two input buses (a3,a2,a1,a0) (b3,b2,b1,b0) and one output ‘equals’
  10. 10. Work example 1.1 <ul><li>1 entity test1 is </li></ul><ul><li>2 port (in1,in2: in bit; </li></ul><ul><li>3 out1: out bit; </li></ul><ul><li>4 end test1; </li></ul><ul><li>5 </li></ul><ul><li>6 architecture test1arch of test1 is </li></ul><ul><li>7 begin </li></ul><ul><li>8 out1<= in1 or in2; </li></ul><ul><li>9 end test1_arch; </li></ul><ul><ul><li>Give line numbers of (i) entity declaration, and (ii) architecture? Also find an error in the code. </li></ul></ul><ul><ul><li>What are the functions of (i) entity declaration and (ii) architecture? </li></ul></ul><ul><ul><li>Draw the chip and names the pins. (Don’t forget the two most important pins) </li></ul></ul><ul><ul><li>Underline the words that are user defined in the above VHDL code. </li></ul></ul>VHDL 1. ver.8a
  11. 11. More on Entity Declaration <ul><li>entity do_care is port( </li></ul><ul><li>s : in std_logic_vector( 1 downto 0 ); </li></ul><ul><li>y : buffer std_logic); </li></ul><ul><li>end do_care ; </li></ul><ul><li>4 types of IO pins </li></ul><ul><ul><li>in, </li></ul></ul><ul><ul><li>out, </li></ul></ul><ul><ul><li>inout (bidirectional) </li></ul></ul><ul><ul><li>buffer (can be read back by the entity) </li></ul></ul>VHDL 1. ver.8a **User defined variables are in Italic.
  12. 12. IN, OUT, INOUT, BUFFER <ul><li>IN: data flows in, like an input pin </li></ul><ul><li>OUT: data flows out, just like an output. The output cannot be read back by the entity </li></ul><ul><li>INOUT: bi-directional, used for data lines of a CPU etc. </li></ul><ul><li>BUFFER: similar to OUT but it can be read back by the entity . Used for control/address pins of a CPU etc. </li></ul>VHDL 1. ver.8a
  13. 13. Worksheet 1.2 Example/Exercise: IN, OUT, INOUT, BUFFER <ul><li>Draw the schematics of the four types </li></ul><ul><li>Based on the following schematic, identify the types of the IO pins. </li></ul>VHDL 1. ver.8a From VHDL for programmable logic , Skahill, Addison Wesley
  14. 14. The architecture body Define the internal architecture/operation VHDL 1. ver.8a Entity Library declaration Entity declaration Architecture body
  15. 15. Architecture body: define the operation of the chip <ul><li>Begin </li></ul><ul><li>… tells you the internal operation….. </li></ul><ul><li>…… .. </li></ul><ul><li>end </li></ul><ul><li>6 architecture dataflow1 of eqcomp4 is </li></ul><ul><li>7 begin </li></ul><ul><li>8 equals <= ' 1 ' when ( a = b ) else ' 0 ’; </li></ul><ul><li>9 -- “comment” equals is active high </li></ul><ul><li>10 end dataflow1 ; </li></ul>VHDL 1. ver.8a Architecuture body
  16. 16. How to read it <ul><li>Architecture name -- dataflow1 (entered by the user) </li></ul><ul><li>equals, a,b are I/O signal pins designed by the user in the entity declaration. </li></ul><ul><li>The operation: equals <= ' 1 ' when ( a = b ) else ' 0 ’; </li></ul><ul><li>“ --” means comment </li></ul>VHDL 1. ver.8a 6 architecture dataflow1 of eqcomp4 is 7 begin 8 equals <= ' 1 ' when ( a = b ) else ' 0 ’; 9-- “comment” equals is active high 10 end dataflow1 ;
  17. 17. Worksheet 1.3: Write the entity of this device <ul><li>Describe the function of the device using plan English/truth table. </li></ul>VHDL 1. ver.8a Worksheet VHDL1.3
  18. 18. Worksheet 1.4: Draw the schematic circuit <ul><li>1 entity test is </li></ul><ul><li>2 port (in1 : in std_logic_vector (2 downto 0); </li></ul><ul><li>3 out1 : out std_logic_vector (3 downto 0)); </li></ul><ul><li>4 end test; </li></ul><ul><li>5 architecture test_arch of test is </li></ul><ul><li>6 begin </li></ul><ul><li>7 out1(0)<=in1(1); </li></ul><ul><li>8 out1(1)<=in1(2); </li></ul><ul><li>9 out1(2)<=in1(0) and in1(1); </li></ul><ul><li>10 out1(3)<=‘1’; </li></ul><ul><li>11 end test_arch ; </li></ul>VHDL 1. ver.8a Worksheet VHDL1.4
  19. 19. Summary <ul><li>Learned entity declaration and architecture body </li></ul>VHDL 1. ver.8a

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