CONVETIONAL CPU• Use hardware to create and dispatch microops that can be executed in parallel leading tomaking them less power efficientX86 INSTRUCTION
ARCHITECTURE OF CRUSOEL1 INSTRUCTIONCACHE64 KbL1 DATA CACHE64KbBUSINTERFACEDDR SDRAMCONTROLLERUNIFIED TLB256 ENTRIESSERIAL ROMINTERFACECPU COREINTEGER UNITFLOATING POINT UNITMMUMULTIMEDIA UNITL2 Web CACHE256 KbPCI CONTROLLERSDR SDRAMCONTROLLER
VLIW Technology The compiler determines which instruction can berun concurrently. The compiler generates grouped independentprimitive instruction executable in parallel.CRUSOE CORE
LONGRUN:POWER MANAGEMENT• Typical Approach 1: Switch off processor quickly tosave power (Can give glitches)• Typical Approach 2: Change clock rate bysuspending processor and restarting• Crusoe 1: Adjust clock rate dynamically, withoutsuspension• Crusoe 2: Adjust voltage level• Result: Cubic power reduction, up to 30%.
BOTH PROCESSORS PLAYING A DVDPIII 105.5 CPIII VS CRUSE HEAT GENERATIONCRUSOE 48.2 C
A revolutionary innovationdies…• Optimization techniques could be tailored to createdifferent target architectures.• Workstation/Server chips were hinted at in thedocumentation.• A whole new family of mobile phone processorsunlike the odds of Nvidia’s Tegra™ and Qualcomm’sSnapdragon™ series