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8b/10b Encoder Decoder design and Verification for PCI Express protocol using cadence tool

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8b/10b Encoder Decoder design and Verification for PCI Express protocol using cadence tool

  1. 1. [1] Presented by Under the guidance of
  2. 2. [2] PCI • Used to attach hardware to a computer. • Introduced by Intel in 1992. PCIE • PCIe, is a high-speed serial computer expansion bus standard designed to replace the older PCI &PCI-X. APPLICATION solid-state drive (SSD) Internet network card
  3. 3. [3] a = A b = B.(L30D)’+L03.D’ c = C+L03.(D’+E) d = D.(L03.D)’ e = E.(L03.D)’+L12.D’.E’+L03.D.E’ i = L21.D’E’+L12.D’.E’+L03.D.E’ f = F.[F.G.H.(S+K)]’ g = G+F’.H’ h = H J = (F≠G).H’+F.G.H.(S+K) Use Common line codes 1.RZ - Return To Zero 2.NRZ - None Return To Zero 3.AMI - Alternate Mark Inversion 4.Manchester Code 5.8B/10B
  4. 4. [4] • Calculation • Enc/Dec Architecture • Xilinx Implementation • CADENCE ASIC Flow • Validation & Evaluation
  5. 5. [5] 5b/6b encoding 3b/4b encoding control Disparity Generation D_FF D_FF D_FF D_FF D_FF xor xor Datain_8b [7:0] Encoder kin rdispin K_error rdispout Dataout_10b [9:0] Decoder 6b/5b decoding 4b/3b decoding control Disparity Generation D_FF D_FF D_FF D_FF Datain_10b [9:0] 6’b 4’b 10’b rdispin rdispout 5’b 3’b K_error Dataout_8b [7:0]
  6. 6. [6] 5b/6b Encoder 3b/4b Encoder Running Disparity 5b sub-block(LSB) (00100) Control data input (D/K) Lets take 8b Hex input = 0X04 Binary Notation = 00000100 8B/10B Notation D 4.0 3b sub-block(MSB) (000) 4b encoded sub-block (0100 or 1011) 6b encoded sub-block (110101 or 001010) CRD Negative 110101 0100 CRD Positive 001010 1011 Concept-
  7. 7. [7] Encoder Decoder
  8. 8. [8] Input of decoderOutput of decoder Input to encoderOutput of encoder Simvision Output
  9. 9. [9] Power(uW) Timing… Area(um²) 0 2000 4000 6000 8000 100 MHz 200 MHz 300 MHz 400 MHz 100 MHz 200 MHz 300 MHz 400 MHz Power(uW) 406.09 770.685 1235.789 1257.176 Timing Slack(ps) 6097 2108 396 1.8 Area(um²) 2591 2498 2435 2302
  10. 10. [10] 0 100 200 300 400 500 N.Kiran (IJRTE) Our Project Power(mW) 452.21 0.40609 Area (x100² µm²) 0 25.91 Frequency (MHz) 0 100 Power(mW) 452.21 .40609 Area (x100² µm²) NA 25.91 Frequency (MHz) NA 100
  11. 11. [11] Computational and Communicational field
  12. 12. [12]
  13. 13. [13] • “Design of Physical Coding Sublayer using 8B/10B Algorithm” N.Kiran Babu, P.S.Srinivas Babu, International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, May 2013 • “8B/10B Encoding And Decoding For High Speed Applications” Alber X.Widmer, IBM Reserch Report RC23408 (W0411-032) November 3,2010. Reference

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