Si4730 31-34-35-d60

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Si4730 31-34-35-d60

  1. 1. Si4730/31/34/35-D60B ROADCAST AM/FM/SW/LW R ADIO R ECEIVERFeatures Worldwide FM band support  Multiplexed stereo audio AUXIN (64–108 MHz) ADC with 85 dB dynamic range Worldwide AM band support  Seven selectable AM channel filters (520–1710 kHz)  AM/FM/SW/LW digital tuning SW band support (Si4734/35)  EN55020 compliant (2.3–26.1 MHz)  No manual alignment necessary LW band support (Si4734/35)  Programmable reference clock (153–279 kHz)  Adjustable soft mute control Excellent real-world performance  RDS/RBDS processor (Si4731/35) Integrated VCO  Digital audio out Advanced AM/FM seek tuning  2-wire and 3-wire control interface Ordering Information: Automatic frequency control (AFC)  Integrated LDO regulator See page 33. Automatic gain control (AGC)  Wide range of ferrite loop sticks and Digital FM stereo decoder air loop antennas supported Pin Assignments Programmable de-emphasis  QFN and SSOP packages Advanced Audio Processing RoHS compliant Si473x-D60 (QFN) GPO3/[DCLK] GPO2/[INT] DFS/[RIN]Applications GPO1 NC Table and portable radios  Modules for consumer electronics NC 1 20 19 18 17 16 FMI 2 15 DOUT/[LIN] Mini/micro systems  Clock radios RFGND 3 14 LOUT/[DFS] GND CD/DVD and Blu-ray players  Mini HiFi and docking stations AMI 4 PAD 13 ROUT/[DOUT] Stereo boom boxes  Entertainment systems RST 5 12 GND 6 7 8 9 10 11 VADescription SEN SCLK RCLK VD SDIOThe Si473x-D60 digital CMOS AM/FM radio receiver IC integrates the complete Si473x-D60(SSOP)tuner function from antenna input to digital audio output and includes a stereo DOUT/[LIN] 1 24 LOUT/[DFS]audio AUXIN ADC input for converting analog audio into standard I2S digital DFS/[RIN] 2 23 ROUT/[DOUT]audio, enabling a cost efficient digital audio platform for consumer electronicapplications with high TDMA noise immunity, superior radio performance, and GPO3/[DCLK] 3 22 DBYPhigh fidelity audio power amplification. When enabling the analog inputs in stereo GPO2/[INT] 4 21 VAAUXIN ADC-mode, the Si473x-D60 supports I2S digital audio output only (no GPO1 5 20 VDanalog output). NC 6 19 RCLK NC 7 18 SDIOFunctional Block Diagram FMI 8 17 SCLK RFGND 9 16 SEN FM / SW AN T R IN Si473x-D60 NC 10 15 RST LIN RD S NC 11 14 GND DO UT FM I (S i4731/ 35) DIG ITA L DFS AMI 12 13 GND LN A AU D IO G PO /D CLK AGC LO W -IF A M / LW A NT AMI M ux AD C DA C RO UT This product, its features, and/or its LN A D SP R FG N D architecture is covered by one or more of M ux AD C DA C LO UT 2.7~5.5 V (Q FN ) AGC the following patents, as well as other 2.0~5.5 V (SSO P) VA CO NTR O L patents, pending and issued, both LD O AFC VD + GND INTER FAC E 1.62 - 3.6 V foreign and domestic: 7,127,217; 7,272,373; 7,272,375; 7,321,324; 7,355,476; 7,426,376; 7,471,940; RCLK SEN SCLK RST SDIO 7,339,503; 7,339,504.Rev. 1.1 11/11 Copyright © 2011 by Silicon Laboratories Si473x-D60
  2. 2. Si4730/31/34/35-D602 Rev. 1.1
  3. 3. Si4730/31/34/35-D60TABLE O F C ONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1. QFN Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2. SSOP Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1. QFN/SSOP Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.7. Stereo Audio AUXIN ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.9. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.10. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.11. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.12. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.13. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.14. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.15. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.16. RDS/RBDS Processor(Si4731/35 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.17. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.18. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.19. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.20. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.21. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.22. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.23. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.24. 2 V Operation (SSOP Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.25. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1. Si473x-D60-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.2. Si473x-D60-GU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1. Si473x-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2. Si473x-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Rev. 1.1 3
  4. 4. Si4730/31/34/35-D60 8.1. Si473x-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.2. Si473x-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 9.1. Si473x-D60 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2. Top Marking Explanation (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3. Si473x-D60 Top Marking (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.4. Top Marking Explanation (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4010. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444 Rev. 1.1
  5. 5. Si4730/31/34/35-D601. Electrical SpecificationsTable 1. Recommended Operating Conditions1 Parameter Symbol Test Condition Min Typ Max UnitAnalog Supply Voltage VA 2.72 — 5.5 VDigital and I/O Supply Voltage VD 1.62 — 3.6 VPower Supply Powerup Rise Time VDDRISE 10 — — µsInterface Power Supply Powerup Rise Time VIORISE 10 — — µsAmbient Temperature TA –20 25 85 CNotes: 1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at VA = 3.3 V and 25 C unless otherwise stated. 2. SSOP devices operate down to 2 V at 25 °C. See section “4.24. 2 V Operation (SSOP Only)” for details. Rev. 1.1 5
  6. 6. Si4730/31/34/35-D60Table 2. DC Characteristics(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max UnitFM ModeVAQFN Supply Current IFMVA — 8.2 9.5VDQFN Supply Current IFMVD — 10.5 13.5 Digital Output Mode1VASSOP Supply Current IFMVA — 18.5 21.5VDSSOP Supply Current IFMVD — 0.15 0.6 mAVAQFN Supply Current IFMVA — 9.1 10.3VDQFN Supply Current IFMVD — 9.9 12.8 Analog Output Mode2VASSOP Supply Current IFMVA — 19.1 21.3VDSSOP Supply Current IFMVD 0.1 0.6AM ModeVAQFN Supply Current IAMVA — 6.5 7.5VDQFN Supply Current IAMVD — 8.5 11.0 Digital Output ModeVASSOP Supply Current IAMVA — 14.5 16.5VDSSOP Supply Current IAMVD — 0.15 0.50 mAVAQFN Supply Current IAMVA — 7.5 8.5VDQFN Supply Current IAMVD — 8 10.2 Analog Output ModeVASSOP Supply Current IAMVA — 15.3 17.2VDSSOP Supply Current IAMVD — 0.1 0.4AUXIN ModeVAQFN Supply Current IAUXVA — 5.7 6.3VDQFN Supply Current IAUXVD — 6.5 8.0 mAVASSOP Supply Current IAUXVA — 0.3 0.4VDSSOP Supply Current IAUXVD — 11.8 13.0PowerdownVAQFN Powerdown Current — 4 15 IAPD µAVASSOP Powerdown Current — 9.5 15VDQFN Powerdown Current SCLK, RCLK inactive — 3 10 IDPD µAVDSSOP Powerdown Current SCLK, RCLK inactive — 3 10High Level Input Voltage3 VIH 0.7 x VD — VD + 0.3 VLow Level Input Voltage3 VIL –0.3 — 0.3 x VD V 3High Level Input Current IIH VIN = VD = 3.6 V –10 — 10 µANotes: 1. Guaranteed by characterization. 2. Backwards compatible mode to rev B and rev C. Additional features on this device may increase typical supply current. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.6 Rev. 1.1
  7. 7. Si4730/31/34/35-D60Table 2. DC Characteristics (Continued)(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit 3Low Level Input Current IIL VIN = 0 V, –10 — 10 µA VD = 3.6 VHigh Level Output Voltage4 VOH IOUT = 500 µA 0.8 x VD — — VLow Level Output Voltage4 VOL IOUT = –500 µA — — 0.2 x VD VNotes: 1. Guaranteed by characterization. 2. Backwards compatible mode to rev B and rev C. Additional features on this device may increase typical supply current. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3. Rev. 1.1 7
  8. 8. Si4730/31/34/35-D60Table 3. Reset Timing Characteristics1,2,3(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)Parameter Symbol Min Typ Max UnitRST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 — — µsGPO1, GPO2/INT Hold from RST tHRST 30 — — nsImportant Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. 4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and GPO2 low. tSRST tHRST 70% RST 30% 70% GPO1 30% GPO2/ 70% INT 30% Figure 1. Reset Timing Parameters for Busmode Select8 Rev. 1.1
  9. 9. Si4730/31/34/35-D60Table 4. 2-Wire Control Interface Characteristics1,2,3(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitSCLK Frequency fSCL 0 — 400 kHzSCLK Low Time tLOW 1.3 — — µsSCLK High Time tHIGH 0.6 — — µsSCLK Input to SDIO  Setup tSU:STA 0.6 — — µs(START)SCLK Input to SDIO  Hold tHD:STA 0.6 — — µs(START)SDIO Input to SCLK  Setup tSU:DAT 100 — — nsSDIO Input to SCLK  Hold4,5 tHD:DAT 0 — 900 nsSCLK input to SDIO  Setup tSU:STO 0.6 — — µs(STOP)STOP to START Time tBUF 1.3 — — µsSDIO Output Fall Time tf:OUT — 250 ns Cb 20 + 0.1 ---------- - 1pFSDIO Input, SCLK Rise/Fall Time tf:IN — 300 ns tr:IN Cb 20 + 0.1 ---------- - 1pFSCLK, SDIO Capacitive Loading Cb — — 50 pFInput Filter Pulse Suppression tSP — — 50 nsNotes: 1. When VD = 0 V, SCLK and SDIO are low impedance. 2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si473x-D60 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum tHD:DAT specification. 5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be violated as long as all other timing parameters are met. Rev. 1.1 9
  10. 10. Si4730/31/34/35-D60 tSU:STA tHD:STA tLOW tHIGH tr:IN tf:IN tSP tSU:STO tBUF 70% SCLK 30% 70% SDIO 30% START tHD:DAT tSU:DAT tf:IN, tr:IN STOP START tf:OUT Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO D7-D0 D7-D0 R/W START ADDRESS + R/W ACK DATA ACK DATA ACK STOP Figure 3. 2-Wire Control Interface Read and Write Timing Diagram10 Rev. 1.1
  11. 11. Si4730/31/34/35-D60Table 5. 3-Wire Control Interface Characteristics(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitSCLK Frequency fCLK 0 — 2.5 MHzSCLK High Time tHIGH 25 — — nsSCLK Low Time tLOW 25 — — nsSDIO Input, SEN to SCLKSetup tS 20 — — nsSDIO Input to SCLKHold tHSDIO 10 — — nsSEN Input to SCLKHold tHSEN 10 — — nsSCLKto SDIO Output Valid tCDV Read 2 — 25 nsSCLKto SDIO Output High Z tCDZ Read 2 — 25 nsSCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 nsNote: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. 70% SCLK 30% tR tF tS tHSDIO tHIGH tLOW tHSEN 70% SEN tS 30% 70% A6-A5, SDIO A7 R/W, A0 D15 D14-D1 D0 30% A4-A1 Address In Data In Figure 4. 3-Wire Control Interface Write Timing Parameters 70% SCLK 30% tS tHSDIO tCDV tHSEN tCDZ 70% SEN tS 30% 70% A6-A5, SDIO A7 R/W, A0 D15 D14-D1 D0 30% A4-A1 Address In ½ Cycle Bus Data Out Turnaround Figure 5. 3-Wire Control Interface Read Timing Parameters Rev. 1.1 11
  12. 12. Si4730/31/34/35-D60Table 6. Digital Audio Interface Characteristics(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max UnitDCLK Cycle Time tDCT 26 — 1000 nsDCLK Pulse Width High tDCH 10 — — nsDCLK Pulse Width Low tDCL 10 — — nsDFS Set-up Time to DCLK Rising Edge tSU:DFS 5 — — nsDFS Hold Time from DCLK Rising Edge tHD:DFS 5 — — nsDOUT Propagation Delay from DCLK Falling tPD:DOUT 0 — 50 nsEdge tDCH tDCL DCLK tDCT DFS tHD:DFS tSU:DFS DOUT tPD:OUT Figure 6. Digital Audio Interface Timing Parameters, I2S Mode12 Rev. 1.1
  13. 13. Si4730/31/34/35-D60Table 7. FM Receiver Characteristics1,2(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitInput Frequency fRF 76 — 108 MHzSensitivity3,4,5,6 (S+N)/N = 26 dB — 2.2 3.5 µV EMFRDS Sensitivity6,7 f = 2 kHz, — 10 — µV EMF RDS BLER < 5%LNA Input Resistance7,8 3 4 5 k 7,8LNA Input Capacitance 4 5 6 pFInput IP37,9 100 105 — dBµV EMFAM Suppression3,4,7,8 m = 0.3 40 50 — dBAdjacent Channel Selectivity ±200 kHz 35 50 — dBAlternate Channel Selectivity ±400 kHz 60 70 — dBSpurious Response Rejection7 In-band 35 — — dB 3,4,8 72 80 90 mVRMSAudio Output Voltage 3,8,10 — — 1 dBAudio Output L/R ImbalanceAudio Frequency Response Low7 –3 dB — — 30 HzAudio Frequency Response High7 –3 dB 15 — — kHz 8,10 35 42 — dBAudio Stereo SeparationAudio Mono S/N3,4,5,8 55 63 — dBAudio Stereo S/N4,5,7,8 — 58 — dBAudio THD3,8,10 — 0.1 0.5 % 7De-emphasis Time Constant FM_DEEMPHASIS = 2 70 75 80 µs FM_DEEMPHASIS = 1 45 50 54 µs 3,4,5,6,7,11, 12Blocking Sensitivity f = ±400 kHz — 34 — dBµV f = ±4 MHz — 30 — dBµVNotes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Analog audio output mode. 7. Guaranteed by characterization. 8. VEMF = 1 mV. 9. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 10. f = 75 kHz. 11. Sensitivity measured at (S+N)/N = 26 dB. 12. Blocker Amplitude = 100 dBuV. 13. At temperature (25 °C). 14. At LOUT and ROUT pins. Rev. 1.1 13
  14. 14. Si4730/31/34/35-D60Table 7. FM Receiver Characteristics1,2 (Continued)(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitIntermod Sensitivity3,4,5,6,7,11,12 f = ±400 kHz, ±800 kHz — 40 — dBµV f = ±4 MHz, ±8 MHz — 35 — dBµVAudio Output Load Resistance7,11,14 RL Single-ended 10 — — kAudio Output Load CL Single-ended — — 50 pFCapacitance7,11,14Seek/Tune Time7 RCLK tolerance — — 60 ms/channel = 100 ppmPowerup Time7 From powerdown — — 110 msRSSI Offset12,13 Input levels of 8 and –3 — 3 dB 60 dBµV at RF InputNotes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Analog audio output mode. 7. Guaranteed by characterization. 8. VEMF = 1 mV. 9. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 10. f = 75 kHz. 11. Sensitivity measured at (S+N)/N = 26 dB. 12. Blocker Amplitude = 100 dBuV. 13. At temperature (25 °C). 14. At LOUT and ROUT pins.14 Rev. 1.1
  15. 15. Si4730/31/34/35-D60Table 8. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,3(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)Parameter Symbol Test Condition Min Typ Max UnitInput Frequency fRF 64 — 75.9 MHzSensitivity4,5,6,8 (S+N)/N = 26 dB — 3.5 — µV EMFLNA Input Resistance3,7 3 4 5 k 3,7LNA Input Capacitance 4 5 6 pF 9Input IP3 — 105 — dBµV EMFAM Suppression3,4,5,7 m = 0.3 — 50 — dBAdjacent Channel Selectivity ±200 kHz — 50 — dBAlternate Channel Selectivity ±400 kHz — 70 — dBAudio Output Voltage4,5,7 72 80 90 mVRMSAudio Output L/R Imbalance4,7,10 — — 1 dB 3 –3 dB — — 30 HzAudio Frequency Response Low 3 –3 dB 15 — — kHzAudio Frequency Response HighAudio Mono S/N4,3,5,7,11 — 63 — dBAudio THD4,7,10 — 0.1 — %De-emphasis Time Constant FM_DEEMPHASIS = 2 70 75 80 µs FM_DEEMPHASIS = 1 45 50 54 µsAudio Output Load Resistance3,11 RL Single-ended 10 — — kAudio Output Load Capacitance3,11 CL Single-ended — — 50 pF 3Seek/Tune Time RCLK tolerance — — 60 ms/channel = 100 ppmPowerup Time3 From powerdown — — 110 ms 12RSSI Offset Input levels of 8 and –3 — 3 dB 60 dBµV EMFNotes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. Guaranteed by characterization. 4. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 5. f = 22.5 kHz. 6. BAF = 300 Hz to 15 kHz, A-weighted. 7. VEMF = 1 mV. 8. Analog output mode. 9. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 10. f = 75 kHz. 11. At LOUT and ROUT pins. 12. At temperature (25 °C). Rev. 1.1 15
  16. 16. Si4730/31/34/35-D60Table 9. AM/SW/LW Receiver Characteristics1,2(VA = 2.7 to 5.5 V, VA = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max UnitInput Frequency fRF Long Wave (LW) 153 — 279 kHz Medium Wave (AM) 520 — 1710 kHz Short Wave (SW) 2.3 — 26.1 MHz 3,4,5Sensitivity (S+N)/N = 26 dB — 25 35 µV EMFLarge Signal Voltage Handling5,6 THD < 8% — 300 — mVRMS 5Power Supply Rejection Ratio ∆VDD = 100 mVRMS, 100 Hz — 40 — dBAudio Output Voltage3,7 54 60 67 mVRMS 3,4,7Audio S/N — 60 — dBAudio THD3,7 — 0.1 0.5 % 5,8Antenna Inductance Long Wave (LW) — 2800 — µH Medium Wave (AM) 180 — 450 µH 5Powerup Time From powerdown — — 110 msNotes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” Volume = maximum for all tests. Tested at RF = 520 kHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 30% modulation, 2 kHz channel filter. 4. BAF = 300 Hz to 15 kHz, A-weighted. 5. Guaranteed by characterization. 6. See “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure” for evaluation method. 7. VIN = 5 mVrms. 8. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.16 Rev. 1.1
  17. 17. Si4730/31/34/35-D60Table 10. AC Receiver Characteristics—AUXIN Analog to Digital Converter(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max UnitTotal Harmonic Distortion + THD+N f = 1 kHz; — 0.035 0.06 %Noise measured 20 Hz—20 kHzDynamic Range/Signal to Noise SNR f = 1 kHz at –60 dBFS — 85 — dBRatio A-weighted f = 1 kHz at –60 dBFS — 78 — dB non-weightedCrosstalk f = 1 kHz with 3% Bandpass — 90 — dB filterGain Mismatch — 0.03 — dBGain Drift — 100 — PPM/°CInput Sample Rate FS — 48 — kHzInput Voltage VAI — — 1.8 VpkpkInput Resistance RAI LIATTEN[1:0] — 60 — kInput Capacitance CAI — 10 — pFTable 11. Digital Filter Characteristics—AUXIN Analog to Digital Converter(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max UnitPassband Frequency Response –0.1 dB 0.02 — 20 kHzPassband Ripple 20—20 kHz –0.1 — 0.1 dBStopband Corner Frequency 25 — — kHzStopband Attenuation 70 — — dB Rev. 1.1 17
  18. 18. Si4730/31/34/35-D60Table 12. Reference Clock and Crystal Characteristics(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Reference ClockRCLK Supported Frequencies1 31.130 32.768 40,000 kHz 2RCLK Frequency Tolerance –100 — 100 ppmREFCLK_PRESCALE 1 — 4095REFCLK 31.130 32.768 34.406 kHz Crystal OscillatorCrystal Oscillator Frequency — 32.768 — kHzCrystal Frequency Tolerance2 –100 — 100 ppmBoard Capacitance — — 3.5 pFESR — — 50 CL3 7 12 22 pFCL–single ended3 14 24 44 pFNotes: 1. The Si473x-D60 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx Programming Guide”. 2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing and AM seek/tune in SW frequencies. 3. Guaranteed by characterization.Table 13. Thermal Conditions Parameter Symbol Min Typ Max UnitThermal Resistance* JA — 80 — °C/WAmbient Temperature TA –15 25 85 °CJunction Temperature TJ — — 92 °C*Note: Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.18 Rev. 1.1
  19. 19. Si4730/31/34/35-D60Table 14. Absolute Maximum Ratings1,2 Parameter Symbol Value UnitAnalog Supply Voltage VA –0.5 to 5.8 VDigital and I/O Supply Voltage VD –0.5 to 3.9 VInput Current3 IIN 10 mA 3Input Voltage VIN –0.3 to (VIO + 0.3) VOperating Temperature TOP –40 to 95 CStorage Temperature TSTG –55 to 150 CRF Input Level4 0.4 VpkNotes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si473x-D60 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. 3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK. 4. At RF input pins FMI and AMI. Rev. 1.1 19
  20. 20. Si4730/31/34/35-D602. Typical Application Schematic2.1. QFN Typical Application Schematic Optional: Digital Audio Out 16 C7 DFS RIN OPMODE: 0xB0, 0xB5 15 C8 DOUT LIN 17 R3 GP03/DCLK DCLK R2 C9 14 GPO1 LOUT DFS 13 R1 GPO2/INT ROUT DOUT R3 GPO3/DCLK Si473x R2 DFS C9 Optional: AUXIN/Digital Audio Out R1 20 19 18 17 16 DOUT OPMODE: 0x5B, 0x0B NC GPO1 GPO2/INT GPO3/DCLK DFS 1 NC 15 DOUT FM Antenna C2 2 14 FMI LOUT LOUT 3 13 RFGND ROUT L1 4 Si473x 12 ROUT AMI D60 GND C3 5 11 2.7 to 5.5 V RSTB VA VA C1 SENB RCLK SCLK SDIO VD 10 6 7 8 9 1.62 to 3.6 V VD RSTB C4 RCLK SDIO SCLK SENB Optional: AM Air Loop Antenna L2 2 1 GPO3 RCLK T1 1 C3 X1 AMI C5 C6 3 RFGND Optional: For Crystal OSCNotes: 1. Place C1 close to VA pin and C4 close to VD pin. 2. All grounds connect directly to GND plane on PCB. 3. Pins 1 and 20 are no connects, leave floating. 4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface. 6. Place Si473x-D60 as close as possible to antenna and keep the FMI and AMI traces as short as possible.20 Rev. 1.1
  21. 21. Si4730/31/34/35-D602.2. SSOP Typical Application Schematic 2 C7 DFS RIN 1 C8 DOUT LIN 3 R3 GP03/DCLK DCLK 24 R2 LOUT DFS 23 R1 Optional: Digital Audio Out ROUT DOUT OPMODE: 0xB0, 0xB5 Si473x C9 C9 Optional: AUXIN/Digital Audio Out OPMODE: 0x5B, 0x0B R1 1 24 DOUT DOUT LOUT LOUT R2 2 23 DFS DFS ROUT ROUT R3 3 22 GPO3/DCLK GPO3/DCLK DBYP 4 GPO2/INT D60 VA 21 C1 GPO2/INT 2.0 to 5.5 V 5 20 VA 1.62 to 3.6 V GPO1 GPO1 VD VD 6 NC 19 RCLK RCLK C4 Si473x 7 NC 18 SDIO SDIO FM Antenna C2 8 17 FMI SCLK SCLK 9 16 RFGND SENB SENB 10 NC 15 RSTB RSTB L1 11 NC GND 14 C3 12 GND 13 AMI Optional: AM Air Loop Antenna L2 2 1 GPO3 RCLK T1 1 C3 X1 AMI C5 C6 3 RFGND Optional: For Crystal OSCNotes: 1. Place C1 close to VA and C4 close to VD pin. 2. All grounds connect directly to GND plane on PCB. 3. Pins 6 and 7 are no connects, leave floating. 4. Pins 10 and 11 are unused. Tie these pins to GND. 5. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 6. Pin 8 connects to the FM antenna interface, and pin 12 connects to the AM antenna interface. 7. Place Si473x-D60 as close as possible to antenna and keep the FMI and AMI traces as short as possible. Rev. 1.1 21
  22. 22. Si4730/31/34/35-D603. Bill of Materials3.1. QFN/SSOP Bill of Materials Table 15. Si473x-D60 QFN/SSOP Bill of Materials Component(s) Value/Description Supplier C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata C2 Coupling capacitor, 1 nF, ±20%, Z5U/X7R Murata C3 Coupling capacitor, 0.47 μF, ±20%, Z5U/X7R Murata C4 Supply bypass capacitor, 100 nF, 10%, Z5U/X7R Murata L1 Ferrite loop stick, 180–450 μH Jiaxin U1 Si47xx AM/FM Radio Tuner Silicon Laboratories Optional Components C5, C6 Crystal load capacitors, 22 pF, ±5%, COG Venkel (Optional for crystal oscillator) C7 Coupling capacitor, 0.39 μF, ±20%, Z5U/X7R Murata (Optional for AUXIN) C8 Coupling capacitor, 0.39 μF, ±20%, Z5U/X7R Murata (Optional for AUXIN) C9 Noise mitigating capacitor, 2~5 pF Murata (Optional for digital audio) R1 Resistor, 600 Ω Venkel (Optional for digital audio) R2 Resistor, 2 kΩ Venkel (Optional for digital audio) R3 Resistor, 2 kΩ Venkel (Optional for digital audio) L2 Air Loop, 10-20 µH Jiaxin (Optional for AM Input) T1 Transformer, 1:5 turns ratio Jiaxin, UMEC (Optional for AM Input) X1 32.768 kHz crystal Epson (Optional for crystal oscillator)22 Rev. 1.1
  23. 23. Si4730/31/34/35-D604. Functional Description4.1. Overview FM / SW ANT RIN LIN Si473x-D60 RDS DOUT FMI (Si4731/ DIGITAL LNA 35) DFS AUDIO GPO/DCLK AGC LOW-IF AM / LW AMI Mux ADC DAC ROUT ANT LNA DSP RFGND Mux ADC DAC LOUT AGC 2.7~5.5 V VA CONTROL LDO AFC VD GND INTERFACE 1.62~3.6 V RST RCLK SEN SCLK SDIO Figure 7. Functional Block DiagramThe Si473x-D60 CMOS AM/FM radio receiver IC audio processing.integrates the complete tuner function from antenna In addition, the Si473x-D60 provides analog and digitalinput to audio output, including a stereo audio AUXIN audio outputs and a programmable reference clock. TheADC input for converting analog audio to digital signals. device supports I2C-compatible 2-wire control interface,This feature enables a cost-efficient digital audio and a Si4700/01 backwards-compatible 3-wire controlplatform for consumer electronics applications with high interface.cell phone noise immunity, superior radio performance, The Si473x-D60 utilizes digital signal processing toand high fidelity audio power amplification. Offering achieve high fidelity, optimal performance, and designunmatched integration and PCB space savings, the flexibility. The chip provides excellent pilot rejection,Si473x-D60 requires only a few external components selectivity, and unmatched audio performance, andand less than 15 mm2 of board area, excluding the offers both the manufacturer and the end-userantenna inputs. The Si473x-D60 AM/FM radio provides extensive programmability and a better listeningthe space savings and low power consumption experience.necessary for portable devices while delivering the highperformance and design simplicity desired for all The Si4731/35 incorporates a digital signal processorAM/FM solutions. for the European Radio Data System (RDS) and the North American Radio Broadcast Data System (RBDS)Leveraging Silicon Laboratories proven and patented including all required symbol decoding, blockSi4700/01 FM tuners digital low intermediate frequency synchronization, error detection, and error correction(low-IF) receiver architecture, the Si473x-D60 delivers functions. Using this feature, the Si4731/35 enablessuperior RF performance and interference rejection in broadcast data such as station identification and songthe AM, FM, SW, and LW bands. The high level of name to be displayed to the user.integration and complete system production testsimplifies design-in, increases system quality, andimproves reliability and manufacturability.The Si473x-D60 is a feature-rich solution that includesadvanced seek algorithms, soft mute, auto-calibrateddigital tuning, FM stereo processing and advanced Rev. 1.1 23
  24. 24. Si4730/31/34/35-D604.2. Operating Modes optimize sensitivity and rejection of strong interferers allowing better reception of weak stations.The Si473x-D60 operates in either an FM receive, AMreceive, or audio AUXIN ADC mode. In FM mode, radio The Si473x-D60 provides highly-accurate digital AMsignals are received on FMI and processed by the FM tuning without factory adjustments. To offer maximumfront-end circuitry. In AM mode, radio signals are flexibility, the receiver supports a wide range of ferritereceived on AMI and processed by the AM front-end loop sticks from 180–450 µH. An air loop antenna iscircuitry. In audio AUXIN ADC mode, stereo audio supported by using a transformer to increase thesignals on LIN/RIN are sampled, converted to digital, effective inductance from the air loop. Using a 1:5 turnfiltered, and decimated to 32, 44.1, or 48 kHz for the I2S ratio inductor, the inductance is increased by 25 timesdigital audio interface. In addition to the receiver mode, and easily supports all typical AM air loop antennasthere is a clocking mode to choose to clock the Si473x- which generally vary between 10 and 20 µH.D60 from a reference clock or crystal. On the Si473x- 4.5. SW ReceiverD60, there is an audio output mode to choose betweenan analog and/or digital audio output. In the analog The Si4734/35 is the first fully integrated IC to supportaudio output mode, ROUT and LOUT are used for the AM and FM, as well as short wave (SW) band receptionaudio output pins. In the digital audio mode, DOUT, from 2.3 to 26.1 MHz fully covering the 120 meter toDFS, and DCLK pins are used. Concurrent 11 meter bands. The Si4734/35 offers extensiveanalog/digital audio output mode is also available shortwave features such as continuous digital tuningrequiring all five pins. with minimal discrete components and no factory adjustments. Other SW features include adjustable4.3. FM Receiver channel step sizes in 1 kHz increments, adjustableThe Si473x-D60 FM receiver is based on the proven channel bandwidth settings, advanced seek algorithm,Si4700/01 FM tuner. The receiver uses a digital low-IF and soft mute.architecture allowing the elimination of external The Si4734/35 uses the FM antenna to capture shortcomponents and factory adjustments. The Si473x-D60 wave signals. These signals are then fed directly intointegrates a low noise amplifier (LNA) supporting the the AMI pin in a wide band configuration. See "AN332:worldwide FM broadcast band (64 to 108 MHz). An Si47xx Programming Guide” and “AN383: Si47xxAGC circuit controls the gain of the LNA to optimize Antenna and Schematic Guidelines" for more details.sensitivity and rejection of strong interferers. An image-reject mixer downconverts the RF signal to low-IF. The 4.6. LW Receiverquadrature mixer output is amplified, filtered, and The Si4734/35 supports the long wave (LW) band fromdigitized with high resolution analog-to-digital 153 to 279 kHz. The highly integrated Si4734/35 offersconverters (ADCs). This advanced architecture allows continuous digital tuning with minimal discretethe Si473x-D60 to perform channel selection, FM components and no factory adjustments. The Si4734/35demodulation, and stereo audio processing to achieve also offers adjustable channel step sizes in 1 kHzsuperior performance compared to traditional analog increments, adjustable channel bandwidth settings,architectures. advanced seek algorithm, and soft mute.4.4. AM Receiver The Si4734/35 uses a separate ferrite bar antenna to capture long wave signals.The highly-integrated Si473x-D60 supports worldwideAM band reception from 520 to 1710 kHz using a digital 4.7. Stereo Audio AUXIN ADClow-IF architecture with a minimum number of external The Si473x-D60 stereo audio AUXIN ADC can becomponents and no manual alignment required. This multiplexed between low-IF input for radio operationdigital low-IF architecture allows for high-precision and analog audio input for high fidelity data conversionfiltering offering excellent selectivity and SNR with at 32, 44.1, or 48 kHz sample rate. When operated inminimum variation across the AM band. The DSP also ADC-mode, the Si473x-D60 supports I2S digital audioprovides adjustable channel step sizes in 1 kHz output only (no analog output) while enabling the analogincrements, AM demodulation, soft mute, seven inputs and the stereo ADC.different channel bandwidth filters, and additionalfeatures, such as a programmable automatic volumecontrol (AVC) maximum gain allowing users to adjustthe level of background noise.Similar to the FM receiver, the integrated LNA and AGC24 Rev. 1.1
  25. 25. Si4730/31/34/35-D604.8. Digital Audio InterfaceThe digital audio interface operates in slave mode andsupports a variety of MSB-first audio data formatsincluding I2S and left-justified modes. The interface hasthree pins: digital data input (DIN), digital framesynchronization input (DFS), and a digital bitsynchronization input clock (DCLK). The Si473x-D60supports a number of industry-standard sampling ratesincluding 32, 44.1, and 48 kHz. The digital audiointerface enables low-power operation by eliminatingthe need for redundant DACs and ADCs on the audiobaseband processor.4.8.1. Audio Data FormatsThe digital audio interface operates in slave mode andsupports three different audio data formats: I2S Left-Justified DSP ModeIn I2S mode, by default the MSB is captured on thesecond rising edge of DCLK following each DFStransition. The remaining bits of the word are sent inorder, down to the LSB. The left channel is transferredfirst when the DFS is low, and the right channel istransferred when the DFS is high.In left-justified mode, by default the MSB is captured onthe first rising edge of DCLK following each DFStransition. The remaining bits of the word are sent inorder, down to the LSB. The left channel is transferredfirst when the DFS is high, and the right channel istransferred when the DFS is low.In DSP mode, the DFS becomes a pulse with a width of1DCLK period. The left channel is transferred first,followed right away by the right channel. There are twooptions in transferring the digital audio data in DSPmode: the MSB of the left channel can be transferred onthe first rising edge of DCLK following the DFS pulse oron the second rising edge.In all audio formats, depending on the word size, DCLKfrequency, and sample rates, there may be unusedDCLK cycles after the LSB of each word before the nextDFS transition and MSB of the next word. In addition, ifpreferred, the user can configure the MSB to becaptured on the falling edge of DCLK via properties.The number of audio bits can be configured for 8, 16,20, or 24 bits.4.8.2. Audio Sample RatesThe device supports a number of industry-standardsampling rates including 32, 44.1, and 48 kHz. Thedigital audio interface enables low-power operation byeliminating the need for redundant DACs on the audiobaseband processor. Rev. 1.1 25
  26. 26. Si4730/31/34/35-D60 (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK DFS LEFT CHANNEL RIGHT CHANNEL I2S (OMODE = 0000) 1 DCLK 1 DCLK DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB LSB MSB LSB Figure 8. I2S Digital Audio Format (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK DFS LEFT CHANNEL RIGHT CHANNEL Left-Justified (OMODE = 0110) DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n MSB LSB MSB LSB Figure 9. Left-Justified Digital Audio Format (OFALL = 0) DCLK DFS LEFT CHANNEL RIGHT CHANNEL(OMODE = 1100) DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n st (MSB at 1 rising edge) MSB LSB MSB LSB 1 DCLK LEFT CHANNEL RIGHT CHANNEL DOUT nd 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n(OMODE = 1000) (MSB at 2 rising edge) MSB LSB MSB LSB Figure 10. DSP Digital Audio Format26 Rev. 1.1

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