library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;USE ieee.numeric_std...
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Ram sourcecode&testbench

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Ram sourcecode&testbench

  1. 1. library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;entity ram isport (address: in std_logic_vector(7 downto 0); data: inout std_logic_vector(7 downto 0); WE, CS, OE: in std_logic);end entity ram;architecture simple_ram of ram istype ram_type is array (0 to 255) of std_logic_vector(7 downto 0);signal ram1: ram_type:= (others => (others => 0));beginprocess(WE,CS,OE,address)begindata <= (others => Z);if (CS = 0) then if WE=1 and OE = 1 then ram1(conv_integer(address)) <= data; end if; if WE = 0 and OE = 0 and CS = 0 then data <= ram1(conv_integer(address)); END IF; else data <= (others => Z);-- end if;end if;end process;end simple_ram;

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