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Fut Lsi


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Fut Lsi

  1. 1.
  2. 2. Index <ul><li>LSI-Patni Relationship </li></ul><ul><li>Software Test life cycle </li></ul><ul><li>Project Details </li></ul><ul><li>Standard Used </li></ul><ul><li>Testing Tools </li></ul><ul><li>Metrics </li></ul><ul><li>Quality </li></ul><ul><li>Achievements </li></ul><ul><li>Patni’s Contribution </li></ul>
  3. 3. LSI - Patni Relationship
  4. 4. LSI-Patni Relationship <ul><li>Patni’ has been working with LSI to supporting in following areas : </li></ul><ul><ul><li>Understanding of the overall architecture </li></ul></ul><ul><ul><li>Design and Development of different Tools. </li></ul></ul><ul><ul><li>Developing and Testing Firmware </li></ul></ul><ul><ul><li>Enhancements for existing Tools </li></ul></ul><ul><ul><li>Migration work </li></ul></ul><ul><ul><li>Setting up the offshore development environment. </li></ul></ul>LSI is a leading global provider of innovative silicon, systems and software technologies that enable products which seamlessly bring people, information and digital content together. Including Custom and standard product ICs, adapters, systems and software that are trusted by the world's best known brands to power leading solutions in the Storage and Networking markets.
  5. 5. Software Test Life Cycle <ul><li>Requirement Phase </li></ul><ul><li>Testing Phase </li></ul><ul><li>Defect Validation Phase </li></ul><ul><li>Delivery Phase </li></ul>Project Prerequisites Resources Test Environment Documents Tools
  6. 6. Requirement Phase <ul><li>To Gather Test Requirement from Client </li></ul><ul><li>Study client requirement </li></ul><ul><li>Prepare project plan & Time Estimation </li></ul><ul><li>Approve Test plan from Client </li></ul>
  7. 7. Testing Phase <ul><li>Upload latest firmware from configuration tool (Clear Case) </li></ul><ul><li>Create and execute test script </li></ul><ul><li>Debug firmware if required </li></ul><ul><li>Analyze actual result with expected result </li></ul><ul><li>Update defect in configuration tool (Clear Quest ) </li></ul>
  8. 8. Defect Validation Phase <ul><li>Validate defect resolved by developer </li></ul><ul><li>Reject defect if persist after resolved </li></ul><ul><li>Communicate with developer for more information </li></ul><ul><li>Closed Validated defects in Clear Quest. </li></ul>
  9. 9. Delivery Phase <ul><li>Deliver test script in Clear Case </li></ul><ul><li>Deliver test result to client </li></ul><ul><li>Conduct project review meeting </li></ul>
  10. 10. Project Details <ul><li>SATA Command testing </li></ul><ul><li>MPI-2 Interface Testing </li></ul><ul><li>ATA Passthrough Testing </li></ul><ul><li>StoreLib IR Testing </li></ul><ul><li>Integrated RAID 1E ASM Testing </li></ul><ul><li>SimDiscovery Tool Testing </li></ul>
  11. 11. Test Setup Server HBA HDD 1 HDD 2 HDD 3 HDD 4 JBOD-1 HDD 1 HDD 2 HDD 3 HDD 4 JBOD-2 Debugger Desktop
  12. 12. SATA Command Testing <ul><li>Requirement: </li></ul><ul><li> Firmware Unit testing of SCSI Primary commands (SPC) and SCSI Block commands (SBC) on SATA device </li></ul><ul><li>Project Highlight: </li></ul><ul><li> 1105 python script created and tested as a part of SATA commands testing. </li></ul><ul><li> User command for CM or command descriptor block (CDB) created to test 32 command set. </li></ul><ul><li> Efforts spent on SPC and SBC specification documents to get exact behavior of SATA commands. </li></ul><ul><li> Existing user commands and python scripts can be reused to test functionality of SATA commands. </li></ul><ul><li> Debug the firmware to find exact location of introduction of bug. </li></ul><ul><li> Communication with firmware development team to reproduce the detected bug. </li></ul><ul><li> Tested 1000+ python script as a part of SATA command regression testing. </li></ul><ul><li> Total 12 number of bugs reported. </li></ul><ul><li> 100 % coverage to SATA command testing. </li></ul><ul><li> Only 3 Resources involved in SATA command testing. </li></ul>
  13. 13. MPI-2 Testing <ul><li>Requirement: </li></ul><ul><li>To test functionality of Message Passing interface ( MPI-2) specification </li></ul><ul><li>Project Highlight: </li></ul><ul><li>Total 512 perl script created and tested as a part of MPI-2 testing </li></ul><ul><li>Total 14 bugs reported for MPI-2 testing </li></ul><ul><li>Only 3 –resources involved for testing </li></ul><ul><li>100 % coverage to MPI2- Specification </li></ul><ul><li>Project completed and delivered on schedule </li></ul>
  14. 14. ATA Passthrough Testing <ul><li>Requirement: </li></ul><ul><li>To test ATA Passthrough commands on SATA drive. </li></ul><ul><li>Project Highlight: </li></ul><ul><li>Total 22 ATA Passthrough commands consider for testing from following protocol group </li></ul><ul><ul><ul><ul><li>Non data transfer commands </li></ul></ul></ul></ul><ul><ul><ul><ul><li>PIO data in commands </li></ul></ul></ul></ul><ul><ul><ul><ul><li>PIO Data out commands </li></ul></ul></ul></ul><ul><ul><ul><ul><li>DMA Data in Commands </li></ul></ul></ul></ul><ul><ul><ul><ul><li>DMA Data out commands </li></ul></ul></ul></ul><ul><li>Total 400+ python script are expected in ATA Passthrough testing </li></ul><ul><li>10+ defects expected in ATA Passthrough testing </li></ul><ul><li>100 % ATA Passthrough specification coverage </li></ul><ul><li>Expected 0% schedule variance </li></ul>
  15. 15. StoreLib IR testing <ul><li>Requirement: </li></ul><ul><li> To test StoreLibIR-2 Library provided by LSI ESG group </li></ul><ul><li>Project Highlight: </li></ul><ul><li>Testing of StoreLibIr-2 executed in two phases </li></ul><ul><ul><li>StoreLibIR-2 Phase 1: </li></ul></ul><ul><ul><ul><li>Created manual test case to covered all normal and abnormal scenarios. </li></ul></ul></ul><ul><ul><ul><li>Time constraint- As per schedule testing completed in 16 days </li></ul></ul></ul><ul><ul><li>StoreLibIR-2 Phase 2 : </li></ul></ul><ul><ul><ul><li>Testing each and every data field of StoreLibIR-2 library </li></ul></ul></ul><ul><ul><ul><li>Expected more than 200+ perl script for StoreLibIR-2 library testing </li></ul></ul></ul><ul><ul><ul><li>Expected more than 20 defects in StoreLibIR-2 testing </li></ul></ul></ul><ul><li>100 % testing coverage to StoreLibIR -2 Library testing. </li></ul>
  16. 16. IR-1E and SimDiscovery testing <ul><li>Integrated RAID -1E Testing </li></ul><ul><li>Requirement: </li></ul><ul><li>To test Integrated RAID 1E ASM (Adjacent stripped mirroring) </li></ul><ul><li>Project Highlight: </li></ul><ul><li>Created perl script and manual test case to test IR 1E ASM testing </li></ul><ul><li> Expected more than 120 test cases </li></ul><ul><li> Expected more that 10 defects </li></ul><ul><li> 100 % testing coverage </li></ul><ul><li> 0 % schedule variance </li></ul><ul><li>SimDiscovery Testing </li></ul><ul><li>Requirement: </li></ul><ul><li> To test Discovery process by using SimDiscovery simulation tool </li></ul><ul><li>Project Highlight: </li></ul><ul><li> Complex topology created and tested to simulate real scenarios. </li></ul><ul><li> Expected more than 20 defects </li></ul><ul><li> 100 % coverage </li></ul>
  17. 17. Standards and Testing Tool <ul><li>Standards : </li></ul><ul><li> SCSI Block Commands (SBC-3) </li></ul><ul><li> SCSI Primary Commands (SPC-4) </li></ul><ul><li> ATA/ATPI command set (ATA8-ACS) </li></ul><ul><li>Testing Tool : </li></ul><ul><li> Crack Monkey </li></ul><ul><li> GreenHills Probe </li></ul><ul><li> StoreLib Test </li></ul><ul><li> Fracture </li></ul>
  18. 18. Metrics-Project Efforts
  19. 19. Metrics- Reported Defects
  20. 20. Quality <ul><li>Attended SCG quality training </li></ul><ul><li>Value addition to quality process </li></ul><ul><li>SCG quality process followed holistically </li></ul><ul><li>Maintained all the artifacts in clear Case </li></ul><ul><li>Attention towards improving SCG quality process </li></ul>
  21. 21. Achievments <ul><li>On Time Schedule delivery </li></ul><ul><li>Achieved Defect Ratio </li></ul><ul><li>100 % testing coverage </li></ul>
  22. 22. Patni’s Contribution 2006 2007 2008 2009 2010 Performance RAID Controller LSI Tarari Processor MultiCore Architecture in Mobile Networks An innovative blue print for an asymmetrical multicore architecture targeted at mobile networks Industry’s first single chip, low cost solution for content inspection LSI as the worldwide leader in host bus RAID controller unit shipment Minimum Resources Maximum Efficiency 0 % Schedule Variance 100 % Code Coverage Maximum Defect count Patni LSI
  23. 23. Thank You