5.1.seyler

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5.1.seyler

  1. 1. Evaluation of a 12 bits Video Processor for Space Application J.-Y. Seyler, F. Malou, G. Villalon ( CNES, Toulouse - France )
  2. 2. Presentation Plan : <ul><li>The Context </li></ul><ul><li>The Purpose </li></ul><ul><li>You said « CSP » ??? </li></ul><ul><ul><li>CSP Functions </li></ul></ul><ul><li>Preliminary Tests </li></ul><ul><ul><li>Preliminary Selection </li></ul></ul><ul><ul><ul><li>From 5 to 3 candidates </li></ul></ul></ul><ul><ul><li>Characterization Principle </li></ul></ul><ul><ul><li>Measurements Results </li></ul></ul><ul><ul><ul><li>1 possible candidate </li></ul></ul></ul><ul><ul><li>Complementary Tests </li></ul></ul><ul><li>“ Lot Evaluation ” Tests </li></ul><ul><ul><li>Quality, Reliability & Radiations Evaluation </li></ul></ul><ul><ul><li>Electrical Tests </li></ul></ul><ul><ul><li>Radiations Validation </li></ul></ul>
  3. 3. Context (1/2) : <ul><li>In space applications, analog electronics for CCD signals processing uses usually specifically designed devices such as : Asics or Hybrid Circuits ... </li></ul><ul><li>Today : </li></ul><ul><ul><li>Performances needs are increasing  ( maximum pixel frequency, linearity, noise ... ) </li></ul></ul><ul><ul><li>While the mean power consumption should be decreased  </li></ul></ul><ul><li>So, commercial CMOS CCD Signal Processor ( CSP ) are a possible solution to cope with all these constraints. </li></ul>
  4. 4. Context (2/2) : <ul><li>In the last years, low power CMOS CSP where introduced on the market for wide diffusion applications ( digital imaging, video, … ). </li></ul><ul><li> BUT : according to their incomplete datasheets it is not possible to accept those devices in a space payloads without complementary measurements ! </li></ul><ul><li>Measurements objectives : </li></ul><ul><li>With a specifically developed electronic bench, characterization : </li></ul><ul><li>of Critical Parameters ( linearity, noise ) </li></ul><ul><li>and Sensibility to Environmental Influence. </li></ul>
  5. 5. Purpose : <ul><li>In order to optimise the performance of the electronics of video equipments, we have tested several “ Video Processors ” ( or CSP = “ CCD Signal Processor ” or AFE = “ Analog Front End ” ). </li></ul><ul><li>PRELIMINARY TESTS : </li></ul><ul><ul><li>These tests were based on : </li></ul></ul><ul><ul><ul><li>Latchup sensitivity </li></ul></ul></ul><ul><ul><ul><li>Electrical performances ( some tests at several temperatures ) </li></ul></ul></ul><ul><ul><li>They have then allowed to select one possible candidate. </li></ul></ul><ul><li>LOT EVALUATION TESTS : </li></ul><ul><ul><li>So, we have bought several parts from the same lot ( 2 sub-lots ) </li></ul></ul><ul><ul><li>and performed a “ Lot Evaluation ” : </li></ul></ul><ul><ul><ul><li>Lot Qualification ( “ COTS ” philosophy ) </li></ul></ul></ul><ul><ul><ul><li>Radiation sensitivity ( Latchup, Total Dose, Single Event Upset ) </li></ul></ul></ul>
  6. 6. You said : “ CSP ” ??? : <ul><ul><ul><li>The Analog Video Signal Processing </li></ul></ul></ul><ul><ul><ul><li>The CSP Function </li></ul></ul></ul>
  7. 7. Analog Video Signal Processing : <ul><li>1 single consumer “ Off-the-shelf ” electronics component may replace several functions  </li></ul>Video Chain Detector Analog Processing Electronics Analog to Digital Conversion Detector Implementation Electronics Timing Generator Power Supply Interface to Digital Devices N bits CCD PROCESSOR Photons
  8. 8. You said « CSP » ??? <ul><li>What is an CSP , « CCD Signal Processor » ? </li></ul><ul><li>It is a Integrated Circuit which is usually composed of the following elements : </li></ul><ul><ul><li>Input DC value compensation ( Clamp ), </li></ul></ul><ul><ul><li>Correlated Double Sampling ( CDS ), </li></ul></ul><ul><ul><li>Signal scaling by Variable Gain Amplifier ( VGA ), </li></ul></ul><ul><ul><li>Analog to Digital Converter ( ADC ), </li></ul></ul><ul><ul><li>Offset Calibration Loop based on Dark Pixels. </li></ul></ul><ul><ul><li>Additional functions : DAC, auxiliary A / D… </li></ul></ul>
  9. 9. CSP Functions : CDS CCD IN VGA A/D CONVERTER OFFSET REGISTER CLPDM SHP SHD CLPOB ADCCLK Input Clamp Correlated Double Sampling Dark Pixel Offset Correction Gain and A/D Conversion
  10. 10. Preliminary Selection : <ul><ul><ul><li>Latch-Up sensitivity Test </li></ul></ul></ul><ul><ul><ul><li>Electrical Characterization </li></ul></ul></ul><ul><ul><ul><li>Selection Criteria </li></ul></ul></ul>
  11. 11. Preliminary Selection : <ul><li>Latch-Up sensitivity Test ( CNES Quality Dep t ) : </li></ul><ul><ul><li>Bibliographic survey </li></ul></ul><ul><ul><li>Elimination of several fab-less candidates </li></ul></ul><ul><ul><li>5 types among 2 manufacturers </li></ul></ul><ul><ul><li>Latch-up tests </li></ul></ul><ul><ul><li>3 candidates among 2 manufacturers </li></ul></ul><ul><li>Full Electrical Characterization : </li></ul><ul><ul><li>Inter-calibration with other bench ( on 1 part already tested ) </li></ul></ul><ul><ul><li>Tests ( @ SODERN ) </li></ul></ul><ul><li>1 only candidate left </li></ul>
  12. 12. Criteria & Selected CSPs : <ul><ul><ul><ul><ul><li>Our need : </li></ul></ul></ul></ul></ul><ul><ul><li>1 Channel only, </li></ul></ul><ul><ul><li>Resolution = 12 bits, </li></ul></ul><ul><ul><li>20 MSamples / Second </li></ul></ul><ul><ul><li>Offset calibration loop ( based on dark pixels ) </li></ul></ul><ul><ul><li>Programmable Gain : ~ 0  40 dB. </li></ul></ul><ul><li>We have eventually selected 3 CSPs : </li></ul><ul><ul><li>Candidate 1 ( Analog Devices ) : 70 mW </li></ul></ul><ul><ul><li>Candidate 2 ( Texas Instruments ) : 80 mW </li></ul></ul><ul><ul><li>Candidate 3 ( Texas Instruments ) : 7 5 mW , Low Latchup sensitivity </li></ul></ul>
  13. 13. SEL Sensitivity / LET :
  14. 14. Preliminary Tests : <ul><ul><ul><li>Test Bench presentation </li></ul></ul></ul><ul><ul><ul><li>General Performances of the CSP </li></ul></ul></ul><ul><ul><ul><li>Complementary tests of the candidate </li></ul></ul></ul><ul><ul><ul><li>Thermal Characterization & Radiation Tests </li></ul></ul></ul>
  15. 15. Characterization Principle : Control Computer Data exploitation DAC 16 bits Clocks Synthesis <ul><li>Pattern Generation </li></ul><ul><li>Bench Configuration </li></ul><ul><li>I/O bench </li></ul><ul><li>Performances computation </li></ul><ul><li>Graphic display </li></ul><ul><li>Storage </li></ul>CSP under Test Real Time recording
  16. 16. Bench : <ul><li>Video stimuli waveform </li></ul><ul><li>Performances : </li></ul><ul><li>9.25 Mhz maxi pixel frequency </li></ul><ul><li>Better than +/- 2 LSB (12) integ. linearity </li></ul>Benchmark and Evaluation Board
  17. 17. General Performances of the CSP : <ul><ul><ul><li>Differential Non Linearity </li></ul></ul></ul><ul><ul><ul><li>Integral Non Linearity </li></ul></ul></ul><ul><ul><ul><li>Noise Performance </li></ul></ul></ul>
  18. 18. Differential Non Linearity Performance :
  19. 19. Integral Non Linearity Performance :
  20. 20. Noise Performance :
  21. 21. Measurements Results : <ul><li>Differential Non Linearity performance </li></ul><ul><li>Integral Non Linearity performance </li></ul><ul><li>Noise performance </li></ul><ul><li>Comparison versus “ Space application ” requirements : </li></ul><ul><li> Compatible with high performances applications  </li></ul><ul><li> … but with complementary measurements ! </li></ul>
  22. 22. Complementary Tests : <ul><ul><ul><li>Complementary Electrical Tests </li></ul></ul></ul><ul><ul><ul><li>Total Dose Tests </li></ul></ul></ul>
  23. 23. Complementary Tests (1/3) : <ul><li>Complementary Electrical Tests : </li></ul><ul><ul><li>Some additional electrical tests ( @ room temp ) </li></ul></ul><ul><ul><li>Tests at : - 20 °C, + 25 °C, + 70 °C </li></ul></ul><ul><li>Total Dose Tests : </li></ul><ul><ul><li>Some concerns about dose rate ( “ Rebound Effect ” ? ) </li></ul></ul>CSP
  24. 24. <ul><ul><li>Electrical Tests made at ambient temperature , and related with project specifications : </li></ul></ul><ul><ul><ul><li>Pleiades Satellites needs </li></ul></ul></ul><ul><ul><ul><li>+ Specific tests for next projects ( “ Post Pleiades ” & Scientific Payloads ) : </li></ul></ul></ul><ul><ul><ul><ul><li>Large Reset peak </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Saturated pixel </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Clamp efficiency ( V_ref influence for V_util = V_ref = C t ) </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Offset correction </li></ul></ul></ul></ul>Complementary Tests (2/3) :
  25. 25. Complementary Tests (3/3) :
  26. 26. Lot Evaluation : <ul><ul><ul><li>Quality, Reliability </li></ul></ul></ul><ul><ul><ul><li>Electrical Tests </li></ul></ul></ul><ul><ul><ul><li>Radiations Validation </li></ul></ul></ul>
  27. 27. The Future : “ Lot Evaluation ” (at CNES) <ul><li>Procurement of “ Commercial Quality Level ” & “ Extended ” Temperature Range ( -20°,+85°C ) </li></ul><ul><li>Purpose : </li></ul><ul><ul><li>Quality, Reliability & Radiations Evaluation </li></ul></ul>
  28. 28. Quality, Reliability & Radiations Evaluation Procurement 750P – DC0501 250P – DC044 Construction Analysis Radiation Test : TID + SEU 11P TID + 5P SEU DC0501 Performance Characterization 6P DC0440 Serialization Electrical Characterization -40°C/–20°C / +25°C / +75°C/+125°C Life Test 10P Electrical Measurement -40°C/+25°C/+125°C DPA Final Report 6P DC0501 13P DC0501 13P DC0501 10P DC0501 1P Reference 3P
  29. 29. Specific Test Bench : <ul><li>Developed @ CNES Qual. laboratory for : </li></ul><ul><ul><li>Biasing the component ( Stimuli Generation ) </li></ul></ul><ul><ul><li>Static & Dynamic performances. </li></ul></ul><ul><li>FPGA delivers different digital stimuli which are transferred through a 16bits Digital to Analog Converter at the input of the CSP. </li></ul><ul><li>The EXA3000 ( ATE ) tester ensures the control signals generation, the data reception and the processing ( parameters extraction ) </li></ul>FPGA Ramp CCD Format DAC 16 bits 1 > f > 600 MSPS CSP under TEST EXA3000 <ul><li>DNL, INL Extraction </li></ul><ul><li>Functional </li></ul><ul><li>Characterization : </li></ul>AC DC D1 1 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Din Pin 8 Bits DAC 8 Bits DAC
  30. 30. Electrical Tests : <ul><li>Up rating / Electrical characterization at 5 temp.  : </li></ul><ul><ul><li>- 20 °C / + 25 °C / + 75 °C  conformity with the manufacturer’s datasheet </li></ul></ul><ul><ul><li>- 40 °C & + 125 °C  possibility of temperature range extension ? </li></ul></ul><ul><li>Dynamic Life Test (10 parts) : </li></ul><ul><ul><li>2000 hours, </li></ul></ul><ul><ul><li>T = 125 °C, </li></ul></ul><ul><ul><li>Vcc = 3.3 V </li></ul></ul><ul><ul><li>Intermediate electrical measurement : 168 h, 500 h, 1000 h @ Tamb = 25 °C with F = 15 Msps. </li></ul></ul><ul><ul><li>The final measurement will be done at 3 temperatures. </li></ul></ul><ul><ul><li>Final DPA </li></ul></ul><ul><li>Construction Analysis ( 6 parts ) : </li></ul><ul><ul><li>Identify & describe the Front-End and Back-End technologies. </li></ul></ul>
  31. 31. Radiations Validation : <ul><li>Total Ionizing Dose : </li></ul><ul><ul><li>11 parts ( 8 On, 2 Off, 1 Ref. ) with ONERA DESP Cobalt60 Source </li></ul></ul><ul><ul><li>Total Dose : 15Krad ( Si ) & 30Krad ( 2 lots ) @ 30 rad / h </li></ul></ul><ul><ul><li>Low Dose Rate ( because of the “Rebound Effect” found after 14 krads in previous TID test ) </li></ul></ul><ul><ul><li>Annealing : 24 h / 25 °C + 168 h / 100 °C </li></ul></ul><ul><li>All the datasheet parameters : measured at ambient temperature & 15 Msps. </li></ul><ul><li>Heavy Ions Tests : </li></ul><ul><ul><li>Previous tests showed that the CSP is not sensitive to Single Event Latch-up for a LET of 60 MeV / mg . cm ² </li></ul></ul><ul><ul><li>Single Event Effect ( Transient, Upset or Functional Interrupt ) </li></ul></ul><ul><ul><li>UCL ( Belgium ) heavy ions facilities + specific test bench ( stimuli, count, record events ) with TRAD support. </li></ul></ul>
  32. 32. Conclusion : <ul><li>At the end of the validation of the lot (beginning 2007), we will be able to answer to the question : </li></ul><ul><li>“ Is our selected CSP, coming from commercial procurement recommended for usage in our spaceflight applications ??? ” </li></ul>

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