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Day1 02.Introduction

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Introduction

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Day1 02.Introduction

  1. 1. Introduction
  2. 2. Introduction Brief history of modern electronic design
  3. 3. History: x86 and ..... 10B PAL TTL Altera MMI '60 '83 '78 MOS Xilinx CMOS '84 IC 1B tsmc '65 Moore's Law 100M IBM Apple IBM PC II PC AT 10M
  4. 4. Moore's Law 1965: a doubling every 12 months 1975: the future rate of increase in a complexity to doubling every two years
  5. 5. Evolution of PC mother- board 286(MCU+TTL or PAL) today(MCU+N+S)
  6. 6. A Motorola 68000-based com- puter with various TTL chips
  7. 7. A real-time clock built of TTL chips designed about 1979.
  8. 8. Logic Family
  9. 9. Logic IC Technology Life Cycle: ti/2007
  10. 10. PAL(Programmable Array Lo- MMI, gic) 1978 GAL, Lattice, 1985 AMD, 1983
  11. 11. History of PLD: Altera CMOS PLD $B 3.0 Simple Control Logic Complex System SOPC Logic Logic 2.5 CPLD SPLD 2.0 1.5 1.0 MAX+PLUS II MAX 7000 7032V AHDL MAX 9000 0.5 ALTR TTL LIB FLEX 8000 FLEX 10K FLEX 10KA APEX Mercury Stratix IPO EP1200 ACCESS EDA IP Library FLEX10KE ARM Transceivers First EPB1400 MAX 7000A Nios Cyclone PLD 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03
  12. 12. Application : World of Digital and Ana- log Computation, control, communication Analog: ● continuous time temperature, pres- sure Why Digital? Digital: ● discrete time ex,
  13. 13. otor Control: ti
  14. 14. Motion Control: Altera
  15. 15. Motion Control: Altera
  16. 16. Introduction What kind of Problems to be solved by logic design
  17. 17. What kinds of problem Digital Only: two Value, Binary, 1/0 ● ● Control ● Communication ● Computation ● ●
  18. 18. Example: Detector and control Event: True (T) ON False(F) OFF Voltage: High (H) 1 Low(L) 0 Sensor Input: T, Pressure If (A OR B OR C) then If (T > 80) then ALARM ALARM else else
  19. 19. Example: Sequence Starting up your Car Motor control Washing Machine Off Menu of Cellar Phone Off Off Start Start Running
  20. 20. Solution to Logic Design: Why PLD Consideration HW ● ● Performance Full Custom ● ● Cost ASIC(std Cell) ● ● Schedule Discrete: TTL, ..... ● ● CPLD ● ● FPGA ● SW/FW ● ● Mixed HW/SW ● uC ● ●
  21. 21. Rising Cost of Development Technology RTL Gates Verification Synthesis + P&R Engineering Qtr./Person Qtr./Person Qtr./Person Man Years 0.35 µ 14 30K 15K 125K 0.25 µ 30 36K 18K 300K 0.18 µ 38 50K 25K 500K 0.15 µ 41 75K 38K 750K 0.13 µ 46 110K 55K 1.0M 0.09 µ 52 150K 75K 1.25M Technology Engineering Costs ($Ms) Masks & Wafers ($) 0.35 µ 2 80K 0.25 µ 5 160K 0.18 µ 6.4 400K 0.15 µ 7.3 600K 0.13 µ 8.8 900K 0.09 µ 10.4 1.3M
  22. 22. General Development Cycle
  23. 23. How we design Structural module, symbol Schematic: lines, name Functional module Physical name Block Cell Language: HDL Wire Level of Abstraction Behavior, system
  24. 24. Introduction Review of Binary Number & Boolean Algebra
  25. 25. Binary Number System LSB: least significant bit MSB: Most significant bit
  26. 26. How many bits are suffi- cent Given N, the minimum integer k, Telephone: 8bits k ● 2 N ● N=10, k=4 CD : 16bits ● ● E-ASCII Code, k=8 ● { high, medium, low}, k=2 ● 3 digital: 0℃ ~ 100℃, k=7 ● K=8, N= 0 ~ 255 ● K=10, N=0 ~ 1023 1K ● K=16, N=0 ~ 65,535 64K ● K=32, N=0 ~ 4,294,967,295 4KKK = 4G ●
  27. 27. Binary and Decimal Con- version Binary to Decimal Decimal to Binary
  28. 28. Binary Addition and Sub- traction 0+0→0 ● 1 1 1 1 1 (carried digits) 01101 0Dh 13 0+1→1 ● + 10111 17h 23 1+0→1 ● --------------------------------------- =1 0 0 1 0 0 24h 36 1 + 1 → 0, ● carry 1 (1+1 → 10) 0−0→0 (starred columns are borrowed from) ● * * ** 0 − 1 → 1, ● 1101110 6Eh 110 − 10111 17h 23 borrow 1 ------------------------------------------ 1−0→1 =1 0 1 0 1 1 1 57h 87 ● 1−1→0 ●
  29. 29. 2's Complement(1) 10's complement of 95 = 10^2 – 95 =5 ● 9's complement of 95 = 99 – 95 = ● 4 ● CM(10's) = CM(9's) + 1 ● 2's complement 0001 = 2^4 – 0001 = 1111 ● 1's complement 0001 = 2^4 – 1 – 0001 An N-bit 1110 = two's-complement numeral system can represent every integer in the range −2^(N-1) to +2^(N-1)-1. 4bit: -2^(3)= -8 to +2^3-1 = +7 8bit: -128 to +127 In this way, we only need ADDER But how it works??
  30. 30. 2's Complement(2) A - B = A + (not B + 1) // ( ) :2's comple- ● ment
  31. 31. 2's complement(3) Overflow ●
  32. 32. What is Logic: Boolean al- gebra a logical calculus of truth values, ● developed by George Boole(1815~1864, English). ● Algebra of two values. These are usu- ally taken to be 0 and 1, false and true, low and high NOT: ¬A, ~A, !A If A = 0 then !A = 1 and if A = 1 then !A= 0 AND: A ︿ B, A*B, AB A product term is 1 only when all terms are a 1 OR: A ﹀ B, A+B A product term is 1 only when any terms is a 1
  33. 33. Law of Bolean Algebra commutativity 交換律 ● A+B = B+A, A*B = B*A Associativity 結合律 ● A+(B+C) = (A+B)+C, A*(B*C) = (A*B)*C Distributive 分配律 ● A*(B+C) = A*B+A*C
  34. 34. Bolean Algebra: basic rules 10. A + A*B = A 1. A + 0 = A = A*(1 + B) where (1+B) according to Rule 2 is equal to 1 2. A + 1 = 1 =A 3. A*0 = 0 11. A*(A+B) = A 4. A*1 = A 5. A + A = A =A*A + A*B Distributive Law 6. A + !A = 1 =A+A*B Rule 7 =A Rule 10 7. A*A = A 12. A + !A*B = A + B 8. A*(!A)= 0 = A*(B+1) + !A*B according to Rule 2 (B+1) = 1 9. !(!A)= A = A*B +A + !A*B = B*(A + !A ) + A according to Rule 6 A + ~A = 1 =B+A 13. (A+B)*(A+C) = A+B*C = A*A+A*C+A*B+B*C applying the Distributive Law = A*(1+C+B) +B*C according to Rule 2 (1+B+C) = 1 = A+B*C
  35. 35. Bolean Algebra: De Morgan's laws De Morgan's laws, ● !(A*B) = !A + !B , !(A+B) = !A * !B Example ● ![(A+ B*C)*(A*C+ B)] = ![(A+B*C)] + ![(A*C+B)] = [!A]*[!(B*C)] + ![A*C] * [!B] = !A *[!B + !C] + [!A + !C] * [!B] = !A* !B + !A*!C + !A*!B + !C*!B = !A* !B + !A*!C + !B*!C
  36. 36. Bolean Algebra: Switch LED = X*Y LED = X + Y
  37. 37. Boolean Algebra: Gate Symbol, Truth Table(1) AND OR NOT
  38. 38. Boolean Algebra: Gate Symbol, Truth Table(2) XOR XNOR NAND NOR
  39. 39. NAND implemented by NOR
  40. 40. NOR implemented by NAND
  41. 41. NAND: an fan failure de- tector 0: Fail 1: Ok ALARM Positive Logic Negative Logic
  42. 42. NOR: an detecor in Wash- ing Machine 1: Lid open Normal 1: < min water level OFF 1: > max weight
  43. 43. SOP(sum of product) POS(product of sum) SOP To derive the Sum of Products form from a truth table, OR together all of the minterms which give a value of 1. POS To derive the Product of Sums form from a truth table, AND together all of the maxterms which give a value of 0. Any boolean expression may be expressed in terms of either minterms or maxterms.
  44. 44. Will we start design now ? With knowledge up to now, we can start to design ● 『 combinational 』 logic circuit such as Decoder, Adder,,,, etc, whenever we have a 『 spec 』 or 『 truth table 』 derived from the problem re- quirement. Traditionally, Karnaugh Map & Boolean Expres- ● sion Simplification technics will be introduced for design optimization. But.....we will skip this portion since we are using ● HDL and FPGA/CPLD other than TTL or ASIC. Let's see “why” later. ●
  45. 45. Introduction Evolution of Programmable Logic device From TTL to CPLD, FPGA
  46. 46. TTL Design
  47. 47. PROM: combinational logic implemena- tion
  48. 48. PLA(Programmable Logic Ar- ray)
  49. 49. PAL(Programmable Array Lo- gic) fixed-OR, programmable-AND SOP Security Flexibility Tools: HDL – ABEL, CUPL, PALASM quot;one-time programmablequot; (OTP) SOP
  50. 50. GAL(Generic Array Logic) 22V10 EEPROM
  51. 51. GAL OLMC(OUTPUT LOGIC MACROCELL) Output Select Input/Feedback Select
  52. 52. CPLD Global Routing, more control on IO
  53. 53. Altera, MAX 3000A
  54. 54. MAX 3000 MacroCell
  55. 55. FPGA
  56. 56. FPGA LE
  57. 57. MAX II and Cyclone Family
  58. 58. MAX CPLD Family
  59. 59. MAX II LE
  60. 60. MAX II LAB
  61. 61. MAX II Device Floor Plan CFM: Configuration Flash Memory UFM: User Flash Memory
  62. 62. MAX II Global Signal: Clock, or con- IO PINS trol Generated Internally Design Style
  63. 63. MAX II
  64. 64. FPGA CPLD Comparison FGPA CPLD Fine-Grain, Coarse-Grain, Arch PAL Gate-array Like like LAB LE, LUT Layout LAB around Global Connect Grid Array Interconn LAB Local and Global LAB Local and row/col Conf (E)EPROM-based SRAM-based instant-on require programming Scale Medium to small Very Large design timing Fast, predictable dependent memory No memory large memory Power Less power High power misc NA DSP, TRCVR
  65. 65. Application
  66. 66. Introduction FPGA/CPLD Design Environment & Flow Generic introduction and RTL simu- lation
  67. 67. Typical Design Flow
  68. 68. Typical Design Flow
  69. 69. Design Flow ModelSim Programming
  70. 70. Quartus: Design Entry
  71. 71. Introduction What is Verilog HDL, take a tour of 1 st tutorial example logic simulation
  72. 72. What is HDL A Hardware Description Language (HDL) is a high-level programming language that offers special constructs with which you can model microelectronic circuits. These special language constructs permit you to: Describe the operation of a circuit at various levels of abstraction, behavior, function, structure, timing of a circuit. Language for the concurrency of hardware, not a software language timing Synthesis: mapping to physical
  73. 73. Why HDL Top-down design methodology using synthes- ● is Implementation/technology highly independ- ● ent Quickly/easily explore design alternatives ● Architectural problems ● Re-use ● Design productivity ● Take advantage of mature software design ● practices
  74. 74. Verilog History 1980’s Gateway Design Automation developed Veri- ● log 1990 Cadence acquired Gateway ● 1991 Cadence released Verilog to the public do- ● main. 1995 IEEE ratified the Verilog LRM ● We will use (IEEE Std. 1364-1995) 2001 IEEE updated the Verilog LRM ● System Verilog ●
  75. 75. Verilog Usage System architects: ● system level Simulations ASIC and FPGA designers: ● RTL code for synthesis Verification engineers: ● tests for all level of simulation Model developers: ● component behavior, ex DRAM SystemVerilog
  76. 76. Introduction Lab1: your 1st Verilog 『 Program 』
  77. 77. What we did in Lab1 Model Test Bench counter,v tcounter.v Simulator ModelSim Text Output Waveform
  78. 78. tcounter.v module test_counter; initial // Test stimulus reg clk, reset; begin wire [7:0] count; reset = 0; #5 reset = 1; counter dut (count, clk, reset); $display(quot;helloquot;); #4 reset = 0; initial // Clock generator end begin clk = 0; initial forever #10 clk = !clk; $monitor($stime,, reset,, clk,,, count); end endmodule
  79. 79. counter.v module counter (count, clk, reset); module and module port output [7:0] count; declaration: output, input, inout input clk, reset; reg data type register reg [7:0] count; always @ (posedge clk or posedge reset) if (reset) count = 8'h00; else count <= count + 8'h01; endmodule
  80. 80. Verilog Module test_counter dut Stimulus and control Response monitor count[7:0] clk verification reset counter
  81. 81. TOP DOWN Design Hier- archy
  82. 82. Module
  83. 83. Module port
  84. 84. Module Instance
  85. 85. Test Bench
  86. 86. Procedure Blocks
  87. 87. Applying stimulus Time clk reset initial // Clock generator 0 0 0 begin 5 0 1 clk = 0; 9 0 0 forever #10 clk = !clk; 10 1 0 end 20 0 0 30 1 0 initial // Test stimulus ........................... begin reset = 0; #5 reset = 1; What is time unit ? #4 reset = 0; end
  88. 88. Checking the Response Example: $monitor($time, o, in1, in2); $monitor($time,, out,, a,, b,, sel); $monitor($time,, ”%b %h %d %o”, sig1, sig2, sig3, sig4); Syntax: C-Like $monitor ([”format_specifiers”,] arguments);
  89. 89. Behavior Modeling Describes a system by the flow of data between its functional blocks, or algorithm Defines signal values when they change a=b*c wait a;
  90. 90. RTL Modeling Describes a system by the flow of data and control signals between and within its functional blocks Defines signal values with respect to a clock
  91. 91. Structure Modeling Describes a system by connecting predefined components Uses technology-specific, low-level components when mapping from an RTL description to a gate-level netlist, such as during synthesis
  92. 92. RTL Synthesis
  93. 93. Why we skip Logic Optim- ization HDL ● FPGA/CPLD vs TTL, ASIC Cell ● ● ● Let Machine do what it excels ● You give direction. ● You have to know what you really want. Speed, Area, Power ● Design Scale Dependent. ●
  94. 94. Summary Brief History ● Review of Number system and Boolean Al- ● gebra ● Basic concept of CPLD/FPGA ● HDL Tour: ● modules; ports, instances ● Test Bench ● Stimulus ● Response

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