Black Box Consulting 2009 Brochure

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Details of our Products and Services, including Xilinx Training courses available online, publically, or onsite, FPGA support consulting, and recrutiment

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Black Box Consulting 2009 Brochure

  1. 1. Black Box Consulting 2009 Products & Services Brochure Authorised Digilent Distributor Authorised Training Provider
  2. 2. Authorised Digilent Distributor 2 Authorised Training Provider
  3. 3. Table of Contents Table of Contents .................................................................................................................................... 3 Recruitment Services .............................................................................................................................. 4 Consulting Services ................................................................................................................................. 5 Xilinx Training Courses ............................................................................................................................ 6 Academy I........................................................................................................................................ 7 Academy II....................................................................................................................................... 9 Academy III.................................................................................................................................... 11 DSP Implementation Techniques using Xilinx FPGAs.................................................................... 14 DSP Design Using System Generator ............................................................................................ 15 Embedded System Development.................................................................................................. 16 Advanced Features & Techniques of Embedded System Development....................................... 17 Embedded System Software development .................................................................................. 18 Embedded Open-Source Linux Development ............................................................................... 19 Designing with Ethernet MAC Controllers .................................................................................... 20 Designing with Multi-Gigabit Serial I/O ........................................................................................ 21 Advanced VHDL ............................................................................................................................. 22 Fundamentals of CPLD Design ...................................................................................................... 23 Designing For Performance for CPLDs .......................................................................................... 24 Designing with Virtex-4 ................................................................................................................. 25 Designing with Virtex-5 ................................................................................................................. 26 Digilent Xilinx Demo Boards .................................................................................................................. 27 Pricing Guide ......................................................................................................................................... 29 Recruitment .................................................................................................................................. 29 Training ......................................................................................................................................... 29 Consulting ..................................................................................................................................... 29 Credit Packages ............................................................................................................................. 30 Terms & Conditions............................................................................................................................... 31 Contact Details / About Us.................................................................................................................... 33 Authorised Digilent Distributor 3 Authorised Training Provider
  4. 4. Recruitment Services Black Box Consulting can offer you a complete recruitment package which can include training. When you recruit with us we can offer you: • A partnership where we will work with you to understand your business • Expertise allowing us to understand the requirements of employees at a technical level • FPGA training to ensure new employees start with the knowledge and skills needed to contribute to your business from day one In a technical environment, where knowledge relates to time to market, it’s important to ensure you recruit engineers with sound technical ability and promise, as well as the ability to form a team with strong morale and work ethic for tangible results. How do you do this? At Black Box consulting we: • Take a firm brief of the role and thoroughly understand it • Assist with Job Descriptions, salary expectations, writing and placement of adverts • Provide advice, assist in writing, and conduct technical assessments for further screening • Create a candidate sourcing strategy from local and overseas markets if applicable • Work closely with Universities to source talented and fresh Engineers • Control the entire recruitment process from sourcing, reviewing and filtering applications, to short listing, interviewing and providing reports • Carry out reference checking and optional background and Psychometric testing • Provide you with professional recruitment advice throughout the entire process at a personnel and engineering level • Follow up with new employees during those more difficult first six months, and can act as a neutral entity for employee reviews Recruitment can be an underestimated and ongoing concern for many companies. The process can take a considerable amount of time and resources through out, let alone if it needs to be repeated. Our aim is to reduce the resources and time required from your company and at the same time delivery exceptional value and quality candidates from your recruitment campaigns. Roles recruited in the past: Engineering Management Sales Marketing Electronic Engineers General Manager Sales Manager Technical Marketing Electrical Engineers State Managers Account Managers Brand Managers Project Managers Product Managers Sales Engineers Marketing Analysts Our services can also be broken down into modules to integrate into your existing HR practices. Authorised Digilent Distributor 4 Authorised Training Provider
  5. 5. Consulting Services At Xilinx, as a Strategic Applications Engineer, Peter Boxall spent his time supporting his assigned customers’ designs. Xilinx also offer a ‘Titanium Support Service’ to assign customers a dedicated Engineer for short term assistance for anything from achieving timing closure to troubleshooting designs. During his time at Xilinx, this is something Peter did frequently, and was also the first Engineer at Xilinx to be assigned to this service in 1999. Many customer issues come down to Timing Closure, including properly constraining designs and ensuring synchronous design techniques are used to avoid those unexplained and intermittent issues. Other times it can simply be to improve design utilisation, frequency or reduce runtimes. Black Box Consulting offers consultative services of this manner to help you build faster: • Design Implementation Support o Xilinx interface o Flow support o Troubleshooting errors o Floorplanning/PlanAhead o Run Times • Timing Closure and consistency o Assistance with fully constraining your design and ensuring all paths are covered and not over constrained o Design and implementation techniques and flow support to ensure you’re using the best synthesis and implementation options to get the best performance. o PlanAhead flows to achieve timing and run time needs There are lots of tricks and techniques we can use to help get you over the line. We encourage knowledge transfer so you also learn along the way. • Troubleshooting o Design not working, or intermittently? Common reasons include asynchronous design or incomplete timing constraints. Let us bring fresh eyes to the table. • Open Days o Common for companies with multiple design groups or large teams. Have us onsite in a meeting room from time to time, where engineers can come and ask questions, fill in knowledge gaps, discuss implementation issues and ask advice. We provide consulting services both on and offsite, or a mixture of both. At this time, Black Box Consulting specialise their efforts on FPGA design support services and not full design house services. However, small design examples, modular assistance, and design conversions are within our scope. We do work closely with a small alliance of Design House companies in Australia. Please contact us for further details for such recommendations. Authorised Digilent Distributor 5 Authorised Training Provider
  6. 6. Xilinx Training Courses There are a number of ways we can provide Training to you: • Onsite Training. Starting from groups of only 3 people up to 12, arrange private, dedicated and tailored training at your own offices without having to wait for public schedules • Public Training. Low cost training for individual engineers. • Online – Live Instructor Led Training. Attend training from the comfort of your home or office, break a 5 day course into smaller blocks, reduce travel and accommodation costs and still have live training with real time presentations and questions. During labs you can share your PC applications (such as ISE) with the presenter, or even log in to one of our remote Training PCs located right next to the presenter. Using WebEx Training software it’s as good as having a presenter in the room with you. Academy I Using the Xilinx Integrated Software Environment (ISE) Fundamentals of FPGA Design Comprehensive Introduction to VHDL Academy II FPGA Design Tips & Techniques Designing for Performance Academy III Advanced FPGA Design Chipscope Pro Use and Debug Guide Designing with PlanAhead DSP courses DSP Implementation Techniques using Xilinx FPGAs DSP Design Using System Generator Embedded Courses Embedded System Development Advanced Features & Techniques of Embedded System Development Embedded Systems Software Development Embedded Open-source Linux Development Connectivity Courses Designing with Ethernet MAC Controllers Designing with Multi-Gigabit Serial I/O Other Courses Advanced VHDL Fundamentals of CPLD Design & Designing for Performance for CPLDs Designing with Virtex-4 Designing with Virtex-5 Authorised Digilent Distributor 6 Authorised Training Provider
  7. 7. Xilinx Academy I Version 10.1i rev2 Course Specification Create a new project, add source files, synthesize a design, and Xilinx Academy I Description: use the error navigation feature. Lab 2: Synthesis Options – Modify XST synthesis properties, The Academy I course consists of 3 packaged courses including: read synthesis reports to compare the synthesis results, and use the snapshot utility. • ISE Design Entry (1 Day) • Fundamentals of FPGA Design (1 Day) Lab 3: ECS – Perform the basic tasks of the schematic editor, • Comprehensive Introduction to VHDL (3 days) such as adding symbols, connecting symbols with wires, naming wires and buses, adding I/O markers, and using the Xilinx CORE Promotion: Save $60 per day and receive a free Digilent Nexys2 Generator™ tool with ECS. Demo Board worth $180. Purchase all 5 days at AU$2700 + GST. Further discounts are available with our credit packages Lab 4: ISE Simulator and the State Diagram Editor – Perform the simulation and verification process of the design cycle. Individual Days are AU $600 + GST Demonstrate how these tools are incorporated into the ISE tools. ISE Design Entry Fundamentals of FPGA Design In this course you will learn about project structure, process windows, Use the ISE® software tools to implement a design and gain a firm various ISE® software design flows, and Xilinx Synthesis Technology understanding of the Xilinx FPGA architecture. Learn the best design (XST). You will examine XST synthesis and use the XST constraints practices and understand the subtleties of the Xilinx design flow. file in the Project Navigator GUI. You will learn about the Engineering Capture System (ECS) , the State Diagram Editor and Simulator tools. This course covers ISE 10.1 features, such as the Architecture Wizard Who Should Attend? – Designers who wish to gain a well rounded and the Floorplan Editor. Other topics include design planning, knowledge of the ISE 10.1 design tools implementation options, and global timing constraints. Recommended Basic FPGA Architecture knowledge Who Should Attend? – Digital designers who have a working Software Tools knowledge of HDL (VHDL or Verilog) and who are new to Xilinx Xilinx ISE Foundation™ 10.1 Design Tools FPGAs Prerequisites After completing this comprehensive training, you will have the Basic FPGA Architecture RELs: Slice and I/O Resources, necessary skills to: Memory and Clocking Resources, Architecture Wizard and Floorplan Editor Create a new Project Navigator project in the ISE software Digital design experience List the design flows available in the ISE software Recommended Access and modify XST synthesis options Basic HDL Coding Techniques REL* (parts 1 and 2) Create a schematic design by using the ECS schematic entry tool Spartan-3 FPGA HDL Coding Techniques REL* (parts 1 and 2) Create a symbolic state machine using the State Diagram Editor Virtex-5 FPGA HDL Coding Techniques REL* (parts 1 and 2) Create testbenches and simulate a design using the TestBench Software Tools Wizard and the ISE Simulator Xilinx ISE Foundation™ 10.1 software with the ISE Simulator Course Outline Three recorded E-Learning Modules are available for this course: www.xilinx.com/education and click the Recorded e-Learning link. Course Agenda After completing this comprehensive training, you will have the Projects in the Project Navigator necessary skills to: Lab 1: Projects in the Project Navigator Use the Xilinx Project Navigator to implement and simulate an HDL Synthesis and XST FPGA design Lab 2: XST Synthesis Options Read reports and determine whether your design goals were met ECS: Engineering Capture System Use the Architecture Wizard to create DCM instantiations Lab 3: ECS Use the Floorplan Editor and PinAhead to make good pin State Diagram Editor assignments ISE Simulator Use the Xilinx Constraints Editor to enter global timing constraints Lab 4: ISE Simulator and the State Diagram Editor Locate and modify the implementation options Additional Features Summary Course Outline Course Agenda Lab Descriptions Xilinx Tool Flow Lab 1: Xilinx Tool Flow Lab 1: Projects in the Project Navigator – Gain comprehensive Reading Reports hands-on experience with the HDL flow in the ISE software. Lab 2: Architecture Wizard and Floorplan Editor/PACE © 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 7 www.blackboxconsulting.com.au
  8. 8. Xilinx Academy I Version 10.1i rev2 Course Specification Lab 3: Pre-Assigning I/O Pins Using PinAhead Use VHDL scalar and composite data types Global Timing Constraints Run a simulation by using VITAL libraries Lab 4: Global Timing Constraints Use the VHDL textio package during simulation Implementation Options Create and manage designs within the ISE design environment Lab 5: Implementation Options Synchronous Design Techniques Course Outline Course Summary Day 1 Lab Descriptions Course Agenda Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Hardware Modeling Overview Navigator and use the Architecture Wizard and the Floorplan VHDL Language Concepts Editor or PACE in the design process. Implement a design by using default software options. The design will be simulated and Lab 1: Building Hierarchy downloaded to a Spartan®-3E FPGA 1600 demo board. Introduction to Testbenches Lab 2: Architecture Wizard and Floorplan Editor/PACE – Use the Lab 2: VHDL Simulation and RTL Verification Architecture Wizard to customize a DCM and incorporate the Signals and Data Types DCM into the design. Use the Floorplan Editor to assign pin VHDL Operators and Expressions locations and implement the design. Lab 3: Memory Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with Day 2 PinAhead. Perform Weighted Average Simultaneously Switching Concurrent and Sequential Statements Output (WASSO) analysis to avoid ground bounce and use the Lab 4: Clock Divider and Address Counter Design Rule Checker to follow I/O banking rules. Controlled Operation Statements Lab 4: Global Timing Constraints – Enter global timing constraints Lab 5: n-bit Binary Counter and RTL Verification with the Xilinx Constraints Editor. Review the Post-Map Static VITAL: VHDL Initiative toward ASIC Libraries Timing Report to verify that the timing constraints are realistic. Lab 6: Timing Simulation Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for timing constraints. Behavioral to RTL Coding Lab 5: Implementation Options – Adjust process properties and Day 3 I/O configuration options to improve the design performance. Finite State Machines Lab 7: Finite State Machines Comprehensive Introduction to VHDL Targeting Xilinx FPGAs Lab 8: Implement and Download This comprehensive course is a thorough introduction to the VHDL Functions and Procedures language. The emphasis is on writing Register Transfer Level (RTL) Advanced Process Statements and behavioral source code. This class addresses targeting Xilinx Lab 9: Text I/O devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures Lab Description with practical lab exercises to reinforce key concepts and advanced coding techniques that will increase your overall VHDL proficiency The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in In this three-day course, you will gain valuable hands-on experience. the labs. You will write, synthesize, simulate, and implement all the Incoming students with little or no VHDL knowledge will finish this labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a Who Should Attend? – Engineers who want to use VHDL functional calculator that you will verify in simulation. effectively for modeling, design, and synthesis of digital designs Prerequisites Register Today Basic digital design knowledge Software Tools Black Box Consulting delivers public and private courses in locations Xilinx ISE® Foundation™ software 10.1 with the ISE Simulator throughout Australia and New Zealand. For more information, such as our range of courses, current schedules, course empowered with the ability to write efficient hardware designs and other services including consulting and recruitment/training and perform high-level HDL simulations. packages, please use one of the contact methods below: After completing this comprehensive training, you will have the Black Box Consulting necessary skills to: PO Box 1147 Write RTL VHDL code for synthesis Stafford City Write VHDL testbenches for simulation QLD 4053 Tel: + 61 7 3137 0905 Create Finite State Machines (FSMs) by using VHDL www.blackboxconsulting.com.au Target and optimize Xilinx FPGAs by using VHDL Create RAM and ROM data structures © 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 8 www.blackboxconsulting.com.au
  9. 9. Xilinx Academy II www.xilinx.com V10.1i Rev1 Course Specification Xilinx Academy II Description: Exercises The Academy II course consists of 2 packaged courses including: Exploring the Slice LUT Functions • Design Tips & Techniques for Low Cost (2 days) Logic Levels • Designing For Performance (2 days) Dedicated Multiplexers Flip Flop Controls Promotion: Save $50 per day. Attend the full Academy II at AU$2200 + GST. Further discounts available with credit packages Performance by Design Clocks Individual days are AU $600 + GST. Counters Fractional Number Formats Design Tips & Techniques Adders Wired Carry Gates This course appeals to engineers who have an interest in good design Aspect Ratios techniques, to produce compact design (for lower coast) with additional Replacing Logic with Block RAM discussion on Logic Levels for Timing. The course and exercises cover Distributed RAM several different design techniques, which will be interesting and Essence of FIFO challenging for any digital designer regardless of the final application. Delay State Machines Level – Fundamental - Intermediate Prerequisites DSP48 Optional Design Challenges An understanding of digital design and the concept of an FPGA Basic – Intermediate VHDL skills Supported Devices Note: software is only required to run optional exercises Spartan™- 3E/A/AN/DSP Virtex-4, Virtex-5 Designing for Performance Attending the Designing for Performance class will help you create After completing this comprehensive training, you will have the more efficient designs. This course can help you fit your design into a necessary skills to: smaller FPGA or a lower speed grade for reducing system costs. In Describe the features of the Spartan-II(E) and Spartan-3 devices addition, by mastering the tools and the design methodologies Accurately estimate design size to aid in predicting product costs presented in this course, you will be able to create your design faster, Apply design techniques that result in low-cost implementations shorten your development time, and lower development costs. Explore creative ways to use the FPGA memory resources to Note that one of the prerequisites of Designing for Performance is the reduce design costs completion of the HDL coding style modules listed below (or attend the much more comprehensive Intro to VHDL course). Go to www.xilinx.com/education and click the Recorded e-Learning link Course Outline to view these recorded modules. Refresh: What is an FPGA? Spartan and Virtex Family Level – Intermediate CLBs, Slices and BRAM Prerequisites Multiplexers Fundamentals of FPGA Design course or equivalent Flip-Flop Controls knowledge of FPGA architecture features; the Xilinx Synchronous Timing vs. Asynchronous Timing implementation software flow and implementation options; Digital Clock Managers reading timing reports; basic FPGA design techniques; global Number Representation timing constraints and the Constraints Editor Dedicated Carry Logic Intermediate HDL knowledge (VHDL or Verilog) Counters Solid digital design background Wired Carry Gates Basic HDL Coding Techniques REL (parts 1 and 2) Block MemoryDistributed RAM Spartan-3 FPGA HDL Coding Techniques REL (parts 1 and 2) FIFO Virtex-5 FPGA HDL Coding Techniques REL (parts 1 and 2) Dual Port Memory Software Tools State Machines ISE Foundation™ software 10.1 with the ISE Simulator DSP48 Blocks ChipScope™ Pro software Design Challenges © 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 9 www.blackboxconsulting.com.au
  10. 10. Xilinx Academy II www.xilinx.com V10.1i Rev1 Course Specification After completing this comprehensive training, you will have the necessary skills to: Lab 4: Review of Global Timing Constraints – Use the Describe a flow for obtaining timing closure Constraints Editor to enter global timing constraints. Describe architectural features of the Virtex-5 FPGA Lab 5: Achieving Timing Closure – Review timing reports and Describe the features of the Digital Clock Manager (DCM) and enter path-specific timing constraints to meet performance goals. Phase-Locked Loop (PLL) and how they can be used to improve Lab 6: Designing for Performance – Improve performance and performance maximize results solely with implementation options. Increase performance by duplicating registers and pipelining Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a Describe different synthesis options and how they can improve design and add a probe to an internal net. performance Lab 8: ChipScope Pro Software – Add an internal logic analyzer Create and integrate cores into your design flow by using the to a design to perform real-time debugging. CORE Generator™ software system Run behavioral simulation on an FPGA design that contains cores Pinpoint design bottlenecks by using the Timing Analyzer reports Apply advanced timing constraints to meet your performance Register Today goals Black Box Consulting delivers public and private courses in locations Use advanced implementation options to increase design throughout Australia and New Zealand. performance For more information, such as our range of courses, current schedules, Course Outline and other services including consulting and recruitment/training packages, please use one of the contact methods below: Day 1 Black Box Consulting Review of Fundamentals of FPGA Design PO Box 1147 Designing with Virtex-5 FPGA Resources Stafford City CORE Generator Software System QLD 4053 Lab 1: CORE Generator Software System Tel: + 61 7 3137 0905 Fax: +61 7 39015586 Designing Clock Resources Lab 2: Designing Clock Resources www.blackboxconsulting.com.au FPGA Design Techniques Synthesis Techniques Lab 3: Synthesis Techniques Day 2 Achieving Timing Closure Lab 4: Review of Global Timing Constraints Timing Groups and OFFSET Constraints Path-Specific Timing Constraints Lab 5: Achieving Timing Closure Advanced Implementation Options Lab 6: Designing for Performance Power Estimation (Optional) Lab 7: FPGA Editor Demo (Optional) ChipScope Pro Software (Optional) Lab 8: ChipScope Pro Software (Optional) Lab Descriptions Lab 1: CORE Generator Software System – Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation. Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources. Lab 3: Synthesis Techniques – Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software. © 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 10 www.blackboxconsulting.com.au
  11. 11. Xilinx Academy III V10.1i Rev1 Course Specification Xilinx Academy III Description: Advanced I/O Timing Lab 4: Advanced I/O Timing The Academy III course consists of 3 packaged courses including: SmartCompile™ Technology Design Preservation Techniques Lab 5: SmartCompile Technology • Advanced FPGA Implementation (2 days) Floorplanning an Effective Layout • Chipscope Pro Debug & Verification (1 day) Lab 6: Floorplanning • Designing with PlanAhead ( 2 days) FPGA Editor: Viewing and Editing a Routed Design Lab 7: Advanced FPGA Editor Promotion: Save $80 per day. Attend this 5 day Academy III at AU$2600 + GST. Further discounts available with credit packages Lab Descriptions Individual days are AU $600 + GST Note: Labs will be based on Xilinx ISE 10.1 software. Lab 1: Achieving Timing Closure and Review of Global Timing Constraints – Use the Constraints Editor to enter global timing Advanced FPGA Implementation constraints. This course tackles the most sophisticated aspects of the ISE® 10.1 Lab 2: Tcl Scripting – Write ISE tool control commands in a Tcl design suite and Xilinx hardware. Seven labs provide hands-on script file to implement the design. Then modify program switches experience in this two-day course and cover the Xilinx Synthesis to obtain the greatest possible performance from the design. Technology (XST) tools. This course requires the Fundamentals of Lab 3: UCF – Write constraints directly into a UCF file to guide FPGA Design and Designing for Performance courses as the performance results of implementation. prerequisites. An intermediate knowledge of Verilog or VHDL is Lab 4: Advanced I/O Timing – Compose timing constraints for an strongly recommended as is at least six months of design experience I/O interface. Analyze the timing failures and determine changes with Xilinx tools and FPGAs. The lecture material in this course covers to correct the timing issues. Modify the design to fix timing the ISE 10.1 tools and the Virtex®-5 and Spartan®-3E FPGAs. failures. Lab 5: SmartCompile Technology – Utilize SmartGuide Level – Advanced technology and partitions to preserve the timing results from one Prerequisites iteration to the next. Fundamentals of FPGA Design Lab 6: Floorplanning – Implement a design by using floorplanned Designing for Performance constraints to enhance the timing results over a design without Intermediate knowledge of Verilog or VHDL is strongly floorplanning. recommended Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view At least six months’ design experience with Xilinx tools and and edit a design. Rapidly locate and swap signals of interest for FPGAs Software Tools ChipScope Pro tool cores. Xilinx ISE Foundation™ 10.1 software with the ISE Simulator ChipScope™ Pro software Chipscope Pro Debug & Verification As FPGA designs become increasingly more complex, designers are After completing this comprehensive training, you will have the searching to reduce design and debug time. The powerful, yet easy-to- necessary skills to: use ChipScope™ Pro tool solution helps minimize the amount of time required for debug and verification. This one-day course will show you Implement designs via the Tcl command line effective ways to debug logic and high-speed designs—thereby Create and edit timing constraints in the UCF file decreasing your overall design development time. This training will Identify the I/O timing constraints and design modifications provide hands-on labs that demonstrate how the ChipScope Pro tools required for source-synchronous and system-synchronous can address advanced verification and debugging challenges. interfaces Preserve design results by using SmartGuide™ technology or Level – Intermediate partitions Prerequisites Use the Floorplan Editor or Pinout and Area Constraints Editor FPGA design experience or completion of the Xilinx (PACE) to create area constraints Fundamentals of FPGA Design course Change signals of interest in the ChipScope™ Pro tool for board- ChipScope Pro Software REL strongly recommended level debugging using the FPGA Editor (www.xilinx.com/support/training/rel/chipscopepro-rel.htm) Software Tools Course Outline ISE™ 9.2i software Introduction ChipScope Pro 9.2i software Lab 1: Achieving Timing Closure and Review of Global Timing ChipScope Pro Serial I/O Toolkit 9.2i* Constraints Agilent Logic Analyzer Application Software* Tcl Scripting Lab 2: Tcl Scripting UCF Editing Lab 3: UCF Editing © 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 11 www.blackboxconsulting.com.au
  12. 12. Xilinx Academy III V10.1i Rev1 Course Specification After completing this comprehensive training, you will have the necessary skills to: Inserting the Agilent ATC2 Measurement Core and Viewing Maximize ChipScope Pro tool core performance Internal Activity with the FPGA Dynamic Probe* – You will Minimize negative timing impacts on a design leverage external memory resources by using the Agilent ATC2 Core, FPGA Dynamic Probe, and Virtual Logic Analyzer to Use techniques that enhance and extend the capabilities of the ChipScope Pro tools address storage demands. Performing System-Level Debug with the Agilent FPGA Enable and identify the advantages of remote debugging Dynamic Probe* – You will see how the Agilent solution is used Analyze, set up, and debug high-speed serial I/O designs* to reduce the time required to validate and determine the root Use the Agilent solutions to overcome storage issues and perform cause of problems in FPGA-based systems. a system-level debug* Course Outline Agenda and Introduction Designing With PlanAhead Lab: Adding the ILA Core to an Existing Design and/or Adding the Learn to increase design performance and achieve repeatable results ILA and VIO Cores for Remote Monitoring and Control by using the PlanAhead™ software tool. Topics include: a product Timing Implications overview, synthesis and project tips, design analysis, creating a Demo: Minimizing ILA Core Impact with the PlanAhead Software floorplan, improving performance, experimenting with implementation Tips and Tricks options, incremental methodology, block-based IP design, and I/O pin Lab: Tips and Tricks assignment. Remote Debug Level – Intermediate Lab: Enabling Remote Debug* Prerequisites High-Speed Serial I/O Debug and Verification (Optional*) Fundamentals of FPGA Design or equivalent knowledge of the Lab: High-Speed Serial I/O Debug and Verification (Optional*) FPGA architecture and the Xilinx ISE® software flow Agilent Solutions for Storage Qualification and System-Level Designing for Performance recommended Debug (Optional*) Software Tools Lab: Inserting the Agilent ATC2 Measurement Core and Viewing Xilinx ISE® Foundation™ 10.1 software Internal Activity with the FPGA Dynamic Probe (Optional*) PlanAhead software 10.1 Lab: Performing System-Level Debug with the Agilent FPGA Dynamic Probe (Optional*) Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is * Please check with your ATP to confirm whether this content is supplemented with instructor-led presentations and demos. included with your specific class. After completing this comprehensive training, you will have the Lab Descriptions necessary skills to: List the main features and benefits of the PlanAhead tool Import designs into the PlanAhead tool project environment Adding the ILA Core to an Existing Design – You will use the Assign optimal I/O pin locations Core Inserter tool flow for adding the ChipScope Pro tool ILA cores into a design to rapidly locate and solve a simple logic Import HDL sources and elaborate and analyze an RTL netlist problem. Analyze design statistics, connectivity, timing, and placement Adding the ILA and VIO Cores for Remote Monitoring and results Control – You will instantiate ICON, ILA, and VIO cores into a Run the Design Rule Checker (DRC) and Weighted Average VHDL or Verilog design and practice monitoring signals of interest Simultaneous Switching Output (WASSO) analysis and externally driving select control signals. Partition and floorplan designs Tips and Tricks – This lab demonstrates the flexibility of the Run ExploreAhead to try multiple implementation strategies ChipScope Pro tool solution as you explore data qualification, Import and analyze the implementation results to improve the cross-clock domain analysis, and oversampling techniques. floorplan Enabling Remote Debug* –This lab demonstrates how the Floorplan to improve performance and consistency ChipScope Pro tools can be used across a network. You will Use block-based design and create reusable IP connect to another team’s board, download your bitstream, and remotely monitor the other team’s board on your machine. High-Speed Serial I/O Debug and Verification* – You will use the Xilinx ChipScope Pro Serial I/O Toolkit for the RocketIO™ transceivers in the Virtex™-5 FPGA. You will generate the ChipScope Pro tool IBERT design for the Virtex-5 XC5VLX50T device and customize it for the ML505 board. You will then connect two GTPs on the ML505 board and use the ChipScope Pro Analyzer tool to control the GTP parameters and monitor the effects. © 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 12 www.blackboxconsulting.com.au
  13. 13. Xilinx Academy III V10.1i Rev1 Course Specification Course Outline Register Today Day 1 Black Box Consulting delivers public and private courses in locations Course Overview throughout Australia and New Zealand. Lab 1: Getting Started with the PlanAhead Tool For more information, such as our range of courses, current schedules, I/O Pin Planning and other services including consulting and recruitment/training Lab 2: Assigning I/O Pins packages, please use one of the contact methods below: Design Analysis and Exploration Lab 3: Design Analysis and Exploration Black Box Consulting Design Partitioning and Top-Level Floorplanning PO Box 1147 Lab 4: Design Partitioning and Top-Level Floorplanning Stafford City QLD 4053 Day 2 Tel: + 61 7 3137 0905 Fax: +61 7 39015586 Implementing a Floorplanned Design Lab 5: Implementation www.blackboxconsulting.com.au Floorplanning Techniques Lab 6: Floorplanning Tuning a Floorplan for Performance Lab 7: Floorplan Tuning Block-Based Design and IP Reuse Lab 8: Block-Based Design and IP Reuse Floorplanning Strategies Course Summary Lab Descriptions Note: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool. Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views. Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments. Lab 3: Design Analysis and Exploration – Introduces the analysis features of the PlanAhead tool that enable early detection of potential design issues, alternate device selection, initial floorplanning direction, and post-implementation exploration. Lab 4: Design Partitioning – Introduces the concept of floorplanning. By using automated partitioning tools, you will create a top-level floorplan and experiment with sizing and shaping Pblocks based on resources assigned to them. Lab 5: Implementation – Introduces the integration of the ISE software implementation tools with the PlanAhead tool. Also introduces the ExploreAhead tool for queuing multiple ISE software runs with varying strategies. Lab 6: Floorplanning – Describes how to analyze implementation results and to use that information to generate a floorplan aimed at increasing design performance. Lab 7: Floorplan Tuning – Introduces techniques to help close on timing targets consistently. Lab 8: Block-Based Design and IP Reuse – Describes the steps to implement a block-based methodology that includes the creation and reuse of an IP module. © 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 13 www.blackboxconsulting.com.au
  14. 14. DSP Implementation Techniques for Xilinx FPGAs DSP20000-7-ILT (v1.0) Course Specification Course Description Day 3 This course shows you how to take advantage of the features available One Filter Does Not Make a System in the Xilinx FPGA architecture, including the Virtex™-4 FPGA, and Options to be considered with multiple channels describes how DSP algorithms can be implemented efficiently. The Interpolation and decimation techniques also demonstrate which decisions at the system level have Rate changing and its effect on FIR filter choice the greatest impact on the implementation process and product costs. Filtering algorithms that exploit device architecture Importance of connectivity versus isolated functions Level – Advanced Do Not Block the Datapath Course Duration – 3 days Price – $2000 + GST Numeric controlled oscillators and mixers Course Part Number – DSP20000-7-ILT Strategies for FFT implementation Who Should Attend? – Engineers and designers who have an Achieving bandwidth requirements of the FFT interest in developing products that use digital signal processing Using the FPGA as an efficient co-processor 3 Prerequisites Course Exercises A fundamental understanding of digital signal processing theory, including an understanding of the following principles: MAC Rates and Memory Requirements Constructing a 128-Tap FIR Filter Sample rates Fractional Number Formats Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters Twos Complement Arithmetic Oscillators and mixers Summation by Addition Tree Summation by Addition Chain Fast Fourier Transform (FFT) algorithm Full Adder: How Many Slices? Summation Structure Sizes After completing this comprehensive training, you will have the Serial Summation Structure necessary skills to: 8-Bit by 12-Bit Multiplier Describe how DSP algorithms can be implemented efficiently by KCM Multipliers using Xilinx FPGA technology Distributed RAM for FIFO Identify the capabilities and features of the various Xilinx FPGA families to implement efficient DSP algorithms Size Estimates for Delay Structures Using the SRL16E as a FIFO Establish methods for the accurate estimation of silicon area consumption and cost Creating Larger RAM Structures Evaluate which algorithms are best suited for FPGA Selecting a MAC FIR Technique implementation and identify which algorithms are less desirable Parallel FIR Filter Size Assess how system-level decisions impact hardware Symmetry, Interpolation, and Phases implementation and how hardware implementation can enhance Decimation Filter results at the system level “fs/4” Mixing and Decimation Designing a Numeric Controlled Oscillator (NCO) Course Outline FFT: Benchmarks and Transform Time Day 1 Collection Time = Processing Time On the Same Wavelength 128-Point FFT in 1.28 µs Basic terminology and acronyms used in DSP design Sample rates and bit widths used in DSP applications Register Today DSP building blocks and processing requirements Some Bits About Numbers Black Box Consulting delivers public and private courses in locations throughout Australia and New Zealand Numbering formats, range, and precision . Mathematical operations using a variety of formats For more information, such as our range of courses, current schedules, Tuning the Receiver and other services including consulting and recruitment/training Structure and Resources of Xilinx Devices packages, please use one of the contact methods below: Estimating DSP building block sizes Day 2 Black Box Consulting Tuning the Receiver (continued) PO Box 1147 Stafford City Implementing the multiplication function QLD 4053 Bit-width impact on system-level decisions Memories are Made of This Tel: + 61 7 3137 0905 Fax: +61 7 39015586 Block versus distributed memory training@blackboxconsulting.com.au SRL16E and the delay function www.blackboxconsulting.com.au Memory aspect ratios and their manipulation Selective Filters FIR filter specifications and implementation Selecting a technique for a given specification Effects of halfband and interpolated filters © 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 14 www.blackboxconsulting.com.au
  15. 15. DSP Design Using System Generator DSP11000-10-ILT (v1.0) Course Specification Course Description Lab 8: System Generator, Project Navigator, and Platform Studio Integration This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions Lab Descriptions focuses on learning how to use System Generator for DSP, design Lab 1: Using the Simulink Software – Learn how to use the implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm toolbox blocks in the Simulink software and design a system. concept to hardware verification using the Xilinx FPGA capabilities. Understand the effect sampling rate. Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based (ML505 board) design. Perform hardware co- Level – Intermediate Course Duration – 2 days simulation verification targeting an ML505 board. Price – AU$1400 + GST Lab 3: Signal Routing – Design padding and unpadding logic by Who Should Attend? – System engineers, system designers, logic using signal routing blocks. designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB® and Lab 4: Implementing System Control – Design an address Simulink® software and want to use Xilinx System Generator for generator circuit by using blocks and Mcode. DSP design Lab 5: Designing a MAC-Based FIR – Using a bottom-up Prerequisites approach, design a MAC-based bandpass FIR filter and verify Experience with the MATLAB and Simulink software through hardware co-simulation by using an ML505 board. Basic understanding of sampling theory Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Software Tools Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through Xilinx ISE® Foundation™ 10.1 software with the ISE Simulator hardware co-simulation by using the ML505 board. System Generator for DSP 10.1 Lab 7: System Generator and Project Navigator Integration – Platform Studio and Embedded Development Kit (EDK) 10.1 Learn how to embed two System Generator designs into a larger MATLAB with Simulink software R2007a or R2007b design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system. Lab 8: System Generator, Project Navigator, and Platform Studio After completing this comprehensive training, you will have the Integration – Learn how to embed two System Generator designs necessary skills to: into a larger design and how VHDL created by System Generator Describe the System Generator design flow for implementing can be incorporated into the simulation model of the overall DSP functions system. Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation Register Today List various low-level and high-level functional blocks available in System Generator Black Box Consulting delivers public and private courses in locations Identify the high-level blocks available for FIR and FFT designs throughout Australia and New Zealand Design a multiple-clock-based System Generator system . Embed two System Generator designs into a larger design For more information, such as our range of courses, current schedules, and other services including consulting and recruitment/training Course Outline packages, please use one of the contact methods below: Day 1 Black Box Consulting Introduction to System Generator PO Box 1147 Simulink Software Basics Stafford City Lab 1: Using the Simulink Software QLD 4053 Basic Xilinx Design Capture Tel: + 61 7 3137 0905 Fax: +61 7 39015586 Lab 2: Getting Started with Xilinx System Generator training@blackboxconsulting.com.au Signal Routing www.blackboxconsulting.com.au Lab 3: Signal Routing Implementing System Control Lab 4: Implementing System Control Day 2 Multi-Rate Systems Lab 5: Designing a MAC-Based FIR Filter Design Lab 6: Designing a FIR Filter Using the FIR Compiler Block Xilinx System Generator, Project Navigator, and Platform Studio Integration Lab 7: System Generator and Project Navigator Integration © 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 15 www.blackboxconsulting.com.au
  16. 16. Embedded Systems Development EMBD21000-7-ILT (v2.0) Course Specification Course Description Lab 5: Software Debugging System Simulation Xilinx FPGAs provide a new level of system design capabilities through Lab 6: Performing System Simulation soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced Lab Descriptions FPGA designers up to speed on developing embedded systems using Both the MicroBlaze and PowerPC 440 processors are supported in the Embedded Development Kit (EDK). The features and capabilities the labs. All labs target the ML507 board. of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on Lab 1: Hardware Construction with the Base System Builder – labs provide experience with the development, debugging, and Create an XPS project by using the Base System Builder to simulation of an embedded system. develop a basic hardware system and generate a series of netlists for the embedded design. Level / Duration – Intermediate / 2 days Lab 2: Software, Implementation, and Download – Complete the Price – AU$1400 + GST processes begun in Lab 1 by building the software libraries and Who Should Attend? – Engineers who are interested in developing applications, generating a bitstream file, merging the application embedded systems with the Xilinx MicroBlaze soft processor or IBM into the bitstream, and downloading to the ML507 board. PowerPC 440 core using the Embedded Development Kit and a Xilinx FPGA Lab 3: Adding IP to a Hardware Design – Learn to add IP from Prerequisites the many choices in the IP library. Use the GUI to add a general- purpose I/O module and access internal block RAM directly from FPGA design experience the MHS file. Completion of the Fundamentals of FPGA Design course or equivalent knowledge of Xilinx ISE® implementation tools Lab 4: Adding Custom IP to an Embedded System – Add custom Basic understanding of C programming IP to your design by using the Create and Import Peripheral Some HDL modeling experience wizard. Software Tools Lab 5: Software Debugging – Run the Software Development Kit Xilinx ISE® Foundation™ design tools 10.1 with the ISE (SDK) to produce a debug perspective, set breakpoints, and Simulator debug the application. Embedded Development Kit 10.1 with the Software Development Kit (SDK) Lab 6: Performing System Simulation – Use ISIM to perform Mentor Graphics ModelSim behavioral simulation of the completed design. After completing this comprehensive training, you will have the necessary skills to: Register Today Describe the various tools that encompass the Xilinx Embedded Development Kit (EDK) Black Box Consulting delivers public and private courses in locations throughout Australia and New Zealand Rapidly architect an embedded system containing a MicroBlaze . or IBM PowerPC processor and Xilinx-supplied CoreConnect bus For more information, such as our range of courses, current schedules, architecture IP by using the Base System Builder (BSB) and other services including consulting and recruitment/training Utilize the Eclipse-based Software Development Kit (SDK) to packages, please use one of the contact methods below: develop software applications and debug software Create and integrate your own IP into the EDK environment Black Box Consulting PO Box 1147 Stafford City Course Outline QLD 4053 Day 1 Tel: + 61 7 3137 0905 Fax: +61 7 39015586 EDK Overview Base System Builder training@blackboxconsulting.com.au Lab 1: Hardware Construction with the Base System Builder Software Development Using SDK Lab 2: Software, Implementation, and Download System Buses Hardware Design Hardware Design Using EDK Lab 3: Adding IP to a Hardware Design Day 2 Adding Your Own IP to the Embedded System Lab 4: Adding Custom IP to an Embedded System Software Debugging Linker Script Generator © 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. 16 www.blackboxconsulting.com.au

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