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Architecture of tms320 f2812

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This ppt contains Architecture of TMS320F2812. The important block of Architecture are separated and explained briefly.

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Architecture of tms320 f2812

  1. 1. Chapter 1 : Architecture Digital Signal Controller TMS320F2812Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  2. 2. C281x Block Diagram Program Bus Event Event Manager A Manager A Event Event Boot Boot Manager B Manager B Sectored Sectored ROM ROM RAM RAM Flash Flash 22 12-bit ADC 12-bit ADC A(18-0) 32 Watchdog Watchdog 32 D(15-0) 32 McBSP McBSP PIE 32-bit R-M-W R-M-W Interrupt CAN2.0B 32-bit 32x32 bit 32x32 bit Atomic CAN2.0B Auxiliary Auxiliary Atomic Manager Registers Multiplier Multiplier ALU Registers ALU SCI-A SCI-A 33 32 bit SCI-B SCI-B Realtime 32 bit Realtime Register Bus Timers Timers JTAG JTAG SPI SPI CPU Data Bus GPIO GPIOTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  3. 3.  MCU/DSP balancing code density C28x CPU & execution time.  Supports 32-bit instructions for Program Bus improved execution time;  Supports 16-bit instructions for improved code efficiency  32-bit fixed-point DSP PIE  32 x 32 bit fixed-point MAC 32-bit 32-bit R-M-W R-M-W Interrupt 32x32 bit 32x32 bit Atomic  Dual 16 x 16 single-cycle fixed-point Auxiliary Auxiliary Multiplier Atomic Manager Registers Multiplier ALU MAC (DMAC) Registers ALU 33  32-/64-bit saturation 32 bit  64/32 and 32/32 modulus division 32 bit Register Bus Timers Timers  Fast interrupt service time Realtime Realtime  Single cycle read-modify-write JTAG CPU JTAG instructions  Unique real-time debugging Data Bus capabilities  Upward code compatibilityTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  4. 4. C28x Multiplier and ALU / Shifters Program Bus 32 Data Bus XT (32) or T/TL 16/32 16 8/16/32 MULTIPLIER 32 32 x 32 or Shift R/L (0-16) Dual 16 x 16 P (32) or PH/PL 8/16 32 32 32 32 Shift R/L (0-16) 32 ALU (32) 32 ACC (32) AH (16) AL (16) AH.MSB AH.LSB AL.MSB AL.LSB • 32 Shift R/L (0-16) 32 Data BusTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  5. 5. C28x Pointer, DP and Memory Data Bus Program Bus 6 LSB from IR XAR0 DP (16) XAR1 XAR2 XAR3 32 22 XAR4 MUX XAR5 XAR6 XAR7 MUX ARAU Data Memory XARn → 32-bits ARn → 16-bitsTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  6. 6. C28x Internal Bus Structure Program Program Address Bus (22) PC Program Program-read Data Bus (32) Decoder (4M* 16) Data-read Address Bus (32) Data-read Data Bus (32) Data (4G * 16) Registers Execution Debug ARAU MPY32x32 Memory Real-Time SP R-M-W Emulation ALU DP @X Atomic & XT JTAG XAR0 ALU Test Standard to P ACC Engine Peripherals XAR7 Register Bus / Result Bus External Interfaces Data/Program-write Data Bus (32) Data-write Address Bus (32)Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  7. 7. C28x Atomic Read/Modify/Write Atomic Instructions Benefits: LOAD Simpler programming READ Smaller, faster code Registers CPU ALU / MPY Mem WRITE Uninterruptible (Atomic) STORE More efficient compiler Standard Load/Store Atomic Read/Modify/Write DINT AND *XAR2,#1234h MOV AL,*XAR2 AND AL,#1234h 2 words / 1 cycles MOV *XAR2,AL EINT 6 words / 6 cyclesTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  8. 8. C28x Pipeline F F D D R R X A 1 2 1 2 1 2 W 8-stage pipeline B F1 F2 D1 D2 R1 R2 X W C F1 F2 D1 D2 R1 R2 X W F1 F2 D1 D2 R1 R2 X W E & G Access D E F1 F2 D1 D2 R1 R2 X W same address F F1 F2 D1 D2 R1 R2 X W G F1 F2 D1 D2 R1 1 R2 X 2 X W R R W H F1 F2 D1 D2 2 R1 R2 1 X 2 X W D R R W F1: Instruction Address F2: Instruction Content Protected Pipeline D1: Decode Instruction  Order of results are as written in source D2: Resolve Operand Addr R1: Operand Address code R2: Get Operand  Programmer need not worry about the X: CPU doing “real” work W: store content to memory pipelineTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  9. 9. TMS320F2812 Memory Map Data | Program Data | Program 0x00 0000 MO SARAM (1K) 0x00 0400 M1 SARAM (1K) 0x00 0800 PF 0 (2K) reserved reserved 0x00 0D00 PIE vector (256) ENPIE=1 reserved XINT Zone 0 (8K) 0x00 2000 0x00 1000 reserved 0x00 6000 PF 2 (4K) reserved XINT Zone 1 (8K) 0x00 4000 0x00 7000 PF 1 (4K) reserved 0x00 8000 LO SARAM (4K) reserved 0x00 9000 L1 SARAM (4K) XINT Zone 2 (0.5M) 0x08 0000 0x00 A000 reserved XINT Zone 6 (0.5M) 0x10 0000 0x3D 7800 OTP (1K) 0x3D 7C00 reserved 0x18 0000 0x3D 8000 FLASH (128K) reserved 128-Bit Password 0x3F 8000 HO SARAM (8K) 0x3F A000 reserved XINT Zone 7 (16K) Boot ROM (4K) MP/MC=1 0x3F C000 0x3F F000 MP/MC=0 BROM vector (32) XINT Vector-RAM (32) CSM: LO, L1 0x3F FFC0 MP/MC=0 ENPIE=0 MP/MC=1 ENPIE=0 OTP, FLASHTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  10. 10. Code Security Module • Prevents reverse engineering and protects valuable intellectual property 0x00 8000 LO SARAM (4K) 0x00 9000 L1 SARAM (4K) 0x00 A000 reserved 0x3D 7800 OTP (1K) 0x3D 7C00 reserved 0x3D 8000 FLASH (128K) 128-Bit Password• 128-bit user defined password is stored in Flash• 128-bits = 2128 = 3.4 x 1038 possible passwords• To try 1 password every 2 cycles at 150 MHz, it would take at least 1.4 x 1023 years to try all possible combinations!Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  11. 11. C28x Fast Interrupt Response Manager  96 dedicated PIE vectors  No software decision making required  Direct access to RAM PIE module For 28x CPU Interrupt logic 96 interrupts vectors  Auto flags update INT1 to INT12 28x  Concurrent auto context IFR IER INTM CPU 96 12 interrupts save PIE Register Map Auto Context Save T ST0 69 = 8x21 st purr et nI l ar e hp r e P AH AL i PH PL AR1 (L) AR0 (L) DP ST1 DBSTAT IER PC(msw) PC(lsw)Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  12. 12. C28x / C24x Modes Mode Type Mode Bits Compiler OBJMODE AMODE Option C24x Mode 1 1 -v28 -m20 C28x Mode 1 0 -v28 Test Mode (default) 0 0 -v27 Reserved 0 1  C24x source-compatible mode:  Allows you to run C24x source code which has been reassembled using the C28x code generation tools (need new vectors)  C28x mode:  Can take advantage of all the C28x native featuresTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  13. 13. Reset – Bootloader Reset OBJMODE=0 AMODE=0 ENPIE=0 VMAP=1 Bootloader sets XMPNMC=0 OBJMODE = 1 (microcomputer mode) AMODE = 0 Reset vector fetched from Boot determined by boot ROM state of GPIO pins 0x3F FFC0 Execution Entry Point H0 SARAM Note: Details of the various boot options will be discussed in the Reset and Interrupts moduleTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  14. 14. Summary • High performance 32-bit DSP • 32 x 32 bit or dual 16 x 16 bit MAC • Atomic read-modify-write instructions • 8-stage fully protected pipeline • Fast interrupt response manager • 128Kw on-chip flash memory • Code security module (CSM) • Two event managers • 12-bit ADC module • 56 shared GPIO pins • Watchdog timer • Communications peripheralsTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt

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