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1 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
Evaluation of Multi-Core Platforms for Human Machine Interface (HMI)
(Coursework - 1A)
Osama Azim (Student ID: 023799), M.Sc. Electronics Communication and Computer Engineering,
The University of Nottingham - Malaysia Campus
Abstract - The x86 platform has been the preferred CPU for industrial automation and control applications. But
with the recent increase in demand for Human Machine Interface (HMI) capability, wherein these display and
control devices are now required to display high resolution graphics and must incorporate a wide range of
industrial communication and control protocols, along with reduced physical size and better thermal performance
requirements - highly integrated, multi-core System on Chip (SoCs) that incorporate high performance RISC or
enhanced x86 processors along with a selection of interface and peripheral busses can emerge as the single chip
solution to these requirements. Application of SoCs for industrial HMI can be made useful only if efficient
utilization of the SoC features are realized in hardware and software or the multi-core RISC based HMI system
development would be expensive and can ultimately result in a poor performing product.
I. Introduction
A. Application - Industrial Human Machine Interface
Also referred to as User Interface, Industrial Terminal Operator Panel or Thin Client - Human Machine Interface
(HMI) provides a means of controlling, monitoring, managing and/or visualizing device processes. For example an
operator panel which allows an industrial machine operator to interact with a machine in a graphical, visual way.
With controls and read-outs graphically displayed on the screen, the operator can use either external buttons or
the touch screen to control the machinery.
Figure 1: Siemens range of Simatic HMI products (Left), HMI/ Thin Client application in Industry Automation (Right)
[1]
Ranging from simple segmented displays to high-resolution LCD panels, HMIs can be located on the machine, in
battery-operated, portable handheld devices, and also in centralized control rooms. They are used in machine and
process control to connect the sensors, actuators and machines on the factory floor to I/O control and PLC
application systems.
2 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
An industrial HMI system’s usability is determined by its processing power, its ability to render complex and
reality- like screens, its fast response time to user input and its flexibility to handle various levels of operator
interactions. HMIs require dynamically changing graphics which, in turn, require a high- performance solution that
can achieve the 60 frame-per-second refresh rate that is required at the right resolution. They also have to
support multiple connectivity and communications protocols to communicate between the operator and various
machines and control system[4]
.
Many HMI units in the market today are x86 based, using processors from Intel and other manufacturers that
provide performance and flexibility. But with the increase in HMI use-case and software demanding features, 32
bit, highly integrated, multi-core RISC-based SoCs would soon become a more compelling solution. Increase in
market for multi-core RISC-based SoCs, such as ARM-cortex based, has resulted in a recent abundance of SoCs that
are capable of running robust industrial real time operating systems (RTOS) with rich graphical user interfaces
(GUI), such as QNX Neutrino RTOS, that meets the requirements of a HMI unit. Each manufacturer integrates
different functionality into their SoCs, making a straightforward comparison more difficult than when making an
x86 choice. In the x86 arena, there are nearly 20 options for microprocessor while in the RISC SoC arena the
number of choices exceeds 50 models. Each has a different mix of processor, I/O, and bus interfaces. In the
following coursework a comparative analysis of these x86 and RISC SoCs for HMI has been evaluated. Also, an
overview of multi-core based HMI system design considerations have been discussed.
B. Multi-core processors
Multi-core processor has changed the dynamics of the market and has enabled new innovative designs that
deliver high performance with an optimized power characteristic. Multi-core processors enables multithreading
and parallelism at hardware, rather than software/instruction, level[2]
. With the advent of improved chip
fabrication process technologies, an attractive option of single chip multi-processor solutions emerged - this
allowed for the best existing microprocessors to be duplicated on the same silicon die, thus doubling performance
at the same power. Since inter-core signals are quite confined and rare, multi-core processors also addresses the
issue of wire delays, hence providing greater advantage than a multi-processor solution like those implemented in
classic server architectures [3]
.
Figure 2: Multi-core solution by Intel
Multi-core processors have eventually been developed to include specialized cores for processing graphics, digital
signal processing algorithms, communication protocols, and other application specific solutions alike.
3 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
Despite its obvious hardware advantage, software development for computer systems design using multi-core
processors is not an evolutionary step. Operating systems need to make use of parallelism and applications must
be split into multiple threads to realize the benefits. This leads to comparing the certain advantages and
disadvantages of multi-processor system architecture:
Advantages:
 Multiple CPU cores on the same die allows the inter-CPU signals to travel a much shorter distance, thus
reducing the signal delay and distortion. More data and processing can be handled in a given time period
since the signals are shorter and with reduced loss.
 Implemented appropriately in software, as well as on hardware, multi-core processors improve the
response time while executing CPU intensive operations. This allows for true multi-tasking in many
modern computing applications such as multi-media processing on personal computers and mobile
phones while running background applications at the same instance.
 Being a single chip solution, multi-core processors provide a vastly reduced physical profile - consuming
much less circuit board space as compared to multi CPU solution. Also, these single chip solutions
consume lesser power in comparison.
 Multiple cores on same chip are designed to share resources, like L2 cache and Front Side Bus (FSB)
interface, reducing external hardware implementation. And, multi core design can make use of proven
CPU architectures, producing a product less prone to design error.
Disadvantages:
 Primary hurdle in implementing multi-core processor based systems is that of software development that
utilizes the advantages of these extra computing cores. In addition to operating system support, the ability
of multi-core processor to increase application performance depends on the programming of multiple
threads within applications. With the increase in popularity of both x86 based and ARM based multi-core
devices, most consumer applications today in general purpose computers and mobile devices support
multi-core architecture, its affect would also be observed in less commercial but regulated business and
industrial applications as computing requirements increase.
 Raw processing power is usually not the only constraint on system performance. Multiple processing cores
sharing the same system bus and memory bandwidth would have limited real world performance
advantage. For example, if a single core device is close to utilizing its memory bandwidth; implementing a
multi-core solution would give a mere 30% to 60% improvement margin.
 With regards to physical architecture, a single CPU design would make better use of silicon surface area.
Also, multi-core chip has lower production yield comparatively, and are more difficult to manage
thermally.
II. Application Considerations
Due to the various computing and input/output requirements, HMI can be considered as an high-performance
embedded application that can be realized using the modern advancements in multi-core SoC. To realize the
potential of multi-core SoCs in HMI, certain design consideration must be carefully examined - implementing an
4 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
unbalanced design that uses multi-core SoC would ultimately result in a product that's inferior in performance to
its present-day counterpart.
Figure 3: Generic HMI system block diagram
[4]
A. Modular design approach
Being an industry specific application, HMI has a small market volume. For cost consideration and to maintain a
common platform throughout the HMI offerings, a new hardware architecture for such a product would require
modular design approach, wherein a base system architecture would be combined with different market segment
modules/features to produce a multitude of HMI types. Selection of an appropriate balance between SoC
integration and system modularity is thus essential to the HMI platform optimization.
Figure 4: HMI modular design approach
If a highly integrated multi-core SoC with high-end features is selected for high end HMI - then adapting to a
different market segment or with upgrade to new product generation, the SoC and HMI system architecture
would require new hardware design, software and fabrication procedures. On the other end, if discrete chips for
CPU, I/O interface, memory, graphics and network are selected in order to develop the HMI with complete
flexibility, then, perhaps, the physical PCB board, software compatibility and component cost would become
unacceptable. The key to designing HMI system with multi-core SoC is to achieve an appropriate balance in SoC
5 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
integrated features while maintaining enough modularity to accommodate different market segments and enable
future modifications.
Table 1: HMI market segment and respective system requirement
HMI Type - Application function Processing/Hardware Requirements
High End - Functions as main process
control interface
 High resolution display
 2D/3D graphic rendering
 Running user interface application with batch control and monitoring features
 Running background operating system (embedded or real time)
 Support wide range of industrial communication protocols such as Profibus,
Profinet, CANbus, Fieldbus, etc
 Internet connectivity, Industry 4.0 (IoT) compatible
 Rugged hardware and robust software implementation
Mid End - Functions as local machine
control interface
 Medium/High resolution display
 2D graphic rendering
 Running user interface application
 Running background operating system (embedded)
 Support wide range of industrial communication protocols
 Industrial temperature and interference compatibility
Base / Entry level - Functions as operator
information unit / alarms and status display
 Low Resolution / dot-matrix display
 Basic graphics
 Support wide range of industrial communication protocols
Mobile / Portable Unit - Functions as
mobile, remote controller of machines and
devices
 Medium/High resolution display
 2D graphic rendering
 Wireless industrial communication protocol compatible
 Rugged and compact hardware, lean software
 Power efficient for battery operation
 Low processor thermal dissipation
B. Operating system consideration and making use of multi-core architecture
The software platform for HMI makes use of fail-safe Real Time Operating Systems (RTOS) and Graphical User
Interface (GUI). Considering that HMI is used in applications that are generally mission critical, these software
components must be highly reliable and hence the right software selection and implementation for HMI system is
essential.
Figure 5: Possible multi-core software implementation for HMI
6 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
Multi-core SoC would allow for two separate operating systems to run simultaneously on the same HMI, this
software architecture would add to the reliability and performance while improving on the flexibility of future
software modifications as well. At the back end, where time critical I/O and communication tasks need to be
handled, deploying a RTOS that performs such time critical tasks and provides true deterministic control would
improve HMI system reliability. A variety of such RTOSs are available commercially such as QNX Neutrino, Mentor
Graphics Nucleus, Windriver VxWorks, and a multitude of embedded Linux versions.
On the front-end of HMI, where the Graphical User Interface (GUI) would reside, Microsoft Windows CE can be
implemented for its real time control and its rich GUI features. The Windows CE GUI combined with .NET
framework would provide developers to create compelling, meaningful mimic diagrams for the factory/industry
operator.
C. Industrial bus connection flexibility: exploiting SoC integrated features
Industrial automation and control market defines multifarious options of bus protocols for communication and
control. These protocols were traditionally implemented on ASICs that had PCI interface for x86 based
architectures. With the advent of SoCs with inbuilt high bandwidth peripheral or local bus, an FPGA with
appropriate communication function could be attached directly to the SoC without the need for intermediate
bridge or interface standard.
The SoC peripheral or local bus also provides the flexibility needed to attach modular industrial communication
and control protocols ASICs, thus by attaching an appropriate ASIC for each market application provides the HMI
with modular structure that meets a wide variety of industrial market needs with maximum design reuse.
Integrating a industrial protocol onto a SoC would be quite restrictive, though, unless the industrial protocol
market is large, one such example is the common Profibus protocol for all Siemens HMIs.
D. Physical design improvements
Due to increased cost of the automated factory floor space and reduced power budgets, industrial equipment
needs to occupy smaller footprints on the factory floor while consuming less power. Using SoC based hardware for
HMIs improves upon both physical size and power requirement of the HMI hardware. The limit of this reduction
would be the size of the display panel.
From a thermal perspective, this physical size also depends on the use of large heat sinks or fans in HMI designs.
This, in turn imposes low power as an important requirement. A fan-less design with (at most) minimal convection
cooling would therefore be desired. Interestingly, most 32 bit RISC SoCs meet this requirement.
III. Market Options
Although SoC market today offers a wide selection of compelling solutions, only industry tested and certified
products could be considered for mission critical devices such as HMI.
7 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
A. Texas Instruments - Sitara™ AM57x Processors
The Sitara AM57x family of SoCs by Texas Instruments provides options of four different types of CPU cores that
include: 1.5 GHz ARM Cortex-A15, 750 MHz C66x DSP, 213 MHz Cortex-M4, and a TI programmable real-time unit
(PRU). It also integrates 2D and 3D graphic cores with 1080p video capability, and packs a wide variety of industry
specific communication and bus protocols.
Figure 6: Sitara AM57x family block diagram
[5]
The two ARM Cortex-A15 could be used for running the front-end computation intensive GUI tasks while the dual
core ARM Cortex-M4 could be ideal choice for running time-critical tasks and RTOS implementation. TIs offering of
quad core PRUs could be programmed to handle industrial communication protocols like Profibus, MODBUS or
EtherCAT. The SoC also integrates comprehensive I/O bus support such as PCIe, USB 3.0/2.0, SATA, I2
C.
The AM57x is featured in different, but pin-compatible, flavors. From the basic AM5716 with single core and
limited peripherals to the AM5728 that packs a powerful selection of cores and peripherals.
Figure 7: Sitara AM57x product range
[5]
8 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
This family of SoCs is supported by TIs Sitara SDK which is designed to enable code reuse from entire Sitara line of
products, and not restricted to the AM57x family. The entire Sitara line of offerings has an extensive third-party
support. RTOS, firmware and SDKs are available from various industrial software brands like Mentor Graphics,
QNX, Wind River, and Microsoft.
B. Freescale / NXP semiconductors - MAC57D5xx Multi-core ARM based MCU
The MAC57D5xx family is publicized by NXP semiconductors as an ultra-reliable multi-core ARM based MCU for
clusters and display. This product is based on the ARM Cortex-M processor (for real time) and the ARM cortex-A
processors (for application processing). It includes 2D graphic accelerator, TFT display driver and a capable I/O
processor.
Figure 8: MAC57D5xx family block diagram
[6]
The SoC integrates 2D Vivante GPU and the 2D Animation and Composition Engine (2D-ACE) by Freescale, which
reduces memory requirements for content creation by a significant degree. This SoC also comes with adequate
onboard memory and has inbuilt security features. NXP and third party software developers provide with
sufficient RTOS and GUI development platforms.
C. Intel - Atom E3800
The E3800 line of SoCs is built on Intel's x86 Silvermont architecture, and is offered in multiple product options
that can range up to four processing cores and are pin compatible throughout the range.
9 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
Figure 9: Intel Atom E3800 block diagram
[7]
Intel offers the E3800 in extended industrial temperature range, and is packed with integrated 3D graphics, Intel
HD audio, 64-bit memory controller and adequate options of I/O protocols.
Figure 10: Intel E3800 integration options
[8]
The entire Atom E3800 range is scalable, different versions can be used for specific market needs while keeping
the development platform intact, and is supported by the abundant x86 ecosystem - providing a wide range of
operating system and application development platforms.
10 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
IV. Comparative Analysis
Option
Comparison
TI - AM57x
Freescale/NXP -
MAC57D5xx
Intel - Atom E3800
(E3845)
Option in
advantage
Processor Cores
Dual Cortex-A15, Dual
Cortex-M5, 32-bit
ARM Cortex-A5,
Cortex-M4, Cortex-
M0+, 32-bit
Quad-core 64-bit
x86, 1.91 GHz
Atom E3800
Memory
2.5 MB L3 Ram, DDR3 -
up to 2 GB RAM
4 MB Flash, 2.3 MB
SRAM, 32-bit DDR2
RAM
2M L2 Cache, Up to
8 GB - DDR3 RAM
TI-AM57x
(for HMI
application)
Graphics Support
Multiple video Out, 2D,
3D Graphics, Dual Core
PowerVR GPU
OpenVG, 2D-ACE,
multiple LCD driver
Intel HD Graphics,
3D/2D rendering
TI-AM57x
Industrial I/O
protocol Options
Dual Programmable
Real time Unit (PRU),
Ethernet, Profibus,
MODBUS, CAN Bus, SPI,
I2
C, UART
Ethernet, Quad SPI, I2
C,
UART, Stepper motor
driver, 24 channel ADC
Legacy I/O - I2
C,
SPI, UART
TI-AM57x
Local peripheral Bus
Options
PCIe, USB, SATA
N/A (product is a
microcontroller)
PCIe, USB, SATA
Atom E3800,
TI-AM57x
Operating
Temperature
-40 o
C to 105 o
C -40 o
C to 105 o
C -40 o
C to 110 o
C Atom E3800
Cost USD 58 USD 29.00 USD 52.00 MAC57D5xx
Operating System
and GUI application
development
support
Extensive TI and 3rd
party RTOS and GUI
support
ARM, Green Hills SDK,
RTOS support
All x86 based OS -
Windows and Linux
variants
Atom E3800
Security
AES, SHA, RNG, DES
and 3DES
Error Correcting Codes,
Hardware Security
CSE2
Intel AES, and
other proprietary
accelerators
TI-AM57x
Quality and
Reliability
IEC standard
compatible
IEC standard
compatible
Designed for High
performance
embedded
applications
MAC57D5xx
Physical Size 23mm x 23mm 28mm x 28mm 25mm x 27mm TI-AM57x
11 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim
V. Discussion and Conclusion
If cost and development time were considered as primary selection parameters then developing a HMI using the
Freescale/NXP -MAC57D5xx MCU would provide with a very robust and reliable overall hardware and software
architecture, but such a design would result in a less flexible end product. Also, if complete hardware modularity
and current market compatibility were the focus of HMI system development, the Intel-Atom E3800 based
architecture would be optimal: in view of its x86 core that has a wide selection of compatible peripheral devices
and existing software development community.
For the proposed hardware and software application considerations of multi-core platforms for HMI system, the TI
- AM57x is preferred as the most viable family of SoCs that can be tailored to specific HMI market requirements.
Apart from must-have hardware requirements such as industrial compatibility, display drivers and onboard
programmable communication protocols, this SoC also provides with a mature software development platform
that can implement the two layer operating system architecture - isolated GUI front end and back end RTOS - with
relative ease. The entire line of SoC, from basic to advance features, is pin and software compatible - this
translates to reduced adaptation time whenever an alternate HMI feature offering needs to be developed.
Regardless of the SoC being selected, processors with four or more cores are readily available, with much higher
core count under development due to relatively easy hardware replication. As the number of processing cores and
integrated features of SoCs continue to evolve, efficient hardware and software can be designed only by making
effective use of these features. Also, with the availability of such powerful computing platforms, future HMIs could
incorporate complex features such as gesture recognition[9]
, voice command[10]
, biometric authentication and
reliable/secure internet connectivity (Industry-4.0) for the ever-changing but heavily regulated industrial
automation and control market.
References
[1] www2.advantech.com/eAutomation/Human-Machine-Interfaces/
[2] Pawel Gepner, "Multi-Core Processors: New Way to Achieve High System Performance", IEEE (PARELEC'06)
[3] Ronny Ronen, " Coming Challenges in Microarchitecture and Architecture", IEEE, VOL. 89, NO. 3, MARCH 2001
[4] Texas Instruments, Human Machine Interface Guide
[5] www.ti.com/lsds/ti/processors/sitara/arm_cortex-a15/am57x/overview.page
[6] http://cache.nxp.com/files/microcontrollers/doc/fact_sheet/MACDISMCUHALOFS.pdf
[7] http://linuxgizmos.com/intel-atom-e3800-socs-head-for-embedded-systems/
[8] Intel Atom E3800 Platform Brief
[9] Chao Nu, Gesture recognition for HMI of robot, IEEE 2003
[10] T.C. Luet, Human-Machine Interaction for Intelligent Robots using Natural Language, IEEE 1994

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H64CSA_1A_023799_Osama

  • 1. 1 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim Evaluation of Multi-Core Platforms for Human Machine Interface (HMI) (Coursework - 1A) Osama Azim (Student ID: 023799), M.Sc. Electronics Communication and Computer Engineering, The University of Nottingham - Malaysia Campus Abstract - The x86 platform has been the preferred CPU for industrial automation and control applications. But with the recent increase in demand for Human Machine Interface (HMI) capability, wherein these display and control devices are now required to display high resolution graphics and must incorporate a wide range of industrial communication and control protocols, along with reduced physical size and better thermal performance requirements - highly integrated, multi-core System on Chip (SoCs) that incorporate high performance RISC or enhanced x86 processors along with a selection of interface and peripheral busses can emerge as the single chip solution to these requirements. Application of SoCs for industrial HMI can be made useful only if efficient utilization of the SoC features are realized in hardware and software or the multi-core RISC based HMI system development would be expensive and can ultimately result in a poor performing product. I. Introduction A. Application - Industrial Human Machine Interface Also referred to as User Interface, Industrial Terminal Operator Panel or Thin Client - Human Machine Interface (HMI) provides a means of controlling, monitoring, managing and/or visualizing device processes. For example an operator panel which allows an industrial machine operator to interact with a machine in a graphical, visual way. With controls and read-outs graphically displayed on the screen, the operator can use either external buttons or the touch screen to control the machinery. Figure 1: Siemens range of Simatic HMI products (Left), HMI/ Thin Client application in Industry Automation (Right) [1] Ranging from simple segmented displays to high-resolution LCD panels, HMIs can be located on the machine, in battery-operated, portable handheld devices, and also in centralized control rooms. They are used in machine and process control to connect the sensors, actuators and machines on the factory floor to I/O control and PLC application systems.
  • 2. 2 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim An industrial HMI system’s usability is determined by its processing power, its ability to render complex and reality- like screens, its fast response time to user input and its flexibility to handle various levels of operator interactions. HMIs require dynamically changing graphics which, in turn, require a high- performance solution that can achieve the 60 frame-per-second refresh rate that is required at the right resolution. They also have to support multiple connectivity and communications protocols to communicate between the operator and various machines and control system[4] . Many HMI units in the market today are x86 based, using processors from Intel and other manufacturers that provide performance and flexibility. But with the increase in HMI use-case and software demanding features, 32 bit, highly integrated, multi-core RISC-based SoCs would soon become a more compelling solution. Increase in market for multi-core RISC-based SoCs, such as ARM-cortex based, has resulted in a recent abundance of SoCs that are capable of running robust industrial real time operating systems (RTOS) with rich graphical user interfaces (GUI), such as QNX Neutrino RTOS, that meets the requirements of a HMI unit. Each manufacturer integrates different functionality into their SoCs, making a straightforward comparison more difficult than when making an x86 choice. In the x86 arena, there are nearly 20 options for microprocessor while in the RISC SoC arena the number of choices exceeds 50 models. Each has a different mix of processor, I/O, and bus interfaces. In the following coursework a comparative analysis of these x86 and RISC SoCs for HMI has been evaluated. Also, an overview of multi-core based HMI system design considerations have been discussed. B. Multi-core processors Multi-core processor has changed the dynamics of the market and has enabled new innovative designs that deliver high performance with an optimized power characteristic. Multi-core processors enables multithreading and parallelism at hardware, rather than software/instruction, level[2] . With the advent of improved chip fabrication process technologies, an attractive option of single chip multi-processor solutions emerged - this allowed for the best existing microprocessors to be duplicated on the same silicon die, thus doubling performance at the same power. Since inter-core signals are quite confined and rare, multi-core processors also addresses the issue of wire delays, hence providing greater advantage than a multi-processor solution like those implemented in classic server architectures [3] . Figure 2: Multi-core solution by Intel Multi-core processors have eventually been developed to include specialized cores for processing graphics, digital signal processing algorithms, communication protocols, and other application specific solutions alike.
  • 3. 3 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim Despite its obvious hardware advantage, software development for computer systems design using multi-core processors is not an evolutionary step. Operating systems need to make use of parallelism and applications must be split into multiple threads to realize the benefits. This leads to comparing the certain advantages and disadvantages of multi-processor system architecture: Advantages:  Multiple CPU cores on the same die allows the inter-CPU signals to travel a much shorter distance, thus reducing the signal delay and distortion. More data and processing can be handled in a given time period since the signals are shorter and with reduced loss.  Implemented appropriately in software, as well as on hardware, multi-core processors improve the response time while executing CPU intensive operations. This allows for true multi-tasking in many modern computing applications such as multi-media processing on personal computers and mobile phones while running background applications at the same instance.  Being a single chip solution, multi-core processors provide a vastly reduced physical profile - consuming much less circuit board space as compared to multi CPU solution. Also, these single chip solutions consume lesser power in comparison.  Multiple cores on same chip are designed to share resources, like L2 cache and Front Side Bus (FSB) interface, reducing external hardware implementation. And, multi core design can make use of proven CPU architectures, producing a product less prone to design error. Disadvantages:  Primary hurdle in implementing multi-core processor based systems is that of software development that utilizes the advantages of these extra computing cores. In addition to operating system support, the ability of multi-core processor to increase application performance depends on the programming of multiple threads within applications. With the increase in popularity of both x86 based and ARM based multi-core devices, most consumer applications today in general purpose computers and mobile devices support multi-core architecture, its affect would also be observed in less commercial but regulated business and industrial applications as computing requirements increase.  Raw processing power is usually not the only constraint on system performance. Multiple processing cores sharing the same system bus and memory bandwidth would have limited real world performance advantage. For example, if a single core device is close to utilizing its memory bandwidth; implementing a multi-core solution would give a mere 30% to 60% improvement margin.  With regards to physical architecture, a single CPU design would make better use of silicon surface area. Also, multi-core chip has lower production yield comparatively, and are more difficult to manage thermally. II. Application Considerations Due to the various computing and input/output requirements, HMI can be considered as an high-performance embedded application that can be realized using the modern advancements in multi-core SoC. To realize the potential of multi-core SoCs in HMI, certain design consideration must be carefully examined - implementing an
  • 4. 4 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim unbalanced design that uses multi-core SoC would ultimately result in a product that's inferior in performance to its present-day counterpart. Figure 3: Generic HMI system block diagram [4] A. Modular design approach Being an industry specific application, HMI has a small market volume. For cost consideration and to maintain a common platform throughout the HMI offerings, a new hardware architecture for such a product would require modular design approach, wherein a base system architecture would be combined with different market segment modules/features to produce a multitude of HMI types. Selection of an appropriate balance between SoC integration and system modularity is thus essential to the HMI platform optimization. Figure 4: HMI modular design approach If a highly integrated multi-core SoC with high-end features is selected for high end HMI - then adapting to a different market segment or with upgrade to new product generation, the SoC and HMI system architecture would require new hardware design, software and fabrication procedures. On the other end, if discrete chips for CPU, I/O interface, memory, graphics and network are selected in order to develop the HMI with complete flexibility, then, perhaps, the physical PCB board, software compatibility and component cost would become unacceptable. The key to designing HMI system with multi-core SoC is to achieve an appropriate balance in SoC
  • 5. 5 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim integrated features while maintaining enough modularity to accommodate different market segments and enable future modifications. Table 1: HMI market segment and respective system requirement HMI Type - Application function Processing/Hardware Requirements High End - Functions as main process control interface  High resolution display  2D/3D graphic rendering  Running user interface application with batch control and monitoring features  Running background operating system (embedded or real time)  Support wide range of industrial communication protocols such as Profibus, Profinet, CANbus, Fieldbus, etc  Internet connectivity, Industry 4.0 (IoT) compatible  Rugged hardware and robust software implementation Mid End - Functions as local machine control interface  Medium/High resolution display  2D graphic rendering  Running user interface application  Running background operating system (embedded)  Support wide range of industrial communication protocols  Industrial temperature and interference compatibility Base / Entry level - Functions as operator information unit / alarms and status display  Low Resolution / dot-matrix display  Basic graphics  Support wide range of industrial communication protocols Mobile / Portable Unit - Functions as mobile, remote controller of machines and devices  Medium/High resolution display  2D graphic rendering  Wireless industrial communication protocol compatible  Rugged and compact hardware, lean software  Power efficient for battery operation  Low processor thermal dissipation B. Operating system consideration and making use of multi-core architecture The software platform for HMI makes use of fail-safe Real Time Operating Systems (RTOS) and Graphical User Interface (GUI). Considering that HMI is used in applications that are generally mission critical, these software components must be highly reliable and hence the right software selection and implementation for HMI system is essential. Figure 5: Possible multi-core software implementation for HMI
  • 6. 6 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim Multi-core SoC would allow for two separate operating systems to run simultaneously on the same HMI, this software architecture would add to the reliability and performance while improving on the flexibility of future software modifications as well. At the back end, where time critical I/O and communication tasks need to be handled, deploying a RTOS that performs such time critical tasks and provides true deterministic control would improve HMI system reliability. A variety of such RTOSs are available commercially such as QNX Neutrino, Mentor Graphics Nucleus, Windriver VxWorks, and a multitude of embedded Linux versions. On the front-end of HMI, where the Graphical User Interface (GUI) would reside, Microsoft Windows CE can be implemented for its real time control and its rich GUI features. The Windows CE GUI combined with .NET framework would provide developers to create compelling, meaningful mimic diagrams for the factory/industry operator. C. Industrial bus connection flexibility: exploiting SoC integrated features Industrial automation and control market defines multifarious options of bus protocols for communication and control. These protocols were traditionally implemented on ASICs that had PCI interface for x86 based architectures. With the advent of SoCs with inbuilt high bandwidth peripheral or local bus, an FPGA with appropriate communication function could be attached directly to the SoC without the need for intermediate bridge or interface standard. The SoC peripheral or local bus also provides the flexibility needed to attach modular industrial communication and control protocols ASICs, thus by attaching an appropriate ASIC for each market application provides the HMI with modular structure that meets a wide variety of industrial market needs with maximum design reuse. Integrating a industrial protocol onto a SoC would be quite restrictive, though, unless the industrial protocol market is large, one such example is the common Profibus protocol for all Siemens HMIs. D. Physical design improvements Due to increased cost of the automated factory floor space and reduced power budgets, industrial equipment needs to occupy smaller footprints on the factory floor while consuming less power. Using SoC based hardware for HMIs improves upon both physical size and power requirement of the HMI hardware. The limit of this reduction would be the size of the display panel. From a thermal perspective, this physical size also depends on the use of large heat sinks or fans in HMI designs. This, in turn imposes low power as an important requirement. A fan-less design with (at most) minimal convection cooling would therefore be desired. Interestingly, most 32 bit RISC SoCs meet this requirement. III. Market Options Although SoC market today offers a wide selection of compelling solutions, only industry tested and certified products could be considered for mission critical devices such as HMI.
  • 7. 7 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim A. Texas Instruments - Sitara™ AM57x Processors The Sitara AM57x family of SoCs by Texas Instruments provides options of four different types of CPU cores that include: 1.5 GHz ARM Cortex-A15, 750 MHz C66x DSP, 213 MHz Cortex-M4, and a TI programmable real-time unit (PRU). It also integrates 2D and 3D graphic cores with 1080p video capability, and packs a wide variety of industry specific communication and bus protocols. Figure 6: Sitara AM57x family block diagram [5] The two ARM Cortex-A15 could be used for running the front-end computation intensive GUI tasks while the dual core ARM Cortex-M4 could be ideal choice for running time-critical tasks and RTOS implementation. TIs offering of quad core PRUs could be programmed to handle industrial communication protocols like Profibus, MODBUS or EtherCAT. The SoC also integrates comprehensive I/O bus support such as PCIe, USB 3.0/2.0, SATA, I2 C. The AM57x is featured in different, but pin-compatible, flavors. From the basic AM5716 with single core and limited peripherals to the AM5728 that packs a powerful selection of cores and peripherals. Figure 7: Sitara AM57x product range [5]
  • 8. 8 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim This family of SoCs is supported by TIs Sitara SDK which is designed to enable code reuse from entire Sitara line of products, and not restricted to the AM57x family. The entire Sitara line of offerings has an extensive third-party support. RTOS, firmware and SDKs are available from various industrial software brands like Mentor Graphics, QNX, Wind River, and Microsoft. B. Freescale / NXP semiconductors - MAC57D5xx Multi-core ARM based MCU The MAC57D5xx family is publicized by NXP semiconductors as an ultra-reliable multi-core ARM based MCU for clusters and display. This product is based on the ARM Cortex-M processor (for real time) and the ARM cortex-A processors (for application processing). It includes 2D graphic accelerator, TFT display driver and a capable I/O processor. Figure 8: MAC57D5xx family block diagram [6] The SoC integrates 2D Vivante GPU and the 2D Animation and Composition Engine (2D-ACE) by Freescale, which reduces memory requirements for content creation by a significant degree. This SoC also comes with adequate onboard memory and has inbuilt security features. NXP and third party software developers provide with sufficient RTOS and GUI development platforms. C. Intel - Atom E3800 The E3800 line of SoCs is built on Intel's x86 Silvermont architecture, and is offered in multiple product options that can range up to four processing cores and are pin compatible throughout the range.
  • 9. 9 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim Figure 9: Intel Atom E3800 block diagram [7] Intel offers the E3800 in extended industrial temperature range, and is packed with integrated 3D graphics, Intel HD audio, 64-bit memory controller and adequate options of I/O protocols. Figure 10: Intel E3800 integration options [8] The entire Atom E3800 range is scalable, different versions can be used for specific market needs while keeping the development platform intact, and is supported by the abundant x86 ecosystem - providing a wide range of operating system and application development platforms.
  • 10. 10 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim IV. Comparative Analysis Option Comparison TI - AM57x Freescale/NXP - MAC57D5xx Intel - Atom E3800 (E3845) Option in advantage Processor Cores Dual Cortex-A15, Dual Cortex-M5, 32-bit ARM Cortex-A5, Cortex-M4, Cortex- M0+, 32-bit Quad-core 64-bit x86, 1.91 GHz Atom E3800 Memory 2.5 MB L3 Ram, DDR3 - up to 2 GB RAM 4 MB Flash, 2.3 MB SRAM, 32-bit DDR2 RAM 2M L2 Cache, Up to 8 GB - DDR3 RAM TI-AM57x (for HMI application) Graphics Support Multiple video Out, 2D, 3D Graphics, Dual Core PowerVR GPU OpenVG, 2D-ACE, multiple LCD driver Intel HD Graphics, 3D/2D rendering TI-AM57x Industrial I/O protocol Options Dual Programmable Real time Unit (PRU), Ethernet, Profibus, MODBUS, CAN Bus, SPI, I2 C, UART Ethernet, Quad SPI, I2 C, UART, Stepper motor driver, 24 channel ADC Legacy I/O - I2 C, SPI, UART TI-AM57x Local peripheral Bus Options PCIe, USB, SATA N/A (product is a microcontroller) PCIe, USB, SATA Atom E3800, TI-AM57x Operating Temperature -40 o C to 105 o C -40 o C to 105 o C -40 o C to 110 o C Atom E3800 Cost USD 58 USD 29.00 USD 52.00 MAC57D5xx Operating System and GUI application development support Extensive TI and 3rd party RTOS and GUI support ARM, Green Hills SDK, RTOS support All x86 based OS - Windows and Linux variants Atom E3800 Security AES, SHA, RNG, DES and 3DES Error Correcting Codes, Hardware Security CSE2 Intel AES, and other proprietary accelerators TI-AM57x Quality and Reliability IEC standard compatible IEC standard compatible Designed for High performance embedded applications MAC57D5xx Physical Size 23mm x 23mm 28mm x 28mm 25mm x 27mm TI-AM57x
  • 11. 11 | H63CSA - Hardware Accelerated Computing - Coursework 1A Osama Azim V. Discussion and Conclusion If cost and development time were considered as primary selection parameters then developing a HMI using the Freescale/NXP -MAC57D5xx MCU would provide with a very robust and reliable overall hardware and software architecture, but such a design would result in a less flexible end product. Also, if complete hardware modularity and current market compatibility were the focus of HMI system development, the Intel-Atom E3800 based architecture would be optimal: in view of its x86 core that has a wide selection of compatible peripheral devices and existing software development community. For the proposed hardware and software application considerations of multi-core platforms for HMI system, the TI - AM57x is preferred as the most viable family of SoCs that can be tailored to specific HMI market requirements. Apart from must-have hardware requirements such as industrial compatibility, display drivers and onboard programmable communication protocols, this SoC also provides with a mature software development platform that can implement the two layer operating system architecture - isolated GUI front end and back end RTOS - with relative ease. The entire line of SoC, from basic to advance features, is pin and software compatible - this translates to reduced adaptation time whenever an alternate HMI feature offering needs to be developed. Regardless of the SoC being selected, processors with four or more cores are readily available, with much higher core count under development due to relatively easy hardware replication. As the number of processing cores and integrated features of SoCs continue to evolve, efficient hardware and software can be designed only by making effective use of these features. Also, with the availability of such powerful computing platforms, future HMIs could incorporate complex features such as gesture recognition[9] , voice command[10] , biometric authentication and reliable/secure internet connectivity (Industry-4.0) for the ever-changing but heavily regulated industrial automation and control market. References [1] www2.advantech.com/eAutomation/Human-Machine-Interfaces/ [2] Pawel Gepner, "Multi-Core Processors: New Way to Achieve High System Performance", IEEE (PARELEC'06) [3] Ronny Ronen, " Coming Challenges in Microarchitecture and Architecture", IEEE, VOL. 89, NO. 3, MARCH 2001 [4] Texas Instruments, Human Machine Interface Guide [5] www.ti.com/lsds/ti/processors/sitara/arm_cortex-a15/am57x/overview.page [6] http://cache.nxp.com/files/microcontrollers/doc/fact_sheet/MACDISMCUHALOFS.pdf [7] http://linuxgizmos.com/intel-atom-e3800-socs-head-for-embedded-systems/ [8] Intel Atom E3800 Platform Brief [9] Chao Nu, Gesture recognition for HMI of robot, IEEE 2003 [10] T.C. Luet, Human-Machine Interaction for Intelligent Robots using Natural Language, IEEE 1994