Introduction to XMOS Software Defined Silicon Technology


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Presentation on the Software Defined Silicon Technology by XMOS, presented at the TinkerSoc OpenMic Session #3, 07/12/2009

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  • XMOS was founded in July 2005 by Ali Dixon (then final-year student at the University of Bristol), James Foster (former CEO of Oxford Semiconductor), Noel Hurley (formerly at ARM Holdings), David May (former chief architect of Inmos), and Hitesh Mehta (Acacia Capital Partners). It received seed funding from the University of Bristol enterprise fund, and Wyvern seed fund (formerly the SulisSeedcorn fund).
  • The XMOS architecture combines a number of processing cores (called XCores) each with its own memory and I/O system, on a single chip. The processing cores are general-purpose in the sense that they can execute languages such as C; they also have direct support for concurrent processing (multi-threading), communication and I/O. A high-performance switch supports communication between the processors, and inter-chip Links are provided so that systems can easily be constructed from multiple chips. Any thread can communicate with any other thread in the system using single-cycle communication instructions. The system switches can efficiently route short packets or streamed data. The XMOS architecture makes it practical to use software to perform many functions that traditionally have been implemented in hardware, for example interfaces and I/O controllers. Both input and output operations can be timed to a local clock or an externally provided clock. The architecture is both multi-threaded and event-driven. Threads can be used to define independent tasks; the event mechanism enables fast and controlled responses to a multitude of signals. The architecture is designed to support any programming language, such as C and C++. The full benefits of the instruction set may require extensions to standard languages, libraries, or the use of assembly language. We have designed XC, a version of C that supports I/O, multi-core and precision timing.
  • An XCore processor runs multiple real-time threads simultaneously. Each thread has access to a set of general purpose registers, gets a guaranteed share of the processing power, and executes a program using common RISC-style instructions. Each thread can execute simple computational code, DSP code, control software (taking logic decisions, or executing a state machine) or handle I/O operations.
  • Processors and fast I/O haven’t mixed well
  • Introduction to XMOS Software Defined Silicon Technology

    1. 1. Introduction to XMOS‘Software Defined Silicon’Technology<br />Omer Kilic |<br />
    2. 2. Disclosure/Disclaimer<br />I am the University Rep for XMOS but I am not employed by them.<br />I have been playing with the architecture for a while now but I am not an expert.<br />If I sound fuzzy have a look at the official documentation for clarification!<br />This is not a marketing talk <br />
    3. 3. Agenda<br />XMOS?<br />Software Defined Silicon Architecture<br />Programming Flow<br />Kits/Silicon Devices Available<br />‘XMOSLinkers’<br />Web Links<br />
    4. 4. XMOS?<br />Fabless Semiconductor Company<br />Founded in 2005, based in Bristol<br />Academic Roots<br />Remember the Transputers?<br />Some concepts based on the Transputer architecture<br />
    5. 5. Software Defined Silicon<br />A number of multi threaded, general purpose cores with individual I/O and memory systems<br />Highly flexible ‘XLink’ interconnect between threads, cores & chips<br />Event driven execution<br />Pretty clever I/O Ports<br />“Custom hardware from a software design flow”<br />
    6. 6. XCore<br /><ul><li>Multi-threaded architecture
    7. 7. 8 threads per core
    8. 8. Up to 400 MIPS
    9. 9. Event driven processing
    10. 10. Mixed 16/32bit Instruction Set
    11. 11. Up to 64 I/O ports per core
    12. 12. Mix of 32,16,8,4,1 bit ports
    13. 13. Integrated memory
    14. 14. 64K Bytes SRAM per tile
    15. 15. 8K Bytes OTP per tile
    16. 16. XLinks for connectivity</li></li></ul><li>XLink<br /><ul><li>Deterministic communications switch fabric
    17. 17. Connects threads, cores & chips
    18. 18. Thread communication abstracted to software
    19. 19. Automatically synchronises threads</li></li></ul><li>I/O Features<br />
    20. 20. Event Driven?<br />Comparing Interrupts/Events:<br />Event Sources: Pins & Ports, Timers & Synchronisers, XLinks<br />
    21. 21. Programming Flow<br /><ul><li>Standard ‘embedded’ software flow
    22. 22. Cross platform development environment based on Eclipse
    23. 23. Debugger/Simulator available
    24. 24. Open Source!</li></ul><br />
    25. 25. ‘XC’ Language<br />Simplifies concurrency and real-time control tasks<br />Support for:<br />I/O with timing<br />Communication<br />Events<br />Multiple threads<br />Does not support floating point arithmetic and pointers.<br />
    26. 26. ‘XC’ Language : An example<br />#include &lt;platform.h&gt; <br />onstdcore [0] : out port tx = XS1_PORT_1A ; <br />onstdcore [0] : in port rx = XS1_PORT_1B ; <br />onstdcore [1] : out port lcdData = XS1_PORT_32A ; <br />onstdcore [2] : in port keys = XS1_PORT_8B ; <br />intmain (void) { <br />par {<br />onstdcore [0] : uartTX (tx); <br />onstdcore [0] : uartRX (rx); <br />onstdcore [1] : lcdDrive (lcdData); <br />onstdcore [2] : kbListen (keys); <br /> } <br />} <br />From:<br />
    27. 27. Silicon Devices<br />
    28. 28. Kits<br />Official kits:<br />Comparison of available dev kits:<br />
    29. 29.<br />The official XMOS community<br />Repository of open-source designs<br />Discussion Forum<br />Blogs, Classifieds, etc.<br />
    30. 30. Web Links<br /><br /><br /><br /><br /><br /><br /><br /><br />
    31. 31. Thanks for listening!Any questions?<br />Further questions/comments to please.<br />