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Introduction to XMOS‘Software Defined Silicon’Technology Omer Kilic | omer@tinkersoc.org
Disclosure/Disclaimer I am the University Rep for XMOS but I am not employed by them. I have been playing with the architecture for a while now but I am not an expert. If I sound fuzzy have a look at  the official documentation for clarification! This is not a marketing talk 
Agenda XMOS? Software Defined Silicon Architecture Programming Flow Kits/Silicon Devices Available ‘XMOSLinkers’ Web Links
XMOS? Fabless Semiconductor Company Founded in 2005, based in Bristol Academic Roots Remember the Transputers? Some concepts based on the Transputer architecture
Software Defined Silicon A number of multi threaded, general purpose cores with individual I/O and memory systems Highly flexible ‘XLink’ interconnect between threads, cores & chips Event driven execution Pretty clever I/O Ports “Custom hardware from a software design flow”
XCore ,[object Object]
8 threads per core
 Up to 400 MIPS
 Event driven processing
Mixed 16/32bit Instruction Set
Up to 64 I/O ports per core
 Mix of 32,16,8,4,1 bit ports
 Integrated memory
 64K Bytes SRAM per tile
 8K Bytes OTP per tile
XLinks for connectivity,[object Object]
 Connects threads, cores & chips

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Introduction to XMOS Software Defined Silicon Technology

Editor's Notes

  1. XMOS was founded in July 2005 by Ali Dixon (then final-year student at the University of Bristol), James Foster (former CEO of Oxford Semiconductor), Noel Hurley (formerly at ARM Holdings), David May (former chief architect of Inmos), and Hitesh Mehta (Acacia Capital Partners). It received seed funding from the University of Bristol enterprise fund, and Wyvern seed fund (formerly the SulisSeedcorn fund).
  2. The XMOS architecture combines a number of processing cores (called XCores) each with its own memory and I/O system, on a single chip. The processing cores are general-purpose in the sense that they can execute languages such as C; they also have direct support for concurrent processing (multi-threading), communication and I/O. A high-performance switch supports communication between the processors, and inter-chip Links are provided so that systems can easily be constructed from multiple chips. Any thread can communicate with any other thread in the system using single-cycle communication instructions. The system switches can efficiently route short packets or streamed data. The XMOS architecture makes it practical to use software to perform many functions that traditionally have been implemented in hardware, for example interfaces and I/O controllers. Both input and output operations can be timed to a local clock or an externally provided clock. The architecture is both multi-threaded and event-driven. Threads can be used to define independent tasks; the event mechanism enables fast and controlled responses to a multitude of signals. The architecture is designed to support any programming language, such as C and C++. The full benefits of the instruction set may require extensions to standard languages, libraries, or the use of assembly language. We have designed XC, a version of C that supports I/O, multi-core and precision timing.
  3. An XCore processor runs multiple real-time threads simultaneously. Each thread has access to a set of general purpose registers, gets a guaranteed share of the processing power, and executes a program using common RISC-style instructions. Each thread can execute simple computational code, DSP code, control software (taking logic decisions, or executing a state machine) or handle I/O operations.
  4. Processors and fast I/O haven’t mixed well