A Quick Introduction to Programmable Logic


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Slides from my talk on Programmable Logic at the Open Source Hardware Users Group Meeting #9 in London on the 21st of April 2011.

More details about the event at: http://oshug.org/event/9

An overview of the slides at:

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  • Logic theory – From Philosophy to MathsAn Investigation of the Laws of Thought by George Boole
  • But he is also credited with founding both digital computer and digital circuit design theory in 1937, when, as a 21-year-old master's student at MIT, he wrote a thesis demonstrating that electrical application of Boolean algebra could construct and resolve any logical, numerical relationship. It has been claimed that this was the most important master's thesis of all time.[2]
  • …is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. Application-specific standard products (ASSPs) are intermediate between ASICs and industry standard integrated circuits like the 7400 or the 4000 series.As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (system-on-a-chip). Designers of digital ASICs use ahardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.Field-programmable gate arrays (FPGA) are the modern-day technology for building a breadboard or prototype from standard parts; programmable logic blocks and programmable interconnects allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design even in production. The non-recurring engineering cost of an ASIC can run into the millions of dollars.
  • Note that the use of the word "programmable" does not indicate that all PLAs are field-programmable; in fact many are mask-programmed during manufacture in the same manner as a mask ROM. 
  • A macrocell array is an approach to the design and manufacture of ASICs. Essentially, it is a small step up from the otherwise similar gate array, but rather than being a prefabricated array of simple logic gates, the macrocell array is a prefabricated array of higher-level logic functions such as flip-flops, ALU functions,registers, and the like.
  • A Field-programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the first commercially viable field programmable gate array in 1985 – the XC2064.[9] The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market.[10] The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-input lookup tables (LUTs).[11]
  • The Configurable Logic Blocks (CLBs) are the main logic resources for implementingsequential as well as combinatorial circuits. Each CLB element is connected to a switchmatrix for access to the general routing matrixA CLB element contains a pair of slices.
  • The Configurable Logic Blocks (CLBs) are the main logic resources for implementingsequential as well as combinatorial circuits. Each CLB element is connected to a switchmatrix for access to the general routing matrixA CLB element contains a pair of slices.
  • The Configurable Logic Blocks (CLBs) are the main logic resources for implementingsequential as well as combinatorial circuits. Each CLB element is connected to a switchmatrix for access to the general routing matrixIn general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE, Slice etc). A typical cell consists of a 4-input Lookup table (LUT), a Full adder (FA) and a D-type flip-flop, as shown below. The LUTs are in this figure split into two 3-input LUTs.
  • HDLs represent a level of abstraction that can isolate the designers from the details of the hardware implementation.  Schematic based entry gives designers much more visibility into the hardware. It is the better choice for those who are hardware oriented. Another method but rarely used is state-machines. It is the better choice for the designers who think the design as a series of states.
  • Synthesis. This stage involves conversion of an HDL description to a so-called netlist which is basically a formally written digital circuit schematic. Synthesis is performed by a special software called synthesizer. For an HDL code that is correctly written and simulated, synthesis shouldn't be any problem. However, synthesis can reveal some problems and potential errors that can't be found using behavioral simulation, so, an FPGA engineer should pay attention to warnings produced by the synthesizer.
  • mplementation. A synthesizer-generated netlist is mapped onto particular device's internal structure. The main phase of the implementation stage is place and route or layout, which allocates FPGA resources (such as logic cells and connection wires). Then these configuration data are written to a special file by a program called bitstream generator.
  • A Quick Introduction to Programmable Logic

    1. 1. AQuick Introduction toProgrammable Logic.Omer Kilic – OSHUG #9, April 2011<br />
    2. 2. http://omer.kilic.name<br />
    3. 3. Agenda<br />History of Digital Electronics<br />Programmable Logic Devices<br />Design ‘flow’ for FPGAs<br />State of the Art / Challenges<br />Q & A<br />
    4. 4. 1854<br />AND<br />NOT<br />OR<br />George Boole<br />Inventor of Boolean Logic<br />An Investigation of the Laws of Thought<br />http://www.gutenberg.org/ebooks/15114<br />
    5. 5. Logic Functions<br />
    6. 6. 1937<br />Claude Shannon<br />Designs first electrical application utilising Boolean Theory<br />A Symbolic Analysis of Relay and Switching Circuits<br />http://dspace.mit.edu/handle/1721.1/11173<br />
    7. 7. 1947: Point-contact transistor invented at Bell Labs<br />1954: Texas Instruments introduces first commercial silicon transistor<br />
    8. 8. http://www.flickr.com/photos/andy_squirrel/4701062117<br />
    9. 9. Logic Families<br />
    10. 10. 7400 Series (TTL)<br />
    11. 11.
    12. 12. http://www.flickr.com/photos/dnny/1435262760/<br />
    13. 13.
    14. 14. Application-Specific Integrated Circuit<br />
    15. 15. Programmable Logic Array<br />
    16. 16. Programmable Array Logic<br />
    17. 17. Complex Programmable Logic Device<br />‘Macrocells’<br />EEPROM/Flash Non-volatile configuration<br />Instant-on<br />Not-OTP!<br />Coarse Grain<br />
    18. 18. Field Programmable Gate Array<br />‘Field Programmable’<br />Based on blocks of logic and a flexible interconnect matrix<br />Fine Grain<br />Used in: digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal detection,…<br />
    19. 19. Programmable Logic Vendors<br />
    20. 20.
    21. 21.
    22. 22.
    23. 23.
    24. 24. Configurable Logic Block<br />
    25. 25. Configurable Logic Block<br />Slice<br />Slice<br />Slice<br />Slice<br />
    26. 26. Configurable Logic Block<br />Slice<br />Slice<br />Logic Cell<br />Logic Cell<br />Logic Cell<br />Logic Cell<br />Slice<br />Slice<br />Logic Cell<br />Logic Cell<br />Logic Cell<br />Logic Cell<br />
    27. 27.
    28. 28.
    29. 29. Aside: Software Compilation<br />main.s<br /> .file "main.c"<br /> .section .rodata<br />.LC0:<br /> .string "hello, world"<br /> .text<br />.globl main<br /> .type main, @function<br />main:<br />leal 4(%esp), %ecx<br />andl $-16, %esp<br />pushl -4(%ecx)<br />pushl %ebp<br />movl %esp, %ebp<br />pushl %ecx<br />subl $4, %esp<br />movl $.LC0, (%esp)<br /> call puts<br />movl $0, %eax<br />addl $4, %esp<br />popl %ecx<br />popl %ebp<br />leal -4(%ecx), %esp<br /> ret<br /> .size main, .-main<br /> .section .note.GNU-stack,"",@progbits<br />main.c<br />#include <stdio.h><br />int main(void)<br />{<br />printf("hello, worldn");<br />return 0;<br />}<br />gcc -S main.c<br />http://en.wikipedia.org/wiki/X86_instruction_listings<br />
    30. 30. FPGA Design Flow<br />Behavioural Simulation<br />Post-Synthesis Simulation<br />Post-PAR Simulation<br />
    31. 31. Design Entry<br />Schematic Based<br />Hardware Description Languages<br />VHDL<br />Verilog<br />Constraints definition<br />‘Floorplan’<br />Timing<br />Power<br />“Which HDL do you prefer?”<br />“The one I'm not using this week”<br />Janick Bergeron<br />
    32. 32. VHDL vs Verilog<br />Example: 8-bit shift-left register with a positive-edge clock, serial in, and serial out<br />VHDL<br />library ieee;use ieee.std_logic_1164.all;entity shift is port(C, SI : in std_logic; SO : out std_logic);end shift;<br />architecture Behav of shift is signal tmp: std_logic_vector(7 downto 0);beginprocess (C)begin if (C'event and C='1') then for i in 0 to 6 looptmp(i+1) = tmp(i); end loop;<br />tmp(0) = SI; end if;end process;<br />SO = tmp(7);end Behav;<br />Verilog<br />module shift (C, SI, SO);<br />input C,SI;output SO;reg [7:0] tmp; always @(posedge C) begintmp= tmp<< 1;tmp[0] = SI; end<br /> assign SO = tmp[7];endmodule<br />From: http://www.xilinx.com/itp/3_1i/data/fise/xst/chap02/xst02007.htm<br />
    33. 33. VHDL vs Verilog<br />“Verilog was written by a bunch of hardware guys who knew nothing about software.  We beat on it 'till you could do software with it.”<br />“VHDL was written by a bunch of software guys who knew nothing about hardware.  We beat on it 'till you could do hardware with it.”<br />http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4<br />
    34. 34. Synthesis<br />Check Syntax<br />Analyse/Optimise hierarchy of design<br />Translate Schematic/HDL code into a ‘netlist’<br />
    35. 35. Implementation<br />Translate<br />Merges netlists/constraints<br />(Functional Simulation)<br />Map<br />Maps design onto physical FPGA blocks (CLB, IOB, etc.)<br />(Static Timing Analysis)<br />Place & Route (PAR)<br />Places ‘mapped’ blocks onto FPGA fabric and arranges connections between them <br />(Static Timing Analysis)<br />Produces ‘bitstream’<br />
    36. 36. Programming<br />Most FPGAs are SRAM based<br />Volatile configuration<br />External configuration memory<br />JTAG<br />
    37. 37. Simulation!<br />
    38. 38. FPGA Design Flow<br />Behavioural Simulation<br />Post-Synthesis Simulation<br />Post-PAR Simulation<br />
    39. 39. Xilinx Microblaze ‘Softcore’ Processor<br />
    40. 40. Xilinx Microblaze ‘Softcore’ Processor<br />
    41. 41. Xilinx ML605<br />http://bit.ly/xilinx-ml605<br />
    42. 42. Avnet Spartan-6 LX9 MicroBoard<br />http://bit.ly/avnet-s6-microboard <br />Digilent Basys2<br />http://bit.ly/digilent-basys2<br />
    43. 43. Enterpoint Merrick1<br />100+1 FPGAs<br />10 x 10 array of Spartan™-3A DSP XC3SD3400A and a Virtex™-5 XC5VLX30T<br />“A standard Merrick1 can be rented at GBP £2000, USD $3000, per month subject to minimum rental period and deposit. Additional costs for shipping, insurance and taxes may also apply.”<br />http://bit.ly/enterpoint-merrick1 <br />
    44. 44. State of the Art<br />
    45. 45. State of the Art<br />
    46. 46. State of the Art<br />
    47. 47. Challenges<br />Toolchains are complicated, costly and (mostly) closed source<br />Lack of standardised frameworks or workflows<br />Advances in device capabilities not fully utilised by applications<br />
    48. 48. Thanks! Any Questions?<br />