Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our User Agreement and Privacy Policy.

Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our Privacy Policy and User Agreement for details.

Like this presentation? Why not share!

- TinkerSoc Electronics 101 by Omer Kilic 1222 views
- Introduction to XMOS Software Defin... by Omer Kilic 2116 views
- From Breadboard to Finished Product by Omer Kilic 2938 views
- Erlang Embedded — Concurrent Blinke... by Omer Kilic 1372 views
- concurrency.cc OSHUG #3 by Omer Kilic 1713 views
- BURO Arduino Workshop by Omer Kilic 6555 views

4,521 views

Published on

More details about the event at: http://oshug.org/event/9

An overview of the slides at:

http://omer.me/2011/05/a-quick-introduction-to-programmable-logic

Published in:
Technology

No Downloads

Total views

4,521

On SlideShare

0

From Embeds

0

Number of Embeds

1,386

Shares

0

Downloads

0

Comments

0

Likes

2

No embeds

No notes for slide

- 1. AQuick Introduction toProgrammable Logic.Omer Kilic – OSHUG #9, April 2011<br />
- 2. http://omer.kilic.name<br />
- 3. Agenda<br />History of Digital Electronics<br />Programmable Logic Devices<br />Design ‘flow’ for FPGAs<br />State of the Art / Challenges<br />Q & A<br />
- 4. 1854<br />AND<br />NOT<br />OR<br />George Boole<br />Inventor of Boolean Logic<br />An Investigation of the Laws of Thought<br />http://www.gutenberg.org/ebooks/15114<br />
- 5. Logic Functions<br />
- 6. 1937<br />Claude Shannon<br />Designs first electrical application utilising Boolean Theory<br />A Symbolic Analysis of Relay and Switching Circuits<br />http://dspace.mit.edu/handle/1721.1/11173<br />
- 7. 1947: Point-contact transistor invented at Bell Labs<br />1954: Texas Instruments introduces first commercial silicon transistor<br />
- 8. http://www.flickr.com/photos/andy_squirrel/4701062117<br />
- 9. Logic Families<br />
- 10. 7400 Series (TTL)<br />
- 11.
- 12. http://www.flickr.com/photos/dnny/1435262760/<br />
- 13.
- 14. Application-Specific Integrated Circuit<br />
- 15. Programmable Logic Array<br />
- 16. Programmable Array Logic<br />
- 17. Complex Programmable Logic Device<br />‘Macrocells’<br />EEPROM/Flash Non-volatile configuration<br />Instant-on<br />Not-OTP!<br />Coarse Grain<br />
- 18. Field Programmable Gate Array<br />‘Field Programmable’<br />Based on blocks of logic and a flexible interconnect matrix<br />Fine Grain<br />Used in: digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal detection,…<br />
- 19. Programmable Logic Vendors<br />
- 20.
- 21.
- 22.
- 23.
- 24. Configurable Logic Block<br />
- 25. Configurable Logic Block<br />Slice<br />Slice<br />Slice<br />Slice<br />
- 26. Configurable Logic Block<br />Slice<br />Slice<br />Logic Cell<br />Logic Cell<br />Logic Cell<br />Logic Cell<br />Slice<br />Slice<br />Logic Cell<br />Logic Cell<br />Logic Cell<br />Logic Cell<br />
- 27.
- 28.
- 29. Aside: Software Compilation<br />main.s<br /> .file "main.c"<br /> .section .rodata<br />.LC0:<br /> .string "hello, world"<br /> .text<br />.globl main<br /> .type main, @function<br />main:<br />leal 4(%esp), %ecx<br />andl $-16, %esp<br />pushl -4(%ecx)<br />pushl %ebp<br />movl %esp, %ebp<br />pushl %ecx<br />subl $4, %esp<br />movl $.LC0, (%esp)<br /> call puts<br />movl $0, %eax<br />addl $4, %esp<br />popl %ecx<br />popl %ebp<br />leal -4(%ecx), %esp<br /> ret<br /> .size main, .-main<br /> .section .note.GNU-stack,"",@progbits<br />main.c<br />#include <stdio.h><br />int main(void)<br />{<br />printf("hello, worldn");<br />return 0;<br />}<br />gcc -S main.c<br />http://en.wikipedia.org/wiki/X86_instruction_listings<br />
- 30. FPGA Design Flow<br />Behavioural Simulation<br />Post-Synthesis Simulation<br />Post-PAR Simulation<br />
- 31. Design Entry<br />Schematic Based<br />Hardware Description Languages<br />VHDL<br />Verilog<br />Constraints definition<br />‘Floorplan’<br />Timing<br />Power<br />“Which HDL do you prefer?”<br />“The one I'm not using this week”<br />Janick Bergeron<br />
- 32. VHDL vs Verilog<br />Example: 8-bit shift-left register with a positive-edge clock, serial in, and serial out<br />VHDL<br />library ieee;use ieee.std_logic_1164.all;entity shift is port(C, SI : in std_logic; SO : out std_logic);end shift;<br />architecture Behav of shift is signal tmp: std_logic_vector(7 downto 0);beginprocess (C)begin if (C'event and C='1') then for i in 0 to 6 looptmp(i+1) = tmp(i); end loop;<br />tmp(0) = SI; end if;end process;<br />SO = tmp(7);end Behav;<br />Verilog<br />module shift (C, SI, SO);<br />input C,SI;output SO;reg [7:0] tmp; always @(posedge C) begintmp= tmp<< 1;tmp[0] = SI; end<br /> assign SO = tmp[7];endmodule<br />From: http://www.xilinx.com/itp/3_1i/data/fise/xst/chap02/xst02007.htm<br />
- 33. VHDL vs Verilog<br />“Verilog was written by a bunch of hardware guys who knew nothing about software. We beat on it 'till you could do software with it.”<br />“VHDL was written by a bunch of software guys who knew nothing about hardware. We beat on it 'till you could do hardware with it.”<br />http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4<br />
- 34. Synthesis<br />Check Syntax<br />Analyse/Optimise hierarchy of design<br />Translate Schematic/HDL code into a ‘netlist’<br />
- 35. Implementation<br />Translate<br />Merges netlists/constraints<br />(Functional Simulation)<br />Map<br />Maps design onto physical FPGA blocks (CLB, IOB, etc.)<br />(Static Timing Analysis)<br />Place & Route (PAR)<br />Places ‘mapped’ blocks onto FPGA fabric and arranges connections between them <br />(Static Timing Analysis)<br />Produces ‘bitstream’<br />
- 36. Programming<br />Most FPGAs are SRAM based<br />Volatile configuration<br />External configuration memory<br />JTAG<br />
- 37. Simulation!<br />
- 38. FPGA Design Flow<br />Behavioural Simulation<br />Post-Synthesis Simulation<br />Post-PAR Simulation<br />
- 39. Xilinx Microblaze ‘Softcore’ Processor<br />
- 40. Xilinx Microblaze ‘Softcore’ Processor<br />
- 41. Xilinx ML605<br />http://bit.ly/xilinx-ml605<br />
- 42. Avnet Spartan-6 LX9 MicroBoard<br />http://bit.ly/avnet-s6-microboard <br />Digilent Basys2<br />http://bit.ly/digilent-basys2<br />
- 43. Enterpoint Merrick1<br />100+1 FPGAs<br />10 x 10 array of Spartan™-3A DSP XC3SD3400A and a Virtex™-5 XC5VLX30T<br />“A standard Merrick1 can be rented at GBP £2000, USD $3000, per month subject to minimum rental period and deposit. Additional costs for shipping, insurance and taxes may also apply.”<br />http://bit.ly/enterpoint-merrick1 <br />
- 44. State of the Art<br />
- 45. State of the Art<br />
- 46. State of the Art<br />
- 47. Challenges<br />Toolchains are complicated, costly and (mostly) closed source<br />Lack of standardised frameworks or workflows<br />Advances in device capabilities not fully utilised by applications<br />
- 48. Thanks! Any Questions?<br />

No public clipboards found for this slide

×
### Save the most important slides with Clipping

Clipping is a handy way to collect and organize the most important slides from a presentation. You can keep your great finds in clipboards organized around topics.

Be the first to comment