Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.

Hosseini sv07

367 views

Published on

  • Be the first to comment

  • Be the first to like this

Hosseini sv07

  1. 1. Simulation Versus ? Anoosh Hosseini Cisco Systems Simulation-DV- external © 2007 Cisco Systems, Inc. All rights reserved. 1
  2. 2. Introduction Simulation versus acceleration, versus emulation Which solution is right for me? When we use simulation Simulation-DV- External © 2007 Cisco Systems, Inc. All rights reserved. 2
  3. 3. Simulation, Acceleration, Emulation Not going to argue between the three The right solution is a factor of: –Complexity and size of the chip/system –The goals, the amount of time allocated, Time to Market, and potential impact –Module or full chip centric DV plan –Is the focus DV or SW dev –The methodology, process, and procedures of a company –The vision, leadership, and engineers who are going to execute the plan Simulation-DV- External © 2007 Cisco Systems, Inc. All rights reserved. 3
  4. 4. Acceleration (Circa ~1999) Acceleration resulted in 5-10X speed up give testbench overhead. Developed light weight TB to leverage HW for 200X (over Sparc 450Mhz) Cycle based simulation resulted in 50X Built a C model of the XR 12000 fabric wired to N Lincards. One LC accelerated RTL, the rest C models of LC. Simulation-DV- External © 2007 Cisco Systems, Inc. All rights reserved. 4
  5. 5. Distributed Simulation (Circa ~2002) 10 ASIC CRS-1 linecard simulation Globally developed, mixed DV languages, libraries Decided on developing both a distributed simulation library, and low overhead Perl based DV environment ASIC’s used as building blocks compiled as independent entities Virtual schematic wired up chips at runtime Scaled to 32 ASIC fabric simulation No emulation/acceleration solution Leveraged large compute farm Simulation-DV- External © 2007 Cisco Systems, Inc. All rights reserved. 5
  6. 6. Emulation (Circa 2005-6) 25M gate ASIC Emulated with home brew FPGA solution 250Khz Found bugs after 4 hour run SW bringup tested on emulation platform Simulation-DV- External © 2007 Cisco Systems, Inc. All rights reserved. 6
  7. 7. SOC Simulation for SW Development ( Circa 2003-2007) New High End SOC Packet Processor No full chip RTL for 2-3 years Need to Develop SW in the absence of Silicon & RTL Developed a C model of the SOC Predicted performance within 6-10% Control plane + data plane integration in simulation Live BGP 1M route updates, VoIP etc Embedded SW run on RTL and Silicon flawlessly Product enters system test at record pace Simulation-DV- External © 2007 Cisco Systems, Inc. All rights reserved. 7
  8. 8. SOC Simulation As Basis For Embedded SW Dev Need to support tens to hundreds of developers Proprietary tools vs open sources: License fees add up! IDE for managing and visualizing simulation Advanced tracing and analysis Sophisticated checks and assertion Advanced temporal breakpoints Single step forwards and backwards in time Simulation-DV- External © 2007 Cisco Systems, Inc. All rights reserved. 8
  9. 9. Future Possibilities For SOC simulation Break the problem down to two components: processor simulation, custom logic simulation Processor Simulation: Fast ISS technology, Instruction Set emulation/translation Custom logic: Traditional simulation, FPGA’s Simulation-DV- External © 2007 Cisco Systems, Inc. All rights reserved. 9
  10. 10. Simulation-DV- External © 2007 Cisco Systems, Inc. All rights reserved. 10

×