Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.
Design Verification: The Past,
       Present and Future

       Sean Smith, Juniper Networks, RTP,
       NC




1 | Copy...
Agenda

   Introduction to Sean & Juniper
   A little background on DV Past
   An overview of where DV is today?
   Wh...
Who is Juniper at a Glance?
                Snapshot:
                     Founded: 1996
                    NASDAQ: JNPR
...
DV: The Past

    DV has been a tremendously evolutionary field
        –   As recent as 15 years ago
        –   There w...
DV: The Present

  Wow! DV has Evolved!
      –   Lots of research on DV including DV centric conference
      –   Dozens...
DV: The Future

  How are we going to deal with capacity?
      – Current simulation techniques are running out steam?
  ...
Dynamic Simulation Challenges

  Closing Coverage…

                               out_0           4 x 4 Switch          ...
Closing coverage continued…

  Constrained random tests are generally not
   coverage aware so they generate a lot of dup...
Formal Targeted ROI and Applications
Formal Application                     Examples                    Resource    Risk  ...
DV: The Future

   But are there bigger looming challenges?
   We need to step back and consider the big picture.
      ...
Reuse Starts with Specification

   IP blocks need consistent specification format
       – Ensure quick and easy integra...
SPIRIT and SystemRDL
        SystemRDL is a language for specifying register
         architectures and implimentations.
...
Traditional CSR Flow
                Requirement Change                                Requirement change due to area,
   ...
Challenges with Traditional CSR Flow

   Resource intensive
       – Multiple engineers creating same/similar content
   ...
Register Compiler Architecture
                SystemRDL™




                                          Register Compiler
...
www.spiritconsortium.org

   Simple high level syntax defines registers
       // This register is a inline register defi...
Defining reusable components in SystemRDL

         field intr_field_f {
            desc = “Some Status Field";
         ...
www.systemrdl.org
        reg vc_pkt_count_r {
           count_field_f vc_count[29:0]=0x0;
           field { desc="VC is...
Automate ESL/TLM Creation
          Auto Generated
          c/c++ Headers,
          Classes, & HAL


                   ...
Closing Thoughts…..

     Verification has come a long way and has a
      promising future.
     Speed and Capacity are...
Juniper advantage

   The POWER of




             Architecture                      Operating System   Open Network
    ...
Upcoming SlideShare
Loading in …5
×

Design verification--the-past-present-and-future

753 views

Published on

  • Be the first to comment

  • Be the first to like this

Design verification--the-past-present-and-future

  1. 1. Design Verification: The Past, Present and Future Sean Smith, Juniper Networks, RTP, NC 1 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  2. 2. Agenda Introduction to Sean & Juniper A little background on DV Past An overview of where DV is today? Where is DV Going? Summary and Q&A 2 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  3. 3. Who is Juniper at a Glance? Snapshot: Founded: 1996 NASDAQ: JNPR Headquarters: Sunnyvale, CA SECTION Employees: 7,000 TITLE WITH IMAGEemployees in offices in 47 countries. Customer Profile: We serve the top 100 global service providers more than 30,000 enterprises, as well as hundreds of government 3 | Copyright © 2009 Juniperagencies and Networks, Inc. | www.juniper.net
  4. 4. DV: The Past  DV has been a tremendously evolutionary field – As recent as 15 years ago – There was little research on DV – There were no published texts on DV (until 2000) – A large void compared to logic design. – Considered by many to be the n00b job  Common DV Techniques – Visual inspection – Diff the golden log files – Directed self checking tests – Code coverage was in its infancy – C++ was a common choice in the high end 4 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  5. 5. DV: The Present  Wow! DV has Evolved! – Lots of research on DV including DV centric conference – Dozens of published texts – Still a void compared to logic design but narrowing – Not necessarily a newbie job but there is a delta in compensation & respect  Common DV Techniques – Self checking constrained random – Objective metrics for measuring completeness – Static verification has become almost mainstream – SystemVerilog provided the unification 5 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  6. 6. DV: The Future  How are we going to deal with capacity? – Current simulation techniques are running out steam? – Emulation? – Formal?  How can we be smarter about reaching our verification goals?  Are the traditional problems where we should be focusing our energy? 6 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  7. 7. Dynamic Simulation Challenges  Closing Coverage… out_0 4 x 4 Switch in_0 out_1 in_1 Routing Table mac_addr dst_port out_2 0x0100 0 in_2 0x0200 1 0x0300 2 out_3 0x0400 3 in_3 Packet Format data crc dst src len 0x0102030 0x9bdbc90 0x100 0x500 2 4 0 7 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  8. 8. Closing coverage continued…  Constrained random tests are generally not coverage aware so they generate a lot of duplicate transactions….  New Approaches are emerging to try and automate coverage specification and closure! – Graph and Genetic based algorithms for stimulus and coverage generation. – Algorithms to mutate stimulus code – Context aware simulators – Formal Verification 8 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  9. 9. Formal Targeted ROI and Applications Formal Application Examples Resource Risk TTM ROI Area Impact Impact Impact Architectural Communications Cache coherency verification and bus  High High High architecture RTL design and Designer X-propagation  High debug sandbox detection High High Register Connectivity check verification Proofs of critical Packet integrity Error correction functionality/ Multi-processor Protocol  High  High  High  High Verification coherence certification Flow control Token leakage Regression test Verification of low- Power Power shutoff  High power modes architecture isolation cells Medium Clock gating Post-silicon debug Root cause bugs Validate fixes  High  High Varies 9 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  10. 10. DV: The Future  But are there bigger looming challenges?  We need to step back and consider the big picture. – The goal of verification is deliver a quality product to market in a timely fashion. – There is an increasing software component of silicon and systems we build. – There is also the redundancy of pre versus post silicon verification.  The future of DV is much broader than the current focus! 10 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  11. 11. Reuse Starts with Specification  IP blocks need consistent specification format – Ensure quick and easy integration into SOC level reference manual, users guides, and programmers guides – Modular & consistent document structure, formatting, look and feel are key – Need to minimize hand editing when going from block to SOC  Standards like IP-Xact and SystemRDL from the SPIRIT Consortium are driving the future. 11 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  12. 12. SPIRIT and SystemRDL  SystemRDL is a language for specifying register architectures and implimentations.  SPIRIT Consortium has accepted the donation of SystemRDL on May 21, 2007  On May 18th 2009, The SystemRDL 1.0 standard was released. http://www.spiritconsortium.org/ 12 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  13. 13. Traditional CSR Flow Requirement Change Requirement change due to area, From Marketing Timing, or Physical Design Concern Architect Writes Specification B B u u g g Verification Eng Design Eng Software Eng F Codes HVL Codes HDL Codes C F o o u u n n d DV Verifies Design d Software Eng Writes Firmware Or Device Driver DONE?? Hope All Match! 13 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  14. 14. Challenges with Traditional CSR Flow  Resource intensive – Multiple engineers creating same/similar content – Very tedious and time consuming work  Difficult to manage changes in architecture  Doesn’t enable common look and feel  Manual nature of process lends to low quality – Specification != HDL != HVL – Manual test cases creation for DV – Doc updates postponed due to pain factor Low Reuse + Tedious Work = Low Quality/Productivity 14 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  15. 15. Register Compiler Architecture SystemRDL™ Register Compiler RTL C Code HVL Code Unformatted for Synthesis for Firmware for Verification Documentation Word Style Processor Sheet Hardware Software Functional Generated Design Development Verification Documentation 15 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  16. 16. www.spiritconsortium.org  Simple high level syntax defines registers // This register is a inline register definition. // It defines a simple ID register. A flip-flop is implemented // reg chip_id_r { name = "This chip part number and revision #"; desc = "This register contains the part # and revision # for XYZ ASIC"; field { hw = rw; // This combination of attr creates a flip flop sw = r; desc = "This field represents the chips part number"; } part_num[28] = 28'h12_34_56_7; }; 16 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  17. 17. Defining reusable components in SystemRDL field intr_field_f { desc = “Some Status Field"; level intr; // Level Sensitive Interrupt }; field count_field_f { // Anonymous Generic Counter. hw = w; sw = rw; rclr; counter; desc = "Number of certain packet type seen"; }; Here we define a couple of field types that we will use on the next slide. This can be used to create templates to ensure common architecture and reuse. 17 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  18. 18. www.systemrdl.org reg vc_pkt_count_r { count_field_f vc_count[29:0]=0x0; field { desc="VC is Active"; } active; intr_field_f cntr_overflow=0; cntr_overflow->next = vc_count->overflow; }; addrmap some_register_map { chip_id_r chip_id @0x0110; external vc_pkt_count_r vc_pkt_count[256] @0x200 +=0x10; // External Interface }; // End some_register_map 18 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  19. 19. Automate ESL/TLM Creation Auto Generated c/c++ Headers, Classes, & HAL SystemC TLM Model of DUT DUT Test Bench or Firmware Behavioral Model Automatically Generated or Of System TLM of CSRs Device Driver DUT Functionality Or Complete RTOS 19 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  20. 20. Closing Thoughts…..  Verification has come a long way and has a promising future.  Speed and Capacity are becoming real bottlenecks for traditional approaches.  More focus needs to be placed on co-verification and verification portability.  SystemRDL and IP-Xact are pragmatic languages that provide benefits to many aspects of ASIC/SOC creation. 20 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net
  21. 21. Juniper advantage The POWER of Architecture Operating System Open Network ••• 21 | Copyright © 2009 Juniper Networks, Inc. | www.juniper.net

×