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Microprocessor & Microcontroller
Microprocessor & Microcontroller -
- I
I
T.E
T.E Sem
Sem V (Rev)
V (Rev)
Prof. Nitin Ahire
Prof. Nitin Ahire
XIE, Mahim
XIE, Mahim
1-Aug-13 Prof.Nitin Ahire 2
Overview of Microprocessor
Overview of Microprocessor
MICROPROCESSOR
( C P U )
MEMORY
INPUT OUTPUT (I/O)
DEVICE
1-Aug-13 Prof.Nitin Ahire 3
Functional block Diagram
Functional block Diagram
• INPUT OUTPUT (I/O) DEVICE
I/P :Key board, scanner, card reader etc
O/P : Display, printer LED etc
• MEMORY
RAM, ROM
• MICROPROCESSOR
Central Processor Unit ( CPU ) include
ALU, Timing & control unit for synchronizations
1-Aug-13 Prof.Nitin Ahire 4
Number System
Number System
• Decimal number system (DNS)(10)
0,1,2 ……,9,10
• Binary number system(2)
0,1,10,11,100
• Hexadecimal number system (16)
0,1,2,…..,9,A,B,C,D,E,F,10,11
• Advantages of Hex No over BCD No system
(1111 1111)2 (FF)16 (255)10
1-Aug-13 Prof.Nitin Ahire 5
Review for Logic Devices
Review for Logic Devices
• Tri State Devices :
3 States are logic 1, logic 0 & high
impedances state ( Z )
Enable Enable
Active high Active Low
6
Tri
Tri-
-State Buffers
State Buffers
• An important circuit element that is used
extensively in memory.
• This buffer is a logic circuit that has three
states:
– Logic 0, logic1, and high impedance.
– When this circuit is in high impedance mode it
looks as if it is disconnected from the output
completely.
The Output is Low The Output is High High Impedance
7
The Tri
The Tri-
-State Buffer
State Buffer
• This circuit has two inputs and one output.
– The first input behaves like the normal
input for the circuit.
– The second input is an “enable”.
• If it is set high, the output follows the proper
circuit behaviour.
• If it is set low, the output looks like a wire
connected to nothing.
Input Output
Enable
Input Output
Enable
OR
1-Aug-13 Prof.Nitin Ahire 8
Review for Logic Devices
Review for Logic Devices
• Buffer e.g. 74LS244(unidirectionl) & 74LS245(Bidirection)
• Buffer is a logic CKT that amplifies the current or
power
• It has one I/P line and one O/P line
• The logic level of O/P is the same as that of the
I/P
• Basically used as to increase the driving capacity
of logic CKT
simple buffer Active low buffer
1-Aug-13 Prof.Nitin Ahire 9
Introduction to 8085
Introduction to 8085
• CPU built into a single semiconductor
chip is called as microprocessor
• The microprocessor work as a brain
of a computer
• It consist of ALU, registers and
control unit
• The microprocessor are usually
characterized by speed, word length
(bit), architecture, instruction set Etc
1-Aug-13 Prof.Nitin Ahire 10
8085 Features
8085 Features
• 8085 is a 8-bit processor
• Frequency of operation
a) 8085 --- 3Mhz
b) 8085-2 --- 5Mhz
c) 8085-1 --- 6Mhz
• 8085 has 16 bit address bus to access
memory
• 8 bit address bus to access I/O
location
1-Aug-13 Prof.Nitin Ahire 11
8085 Features
8085 Features
• It required only single +5V power supply
• 8085 has following registers
a) 8 bit accumulator
b) six 8- bit general purpose registers
c) 8-bit flag register
d) 16 –bit PC and SP
• It has 5 hardware and 8 software interrupt
• 8085 required 6 Mhz crystal
• It can transmit and receive serial data
1-Aug-13 Prof.Nitin Ahire 12
8085
PIN DIG
1 X1 40 VCC
2 X2 39 HOLD
3 RESET OUT 38 HLDA
4 SOD 37 CLOCK (OUT)
5 SID 36 RESET IN
6 TRAP 35 READY
7 RST 7.5 34IO/M
8 RST 6.5 33 S1
9 RST 5.5 32 RD
10 INTR 31 WR
11 INTA 30 ALE
12 AD0 29 S0
13 AD1 28 A15
14 AD2 27 A14
15 AD3 26 A13
16 AD4 25 A12
17 AD5 24 A11
18 AD6 23 A10
19 AD7 22 A9
20 VSS 21 A8
8085
(3 MHz )
X1 Crystal 6 MHz
X2
PIN DIG
8085
1-Aug-13 Prof.Nitin Ahire 13
Serial I/O
Serial I/O
ports
ports
8085
Functional
Pin Diagram
A8-A15
AD0- AD7
RST 6.5
RST 6.5
RST 5.5
RST 5.5
INTR
INTR
RESET IN
RESET IN
READY
READY
INTA
INTA
HOLD
HOLD
HLDA
HLDA
SOD
SOD
TRAP
TRAP
RST 7.5
RST 7.5
ALE
ALE
X1
X1
S0
S0
S1
S1
IO/M
IO/M
RESET OUT
RESET OUT
CLK OUT
CLK OUT
WR
WR
RD
RD
Externally
Externally
Initiated
Initiated
Signal
Signal
External
External
Acknowledge
Acknowledge
Signal
Signal
H.O.A.B
H.O.A.B
Multiplexed
Multiplexed
A/D Bus
A/D Bus
Control &
Control &
Status
Status
Signal
Signal
SID
SID
X2
X2 vcc
vcc CLK CKT &
CLK CKT &
P.S.
P.S.
1-Aug-13 Prof.Nitin Ahire 14
Interrupt control Serial I/O Control
W 8 Z 8
D E
C
B
H L
SP 16
PC 16
Internal latch
F/F 5
ALU
8
Temp. Reg
Accumulator 8 I.R. 8
Inst.
Decoder
&
M/C
Encoder
Timing and control unit Add. Buffer
A/D. Buffer
8 bit Internal BUS
AD0-AD7
A15-A8
SID SOD
INTR
INTA RST 7.5 to 5.5 TRAP
X1
X2
READY
WR RD ALE S0 S1 IO/M HLDA HOLD
CLK OUT RESET IN RESET OUT
P.S
+5V
GND
DECODRE
MUX
1-Aug-13 Prof.Nitin Ahire 15
Interrupt control Serial I/O Control
W 8 Z 8
D E
C
B
H L
SP 16
PC 16
Internal latch
F/F 5
ALU
8
Temp. Reg
8
Accumulator 8 I.R. 8
Inst.
Decoder
&
M/C
Encoder
Timing and control unit Add. Buffer
A/D. Buffer
8 bit Internal BUS
AD0-AD7
A15-A8
SID SOD
INTR
INTA RST 7.5 to 5.5 TRAP
X1
X2
READY
WR RD ALE S0 S1 IO/M HLDA HOLD
CLK OUT RESET IN RESET OUT
P.S
+5V
GND
DECODRE
MUX
1-Aug-13 Prof.Nitin Ahire 16
Registers
Registers
• The register contains a set of
binary storage cells/Flip Flop
• 6 general purpose 8 bit Reg.
B,C,D,E,H&L (or can be used as
pair of 16 bit reg. like BC,DE,HL)
• W & Z (Temp reg.)
• 16 bit Reg are PC And SP
• 8 bit flag register
B C
D E
H L
SP
PC
W Z
A F
1-Aug-13 Prof.Nitin Ahire 17
Interrupts
Interrupts
• Hardware interrupt
Trap (Non Mask able) (vectored)
RST 7.5(Mask able) (vectored)
RST 6.5 (Mask able) (vectored)
RST 5.5(Mask able) (vectored)
INTR (Mask able) (Non vectored)
• Software interrupt RST 0 to RST 7
All are vectored interrupt
1-Aug-13 Prof.Nitin Ahire 18
Interrupts
Interrupts
• 8085 has 5 hardware interrupts
8 software interrupts
• All software interrupt are vectored
• Out of 5 hardware interrupt 4 are
vector and 1 is non vector
also 4 are maskable and one is non
mask able
1-Aug-13 Prof.Nitin Ahire 19
Flags Register ( 8 bit )
Flags Register ( 8 bit )
D7 D6 D5 D4 D3 D2 D1 D0
• S –sign flag (for signed number)
if D7=1 the number in accumulator
will be –ve number
D7=0 the number in accumulator
will be +ve number
• Z – zero flag if D6=1The zero flag is set if the result
in accumulator is zero
S Z -- AC - P -- C
1-Aug-13 Prof.Nitin Ahire 20
Flags Register ( 8 bit )
Flags Register ( 8 bit )
D7 D6 D5 D4 D3 D2 D1 D0
AC – Auxiliary carry in the arithmetic operation, when the carry
is generated digit D3 and passed on digit D4 the AC flag is set
P – parity flag after an arithmetic and logical operation, if the
result has even number of ones the flag is set if it has odd
numbers of ones, the flag is reset
CY – Carry flag if an arithmetic operation results in carry, the
carry flag is set otherwise it is reset. The carry flag also serves as
a barrow flag for subtraction
S Z AC P C
1-Aug-13 Prof.Nitin Ahire 21
Subtraction process in 8085
Subtraction process in 8085
• 1 : find 1’s complement of the subtrahend
• 2 : find 2’s complement of the subtrahend
• 3 : Adds 2’s complement of the
subtrahend to the minuend
• 4 : complements the CY flag.
These steps are invisible to the user, only
the result is available to the user.
For unsigned number if CY is reset the result
is positive and if CY is set the result is
negative(2’complement)
1-Aug-13 Prof.Nitin Ahire 22
Sign flag (used only for sign No.)
Sign flag (used only for sign No.)
• Sign flag: This flag is used with signed
numbers in the arithmetic operation.
With sign number, bit D7 is reserved
for indicating the sign and the
remaining 7 bit are used to represent
the magnitude of a number
• Sign flag is irrelevant for unsigned
number
1-Aug-13 Prof.Nitin Ahire 23
D
D –
– F/F (Latch)
F/F (Latch)
D F/F
Latch
clk
I/P
O/P
clk
I/P
Q
Q
1-Aug-13 Prof.Nitin Ahire 24
De multiplexing Of AD0
De multiplexing Of AD0-
-AD7
AD7
8085
Latch
AD0-AD7
D0-D7
ALE
A0-A7
A8-A15
IO/M
De multiplexing (AD0
De multiplexing (AD0-
-AD7)
AD7)
1-Aug-13 Prof.Nitin Ahire 25
1-Aug-13 Prof.Nitin Ahire 26
De multiplexing Of AD0
De multiplexing Of AD0-
-AD7
AD7
8085
Latch
AD0-AD7
D0-D7
ALE
A0-A7
IO/M
1-Aug-13 Prof.Nitin Ahire 27
Differentiate between IO/M
Differentiate between IO/M
8085
Latch
AD0-AD7 A0-A7
D0-D7
IO/M Memory
IO device
ALE
A8-A15
A0-A7
1
1-Aug-13 Prof.Nitin Ahire 28
1-Aug-13 Prof.Nitin Ahire 28
Differentiate between IO/M
Differentiate between IO/M
8085
Latch
AD0-AD7 A0-A7
D0-D7
IO/M Memory
IO device
ALE
A8-A15
A0-A7
0
1-Aug-13 Prof.Nitin Ahire 29
Control & Status Signals
Control & Status Signals
S0
S1
1-Aug-13 Prof.Nitin Ahire 30
Generation of control Signals
Generation of control Signals
1-Aug-13 Prof.Nitin Ahire 31
Instruction, Data format
Instruction, Data format
and storage
and storage
• Part of instruction each instruction has
two parts
1 opcode: one is the task to be perform
(operational code)
2 operand: data to be operated on
(data)
The data can be specified in the various
form it may in the memory or I/O or in
the instruction it self.
1-Aug-13 Prof.Nitin Ahire 32
Opcode
Opcode
• Opcode : operational code
• Operand : Data
• Mnemonics : Instructions
Memory Locations Opcode Mnemonics Operand
2000 3E MVI A, 20
2001 20
2002 06 MVI B, 12
2003 12
2004 4F MOV C, A
1-Aug-13 Prof.Nitin Ahire 33
ALU
(A)
INST.
DECODER
CONTROL
LOGIC
B C
D E
H L
SP
PC (2000)
2000
2001
2002
2003
2004
3E
MERD
MEMORY LOCATION
ADD BUS
Internal Data BUS
DECODER
DATA BUS
3E
20
06
12
4F
1-Aug-13 Prof.Nitin Ahire 34
ALU
(A)
INST.
DECODER
CONTROL
LOGIC
B C
D E
H L
SP
PC (2001)
2000
2001
2002
2003
2004
20
MERD
MEMORY LOCATION
ADD BUS
Internal Data BUS
DECODER
DATA BUS
3E
20
06
12
4F
3E
1-Aug-13 Prof.Nitin Ahire 35
ALU
(A)
INST.
DECODER
CONTROL
LOGIC
B C
D E
H L
SP
PC (2002)
2000
2001
2002
2003
2004
06
MERD
MEMORY LOCATION
ADD BUS
Internal Data BUS
DECODER
DATA BUS
3E
20
06
12
4F
20
1-Aug-13 Prof.Nitin Ahire 36
ALU
(A)
INST.
DECODER
CONTROL
LOGIC
B C
D E
H L
SP
PC (2003)
2000
2001
2002
2003
2004
12
MERD
MEMORY LOCATION
ADD BUS
Internal Data BUS
DECODER
DATA BUS
3E
20
06
12
4F
20
1-Aug-13 Prof.Nitin Ahire 37
ALU
(A)
INST.
DECODER
CONTROL
LOGIC
B C
D E
H L
SP
PC (2004)
2000
2001
2002
2003
2004
4F
MERD
MEMORY LOCATION
ADD BUS
Internal Data BUS
DECODER
DATA BUS
3E
20
06
12
4F
20
1-Aug-13 Prof.Nitin Ahire 38
Instruction classification
Instruction classification
• “Instruction” is a command to the
microprocessor to perform a given task
on specified data”.
• The instruction can be classified into
following fundamental categories
1 Data transfer
2 Arithmetic & Logical operation
3 Branching operation
4 Machine control operation
1-Aug-13 Prof.Nitin Ahire 39
Instruction classification
Instruction classification
• 1 Data transfer (copy)
basically used to copies data from source
to destination without modifying the
content of the source like,
Opcode operand
MOV rd, rs
MVI r, 8-bit
IN 8 bit port add.
OUT 8 bit port add.
1-Aug-13 Prof.Nitin Ahire 40
Instruction classification
Instruction classification
• 1 Data transfer (copy)
• LXI Rp, 16-bit add.
• MOV R,M
• MOV M,R
• LDA 16-bit add.
• STA 16-bit add.
• LDAX R*
• STAX R*
• LHLD 16-bit add (1st memory location copy to L & 2nd memory
location to H)
• SHLD 16-bit add
*R – Register pair
LHLD 4000H & SHLD 4000H
LHLD 4000H & SHLD 4000H
H L memory
» 4000
» 4001
1-Aug-13 Prof.Nitin Ahire 41
03
70
03
70
1-Aug-13 Prof.Nitin Ahire 42
Instruction classification
Instruction classification
• Arithmetic operation
These instruction perform arithmetic
operation such as addition subtraction,
increment, decrement.
• ADD R
• ADI data
• ADC R
• ADC M
• ACI data
• DAD Rp
1-Aug-13 Prof.Nitin Ahire 43
Instruction classification
Instruction classification
• SUB R
• SUB M
• SBB R
• SBB M
• SUI Data
• SBI Data
• DAA
1-Aug-13 Prof.Nitin Ahire 44
Instruction classification
Instruction classification
• INR R
• DCR R
• INR M
• DCR M
• INX Rp
• DCX Rp
1-Aug-13 Prof.Nitin Ahire 45
Instruction classification
Instruction classification
• Logical instruction.
These instruction perform various logical
operation with the content of the
accumulator
e.g. 1) AND,OR,EX-OR(ANA R,ANI Data,
XRA R)
2) Rotate (RAL,RAR,RLC,RRC)
3) Compare (CMP B,CPI Data)
4) Complement (CMC, CMA,STC)
RAL
RAL
1-Aug-13 Prof.Nitin Ahire 46
More about
More about CMP R
CMP R
instruction
instruction
• CMP R
• This instruction compare the contents of
accumulator with the contents of register
specified
• The operation of comparing is performed by
subtracting (Acc. – Reg.)
• The contents of Acc or Reg. are not altered
• The result of comparison is indicated by flags
When A>R ; CY=0 & Z=0
When A=R ; CY=0 & Z=1
When A<R ; CY=1 & Z=0
1-Aug-13 Prof.Nitin Ahire 47
1-Aug-13 Prof.Nitin Ahire 48
Instruction classification
Instruction classification
• Branching operation
These group of instruction alter the
sequence of program execution
either conditionally or unconditionally
e.g. JUMP (conditionally or unconditionally)
CALL & RET (conditionally or unconditionally)
1-Aug-13 Prof.Nitin Ahire 49
Instruction classification
Instruction classification
• Machine control instruction
These instruction control the machine
function such as Halt (HLT),
interrupt (RST 1) or do noting (NOP)
More about
More about DAA
DAA
instruction
instruction
• Decimal Adjust Accumulator
• If lower nibble of A > 9 or AC =1
then, lower nibble of A = lower
nibble of A + 06H.
• If Higher nibble of A > 9 or CY =1
then, Higher nibble of A = Higher
nibble of A + 06H.
1-Aug-13 Prof.Nitin Ahire 50
• E.g. 1) 55 h + 06 h = 5B h
55 + 06 = 61 D
1-Aug-13 Prof.Nitin Ahire 51
Programming
Programming
• Write a generalized program for
addition of two 8 -bit numbers
and get the result in BCD
• 1st No. is located at memory location
C200h
• 2ndNo. is located at memory location
C201h
• Save the result at next location C202
1-Aug-13 Prof.Nitin Ahire 52
1-Aug-13 Prof.Nitin Ahire 53
Addition of two 8 bit
Addition of two 8 bit number
number
located at C200h & C201h
located at C200h & C201h
LXI H, C200H; load HL pair by C200h
MOV A,M; Move 1st No. in the Reg. A
INX H ; increment the HL pair by 1
ADD M; Add A+(M)=A
DAA
INX H; increment the HL pair by 1
MOV M,A; move the result in M
HLT; Stop
Programming
Programming
• Write a generalized program for addition
of two 8 -bit numbers located at (with carry)
• 1st No. is located at memory location C200h
• 2ndNo. is located at memory location C201h
• Save the result at next memory location C202h
• And save the status of carry at next memory
location C203h
1-Aug-13 Prof.Nitin Ahire 54
Addition of two 8
Addition of two 8-
-bit numbers
bit numbers
• MVI C,00H ; use reg. C to know the status of CY flag
• LXI H,C200h ; set memory pointer at C200h
• MOV A,M ; transfer the 1st No. from memory to Acc.
• INX H; go to the next memory location point to 2nd No.
• ADD M; Add A+M =A
• JNC Down (Put 16-bit memory address of target instruction)
• INR C ; If there is carry increment the reg. C by 1
• Down: STA C202H ; load the Acc. Data at C202h
• MOV A,C ; load Carry to Acc
• STA C203H ; load Acc. Data (carry) at C203h
• RST 1/ HLT ; Stop
1-Aug-13 Prof.Nitin Ahire 55
Programming
Programming
• Write a generalized program for addition
of two 16-bit numbers located at (with carry)
• 1st No. is located at memory location C200h & C201h
• 2ndNo. is located at memory location C202h & C203h
• Save the result at next memory location C204h & C205h
• And save the status of carry at next memory location
C206h
1-Aug-13 Prof.Nitin Ahire 56
1-Aug-13 Prof.Nitin Ahire 57
Addition of two 16 bit number
Addition of two 16 bit number
MOV C,00h ; Reg. C for to save the status of carry flag
LHLD C200H ; Here C200h-L=34, C201h H=12
XCHG ; exchange HL with DE
LHLD C202H ; Here L= 21, H=43
DAD D ; DE+HL = HL
JNC down
INR C
Down: SHLD C204H ; store the result
MOV A,C
STA C206H ; store the carry
HLT ; stop
Find the largest number from the series of 10
Find the largest number from the series of 10
numbers
numbers
• The 10 numbers are saved from memory
location 8500h to 8509h
• Save the largest number at memory location
8550h
1-Aug-13 Prof.Nitin Ahire 58
8500 8501 8502 8503 8504 8505 8506 8507 8508 8509
99 66 AA DF DD 97 F3 44 FE 67
8550
XX
Find the largest number from the series of 10 numbers
Find the largest number from the series of 10 numbers
• MVI C,O9H ; counter
• LXI H,8500H ; memory pointer
• MOV A,M; move 1ST No. to Acc.
• UP:INX H ; Increment HL pair point to 2nd No.
• CMP M; Compare 1st No. with 2nd No.
• JNC DOWN; Jump on no carry ( A > M)
• MOV A,M ; If carry change the No. ( A < M)
• DOWN:DCR C ; Decrement the counter by 1
• JNZ UP; Check for zero flag ( counter = zero)
• STA 8550H ; Save the result ( Acc to 8850h)
• HLT; Stop
1-Aug-13 Prof.Nitin Ahire 59
Memory
location
Opcode,
Operand
Mnemonics Remark
8000 0E ,09 MVI C,09H COUNTER
8002 21,00,85 LXI H,8500H MEMORY POINTER
8005 7E MOV A,M 1ST No. to Acc.
8006 23 UP:INX H Increment HL pair
8007 BE CMP M Compare
8008 D2,0C,80 JNC DOWN Jump on no carry
800B 7E MOV A,M If carry change the No.
800C 0D DOWN:DCR C Decrement the counter
800D C2,06,80 JNZ UP Check for zero flag
8010 32,50,85 STA 8550H Save the result
8013 76 HLT Stop
1-Aug-13 Prof.Nitin Ahire 60
1-Aug-13 Prof.Nitin Ahire 61
8550
FE
• After the execution of program
status of memory location
Block Transfer
Block Transfer
• Write a program to transfer a block
of data from 8500H to 8509H. Store
the data from 8570H to 8579H .
1-Aug-13 Prof.Nitin Ahire 62
8500 8501 8502 8503 8504 8505 8506 8507 8508 8509
99 66 AA DF DD 97 F3 44 FE 67
8570 8571 8572 8573 8574 8575 8576 8577 8578 8579
xx xx xx xx xx xx xx xx xx xx
Program
Program
1-Aug-13 Prof.Nitin Ahire 63
LXI H ,8500H ; source location
LXI H ,8500H ; source location
LXI B
LXI B ,8570H ; Destination location
,8570H ; Destination location
MVI
MVI D,0AH ; Counter
D,0AH ; Counter
UP
UP MOV
MOV A,M ; 1
A,M ; 1st
st No. transfer in Acc.
No. transfer in Acc.
STAX B;
STAX B; Save Acc. Content at memory location pointed by BC
Save Acc. Content at memory location pointed by BC Reg
Reg
INX
INX H
H
INX B
INX B
DCR D
DCR D
JNZ
JNZ UP
UP
HLT
HLT
• After the execution of program
status of memory location
1-Aug-13 Prof.Nitin Ahire 64
8500 8501 8502 8503 8504 8505 8506 8507 8508 8509
99 66 AA DF DD 97 F3 44 FE 67
8570 8571 8572 8573 8574 8575 8576 8577 8578 8579
99 66 AA DF DD 97 F3 44 FE 67
Draw a minimum mode system of 8085
Draw a minimum mode system of 8085
• The minimum number of components
required to make a system using
8085 is called minimum system or
minimum mode system.
1-Aug-13 Prof.Nitin Ahire 65
1-Aug-13 Prof.Nitin Ahire 66
8
0
8
5
74
LS
373
74
LS
138
Memory I/O
MERD
MEWR
IORD
IOWR
A0-A15
D0-D7
A0-A7
ALE
AD0-AD7
A8-A15
RD
IO/M
WR
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
READY
SOD
SID
RESET OUT
RESET IN
VCC
Minimum mode system
Minimum mode system(8085
(8085)
)
X1
X2
1-Aug-13 Prof.Nitin Ahire 67
Instruction classification
Instruction classification
• The 8085 instruction set is classified
into the following 3 group according
to word size or byte size
1) 1- byte instruction
2) 2- byte instruction
3) 3 –byte instruction
1-Aug-13 Prof.Nitin Ahire 68
1
1-
- byte instruction
byte instruction
• A 1- byte instruction includes the
opcode and the operand in the same
byte
e.g. Opcode operand hex code
1 MOV C, A (4F) (opcode)
2 ADD B (80) (Data)
each instruction required 1 memory
location ( 8-bit)
1-Aug-13 Prof.Nitin Ahire 69
2
2-
- byte instruction
byte instruction
• In the 2- byte instruction the first byte
specifies the operation code and the
second byte specifies the operand
e.g. Opcode operand hex code
MVI A, 12H 3E (opcode)
12 (Data)
These instruction required 2 memory
location
1-Aug-13 Prof.Nitin Ahire 70
3
3-
- byte instruction
byte instruction
• In 3-byte instruction the first byte specifies the
opcode and the following 2 bytes specify the 16-
bit address
e.g. Opcode operand hex code
LDA 2050 3A (Opcode)
50 (Data)
20 (Data)
Note the second byte is the lower address and the
third byte is the high order address
These instruction required 3 memory location
1-Aug-13 Prof.Nitin Ahire 71
Addressing
Addressing mode
mode
• The different methods (mode) to select
the operands or address are called
addressing mode
• For 8085 they are
1 Immediate addressing
2 Register addressing
3 Direct addressing
4 Indirect addressing
5 Implied addressing
1-Aug-13 Prof.Nitin Ahire 72
Addressing mode
Addressing mode
1 Immediate addressing
• In the immediate addressing mode the
data is specified in the instruction it self.
• The immediate addressing mode
instruction are either 2- byte or 3- byte
long.
• The instruction contain the letter “I”
indicate the immediate addressing mode.
e.g. 1 MVI A,12h
2 LXI H,2000h
1-Aug-13 Prof.Nitin Ahire 73
Addressing mode
Addressing mode
2 Register addressing mode
• In register addressing mode the source
and destination operands are general
purpose registers
• The register addressing mode
instructions are generally of 1 –byte
e.g. 1 MOV A,B
2 ADD B
3 PCHL
4 XRA A
1-Aug-13 Prof.Nitin Ahire 74
Addressing mode
Addressing mode
3 Direct addressing
• In the direct addressing mode the
16 bit address of the data or operand
is directly specified in the instruction
• These instruction are 3 –byte
instruction.
e.g. 1 LDA 2000h
2 STA 2060h
1-Aug-13 Prof.Nitin Ahire 75
Addressing mode
Addressing mode
4 Indirect addressing
• In the Indirect addressing mode the
instruction reference the memory
through the register pair i.e. the
memory address where the data is
located is specified by the register
pair
e.g.1 MOV A,M
2 LDAX B
1-Aug-13 Prof.Nitin Ahire 76
Addressing mode
Addressing mode
5 Implied addressing
• The Implied mode of addressing does not
required any operand
• The data is specified within the opcode it-
self
• Generally these instructions are 1-byte
instruction
• The data is supposed to be present in the
Accumulator
e.g. 1 RAL
2 CMC
1-Aug-13 Prof.Nitin Ahire 77
Timing diagram
Timing diagram
• For better understanding of each
instruction it is very essential to
understand the Timing diagram of
each instruction.
• The graphical representation of each
instruction with respective to time i.e.
CLOCK is called “Timing Diagram”
1-Aug-13 Prof.Nitin Ahire 78
Timing diagram
Timing diagram
• Instruction cycle (IC) : The essential step
required by CPU to fetch and execute an
instruction is called IC
IC=FC+EC
• Machine cycle (MC) : Time required by
microprocessor to complete the operation
of accessing memory or I/O device is
called MC.
• T –state :Each clock cycle is called T-state
1-Aug-13 Prof.Nitin Ahire 79
Timing diagram
• The µP operates with reference to clock signal.
• Each clock cycle is called a T state and a
collection of several T states gives a machine
cycle.
• Important machine cycles are :
1. Op-code fetch.
2. Memory read.
3. Memory write.
4. I/O-read.
5. I/O write.
Timing diagram
Timing diagram
• Timing diagram for the 1- byte
instruction
• single MC = opcode fetch
1-Aug-13 Prof.Nitin Ahire 80
Memory
location /(PC)
Opcode Instruction
2005 4F MOV C,A
1-Aug-13 Prof.Nitin Ahire 81
1-Aug-13 Prof.Nitin Ahire 82
Control & Status Signals
Control & Status Signals
S0
S1
1-Aug-13 Prof.Nitin Ahire 83
Timing diagram
Timing diagram
• Step 1 (State T1) In the state, 8085 sends the status
signals, IO/M=0, S1=1 and S0=1
• The 8085 send a 16 bit address on A8-A15 and AD0-
AD7
• The high order bytes of PC (20) is placed on the A8-A15
lines, and it remain there upto T3 state.
• The low order bytes of PC (05) placed on the AD0-
AD7,lines which remain there only for T1
• During this state, ALE gives a positive pulse signal is
used to latch the add A0-A7.
• No control signal is generated in state. ( RD & WR )
1-Aug-13 Prof.Nitin Ahire 84
Timing diagram
Timing diagram
• Step2 (T2): The content of PC lower byte will
disappear on AD0-AD7 lines, so the same line can be
used as data line . The contents of A0-A7 are still
available for memory from external Latch.
• The control signal RD is made low by the processor
which enables the read ckt of addressed memory
device.
• Then the memory device send the content on the data
bus D0-D7 (4F)
• In addition to these the processor increments PC
content by one
1-Aug-13 Prof.Nitin Ahire 85
Timing diagram
Timing diagram
• Step3 (T3): during this cycle the data from
memory (opcode) is transfer in the instruction
Reg. and RD control signal made HIGH
1-Aug-13 Prof.Nitin Ahire 86
Timing diagram
Timing diagram
Step 4 (T4): the microprocessor perform only
internal operation.
The opcode decoded by the CPU and 8085 decide
1) Whether it should enter T5 and T6 states or not
2) How my bytes of instruction it is ?
If instruction doesn’t required T5 &T6 states, it
go to the next MC
1-Aug-13 Prof.Nitin Ahire 87
Timing diagram
Timing diagram
• Step 5 (T5 &T6): T5 and T6 states, states are
required to complete decoding and some
operations inside the 8085 it depend on the
type of instruction
1-Aug-13 Prof.Nitin Ahire 88
Timing diagram
Timing diagram
• Following instruction required T5 & T6 states for the opcode
fetch MC
1 CALL
2 CALL conditional
3 DCX Rp
4 INX Rp
5 PCHL
6 SPHL
7 PUSH Rp
8 RET conditional
All other instruction except the above instruction required opcode
fetch of T1 to T4 states only.
1-Aug-13 Prof.Nitin Ahire 89
Timing diagram
Timing diagram
• Machine cycle (type)
Few more MC
1 opcode fetch
2 operand fetch
3 Memory read
4 Memory write
5 I/O read
6 I/O write
7 Interrupt Ack M-cycle
8 Ideal M-cycle
Timing diagram
Timing diagram
• Timing diagram for the 2- byte
instruction
• 2 MC = 1 opcode fetch & 2 Data fetch
1-Aug-13 Prof.Nitin Ahire 90
Memory
location /(PC)
Opcode Instruction
2000 06 MVI B , 43 h
2001 43
1-Aug-13 Prof.Nitin Ahire 91
1-Aug-13 Prof.Nitin Ahire 92
Stack control and branching group
Stack control and branching group
• Stack is the reserved area of the
memory in RAM where temporary
information may be stored
• Stack pointer (SP): an 16-bit SP is
used to hold the address of the most
recent stack entry. It work on the
principle of LIFO or FILO.
STACK MEMORY
STACK MEMORY
1-Aug-13 Prof.Nitin Ahire 93
STACK
Memory
(Reserve area)
Total Memory
Size
Reserve
area
1-Aug-13 Prof.Nitin Ahire 94
Stack Related Instructions
Stack Related Instructions
• LXI SP,16-bit address
• LXI SP, 2000 h
• LXI SP,FFFF h
• PUSH Rp(PUSH B, PUSH H, PUSH D,PUSH PSW)
• POP RP (POP B, POP D,POP H,POP PSW)
• SPHL ( HL SP)
• XTHL ( HL SP)
• PCHL ( HL PC)
1-Aug-13 Prof.Nitin Ahire 95
Stack Related Instructions
Stack Related Instructions
• PUSH B
Let BC=3010, B=30h, C=10h
suppose SP initialized at FFFF h
after execution of instruction PUSH B
SP=SP-1=FFFF-1=FFFE
B [FFFE] =30h
again SP=SP-1=FFFE-1=FFFD
C [FFFD]=10h
SP=[FFFD] New location of SP
1-Aug-13 Prof.Nitin Ahire 96
PUSH H
Contents on the stack & in the register
after the PUSH instruction
42
42 F2
F2
F
C
E
L
A
B
D
H
SP
F2
42
X
2097
2098
2099
2097
8085 Register
Memory
Initially SP at 2900 & H=42 , L=F2
1 2
1-Aug-13 Prof.Nitin Ahire 97
Stack Related Instructions
Stack Related Instructions
• POP B
initially B=20, C=40h
SP at=[FFFD]=10h
at=[FFFE]=30h
After execution of POP B
SP=[FFFD]=10h [C]
SP=SP+1=[FFFE]=30h [B]
Again SP=SP+1=[FFFF]
Now B=30h, C=10h and SP=[FFFF]
POP H
POP H
1-Aug-13 Prof.Nitin Ahire 98
Initially SP at 2097 After POP H ,
H= 42
L= F2
Contents on the stack and in the registers
after the POP instruction
42 F2
2099
F2 2097
42 2098
X 2099
F
C
E
L
A
B
D
H
SP
8085 Register
1
2
1-Aug-13 Prof.Nitin Ahire 99
Subroutines
Subroutines
• Whenever we need to use a group of instruction
several times throughout a program there is a way we
can avoid having to write the group of instructions each
time we want to use them.
• One way is to write the group of instruction
separately, Called Subroutines
• Whenever we want to execute that group of
instruction we can call that Subroutine.
• The return address has to be stored back on the stack
memory
1-Aug-13 Prof.Nitin Ahire 100
Subroutines
Subroutines
e.g.
6FFD 31 LXI SP, FFFF h
FF
FF
7000 CD CALL C200h
7001 00
7002 C2
7003 Next instruction
When this instruction is executed PC contents 7003h
(next instruction) will stored on to the stack and
microprocessor will load PC with C200h and start
executing instruction from C200h
1-Aug-13 Prof.Nitin Ahire 101
Subroutines
Subroutines
• If SP= FFFF h
• CALL C200. PC stack (memory)
(SP-1)=Pc H FFFF
(SP-2)=Pc L FFFE
SP=SP-2 FFED
PC=new C200
70
03
03
70
1-Aug-13 Prof.Nitin Ahire 102
Subroutines
Subroutines
• Conditional Call instructions
When condition is true, then CALL at NEW address else execute
the next instruction of the program
1) CZ Add
2) CNZ Add
3) CP Add
4) CM Add
5) CPO Add
6) CPE Add
7) CC Add
8) CNC Add If condition false 9T True16T
1-Aug-13 Prof.Nitin Ahire 103
Subroutines
Subroutines
• RET unconditionally
1 SP (PC L) PC Stack
2 SP+1 (PC H)
3 SP+2=SP
Initially SP at FFFD
After execution of RET SP=FFFF
70
03
03
70
FFFD
FFFE
FFFF
1-Aug-13 Prof.Nitin Ahire 104
Subroutines
Subroutines
• RET conditionally
When condition is true, then RET at the main
program
1) RZ
2) RNZ
3) RP
4) RM
5) RPO
6) RPE
7) RC
8) RNC
1-Aug-13 Prof.Nitin Ahire 105
Nested Subroutines
Nested Subroutines
• Whenever one subroutine calls another
subroutine in order to complete a specific
task, the operation is called as nesting.
• The First subroutine may call the second
subroutine and in turn the second
subroutine may called first or third
subroutine such routines called NESTED
subroutines
1-Aug-13 Prof.Nitin Ahire 106
Nested subroutines
Nested subroutines
. sub 1 sub 2
. . .
call sub 1 call sub 2 .
. . .
. . .
. RET RET
1-Aug-13 Prof.Nitin Ahire 107
• There are two kinds of subroutines
1) Re-entrant subroutines.
2) Recursive subroutines.
Nested Subroutines
Nested Subroutines
1-Aug-13 Prof.Nitin Ahire 108
Re entrant
Re entrant Subroutines
Subroutines
1)Re-entrant Subroutine
It may happened a Subroutine ‘1’ is called
from main program and ‘2’ Subroutine is
called from Subroutine ‘1’ and Subroutine
‘2’ may called Subroutine ‘1’ then the
program re entrant in Subroutine ‘1’ this is
called re-entrant Subroutine
1-Aug-13 Prof.Nitin Ahire 109
Re entrant
Re entrant subroutine
subroutine
• Main Program
• Next
• line
SUB 1 SUB 2
CALL
CALL
RET
RET
1-Aug-13 Prof.Nitin Ahire 110
Recursive
Recursive subroutine
subroutine
• A procedure which called it self is
called a recursive subroutine
• The recursive subroutine loop takes
long time to execute
• In this type of subroutine we
normally define N ( recursive depth)
it is decrement by one after each
subroutine is call until N=0
1-Aug-13 Prof.Nitin Ahire 111
Recursive
Recursive subroutine
subroutine
• Main Program N=3 N=2 N=1
• Next
• line
SUB 1 SUB 2
CALL
CALL
RET
RET
RET
SUB 3
CALL
1-Aug-13 Prof.Nitin Ahire 112
Software
Software Delay
Delay
• Delay : operating after an some
time interval.
• Microprocessor take fixed amount of
time to execute each instruction
• Microprocessor driven by fixed
frequency (crystal)
• So using instruction we can generate
a Delay.
1-Aug-13 Prof.Nitin Ahire 113
Software Delay
Software Delay
• E.g. delay using NOP instruction
NOP ( 1-byte instruction- 4T state)
assume crystal freq= 4Mhz..
CLK freq = 2Mhz
(T=0.5 microsecond)
Delay using NOP = 4 X 0.5 microsecond
= 2.0 microsecond
1-Aug-13 Prof.Nitin Ahire 114
Software Delay
Software Delay
• If we want the more delay than
4T,then we go on increasing NOP after
NOP.
• Impractical (size of program increase)
1-Aug-13 Prof.Nitin Ahire 115
Delay using 8
Delay using 8 –
–bit counter
bit counter
Delay
Initializes 8-bit counter
Decrement counter
RET
yes
No
1-Aug-13 Prof.Nitin Ahire 116
Delay using 8
Delay using 8 –
–bit counter
bit counter
•
MVI C, Count 7T
up: DCR C 4T
JNZ :up 10T/7T
RET 10T
The loop is executed ( count-1 ) times
1-Aug-13 Prof.Nitin Ahire 117
Delay using 8
Delay using 8 –
–bit counter
bit counter
• Formula for delay value
Td=[ M + {(count) X N} -3 ] T
M=No. of T state out side the loop
N=No. of T state inside the loop
M=10+7=17 T; N=10+4=14T
1-Aug-13 Prof.Nitin Ahire 118
Delay using 8
Delay using 8 –
–bit counter
bit counter
JNZ instruction required 10 or 7 T state
based on the condition ( Z=0 or 1)
(when condition is satisfied it take
10T state and if not satisfied it take 7T
state)
so 3 T must be subtracted from total
value
1-Aug-13 Prof.Nitin Ahire 119
Delay using 8
Delay using 8 –
–bit counter
bit counter
• Td max= [17+[ {255} X 14 ] -3] T
= 3584 T
= 3584 X 0.5 microsecond
= 1792 microsecond
(FF)=(255)
1-Aug-13 Prof.Nitin Ahire 120
Delay using 16 bit counter
Delay using 16 bit counter
• LXI B, (count)H 10T
up: DCX B 6T
MOV A,C 4T
ORA B 4T
JNZ :up 10/7T
RET 10T
DCX not affect the zero flag.
1-Aug-13 Prof.Nitin Ahire 121
Delay using 16 bit counter
Delay using 16 bit counter
Td=[ M + {(count) X N} -3 ] T
M=No. of T state out side the loop
N=No. of T state inside the loop
M=20 T; N=24T
1-Aug-13 Prof.Nitin Ahire 122
Delay using 16 bit counter
Delay using 16 bit counter
• Td max= [20+[ {65535}X 24 ] -3] T
= 1572857 T
=1572857 X 0.5 microsecond
= 78642 microsecond
(FFFF)=(65535) largest count.
1-Aug-13 Prof.Nitin Ahire 123
Memory and I/O interfacing
Memory and I/O interfacing
• Types of memory
1 ROM (EPROM)
2 RAM
1-Aug-13 Prof.Nitin Ahire 124
Memory structure & it’s
Memory structure & it’s
requirement's
requirement's
• The read write
memories consist
of an array of
registers, where in
each register has a
unique address
• M=No. of register
• N=No. of bits
MXN
I/P
decoder
I/P Buffer
O/P Buffer
A1
A0
AM
Data i/Ps
Data o/p s
WR
RD
CS
1-Aug-13 Prof.Nitin Ahire 125
Memory structure & it’s
Memory structure & it’s
requirement's
requirement's
• If the memory having 13 address
line and 8 data lines, then it can
access 213 address lines = 8192
and N= 8 bit or 1-byte
• No of address lines of the ‘up’ is to
be used to find how much memory
array can be access by that
processor.
1-Aug-13 Prof.Nitin Ahire 126
No. of address line
No. of address line
required to accessed the memory
required to accessed the memory
• No of lines size of memory
1 21= 2
2 22= 4
3 23= 8
4 24 =16
10 210= 1K= 1024
11 211 =2K= 2048
16 216 =64K= 65536
1-Aug-13 Prof.Nitin Ahire 127
EPROM IC available in the
EPROM IC available in the
market
market
IC NO size
2716 2k X 8
2732 4k X 8
2764 8k X 8
27128 16k X 8
27256 32K x 8
27512 64k X 8
1-Aug-13 Prof.Nitin Ahire 128
RAM IC available in the
RAM IC available in the
market
market
IC NO size
6116 2k X 8
6264 8k X 8
62512 64k X 8
2114 1k X 4
1-Aug-13 Prof.Nitin Ahire 129
Comparison between full
Comparison between full
and partial decoding
and partial decoding
• full decoding
1) Also referred to be as
absolute decoding
2) All address lines are
consider
3) More hardware
required
• partial decoding
1) Also referred to be
as liner decoding
2) Few address lines are
ignored
3) Decoder hardware is
simple
1-Aug-13 Prof.Nitin Ahire 130
8085 Memory Interfacing
1-Aug-13 Prof.Nitin Ahire 131
Memory and I/O interfacing
Memory and I/O interfacing
• Types of memory
1 ROM (EPROM)
2 RAM
1-Aug-13 Prof.Nitin Ahire 132
Memory structure & it’s
Memory structure & it’s
requirement's
requirement's
• The read write
memories consist
of an array of
registers, where in
each register has a
unique address
• M=No. of register
• N=No. of bits
MXN
I/P
decoder
I/P Buffer
O/P Buffer
A1
A0
AM
Data i/Ps
Data o/p s
WR
RD
CS
1-Aug-13 Prof.Nitin Ahire 133
Memory structure & it’s
Memory structure & it’s
requirement's
requirement's
• If the memory having 13 address
line and 8 data lines, then it can
access 213 address lines = 8192
and N= 8 bit or 1-byte
• No of address lines of the ‘up’ is to
be used to find how much memory
array can be access by that
processor.
1-Aug-13 Prof.Nitin Ahire 134
No. of address line
No. of address line
required to accessed the memory
required to accessed the memory
• No of lines size of memory
1 21= 2
2 22= 4
3 23= 8
4 24 =16
10 210= 1K= 1024
11 211 =2K= 2048
16 216 =64K= 65536
1-Aug-13 Prof.Nitin Ahire 135
EPROM IC available in the
EPROM IC available in the
market
market
IC NO size
2716 2k X 8
2732 4k X 8
2764 8k X 8
27128 16k X 8
27256 32K x 8
27512 64k X 8
1-Aug-13 Prof.Nitin Ahire 136
RAM IC available in the
RAM IC available in the
market
market
IC NO size
6116 2k X 8
6264 8k X 8
62512 64k X 8
2114 1k X 4
1-Aug-13 Prof.Nitin Ahire 137
Comparison between full
Comparison between full
and partial decoding
and partial decoding
• full decoding
1) Also referred to be as
absolute decoding
2) All address lines are
consider
3) More hardware
required
• partial decoding
1) Also referred to be
as liner decoding
2) Few address lines are
ignored
3) Decoder hardware is
simple
1-Aug-13 Prof.Nitin Ahire 138
8085 Memory Interfacing
8085 Memory Interfacing
• Generally µP 8085 can address 64 kB of memory .
• Generally EPROMS are used as program memory and RAM as
data memory.
• We can interface Multiple RAMs and EPROMS to single µP .
• Memory interfacing includes 3 steps :
1. Select the chip.
2. Identify register.
3. Enable appropriate buffer.
4. linkmemory_interfacing.ppt
1-Aug-13 Prof.Nitin Ahire 139
8085 Memory Interfacing
8085 Memory Interfacing
• Example: Interface 2Kbytes of Memory to 8085
with starting address 8000H.
Initially we realize that 2K memory requires 11
address lines
(2^11=2048). So we use A0-A10 .
• Write down A15 –A0
A15
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ADD
8000H
87FFH
1-Aug-13 Prof.Nitin Ahire 140
8085 Memory Interfacing
8085 Memory Interfacing
• Address lines A0-A10 are used to interface memory
while A11,A12,A13,A14,A15 are given to 3:8 Decoder
to provide an output signal used to select the
memory chip CS‾or Chip select input.
• MEMR‾ and MEMW‾are given to RD‾and WR‾pins
of Memory chip.
• Data lines D0-D7 are given to D0-D7 pins of the
memory chip.
• In this way memory interfacing can be achieved.
1-Aug-13 Prof.Nitin Ahire 141
8085 Memory Interfacing
8085 Memory Interfacing
• The diagram of 2k interfacing is shown below:
A15-A8
Latch
AD7-AD0
D7- D0
A7- A0
8085
ALE
IO/M
RD
WR
2K Byte
Memory
Chip
WR
RD
CS
A10- A0
A15- A11
3:8DECODER
Microprocessor & Microcontroller
Microprocessor & Microcontroller
-
- I
I
T.E Sem V (Rev)
T.E Sem V (Rev)
Prof. Nitin Ahire
Prof. Nitin Ahire
XIE, Mahim
XIE, Mahim
1-Aug-13 Prof.Nitin Ahire 143
Connection of I/O devices.
Connection of I/O devices.
• Polling method
• Interrupt method
1-Aug-13 Prof.Nitin Ahire 144
Interrupt system of 8085
Interrupt system of 8085
• Definition: “It is a mechanism by
which an I/O device ( Hardware
interrupt) or an instruction (software
interrupt) can suspend the normal
execution of the processor and get it
self serviced.”
1-Aug-13 Prof.Nitin Ahire 145
Types of interrupt
Types of interrupt
• 1) Hardware interrupt
• 2) Software interrupt
1-Aug-13 Prof.Nitin Ahire 146
Hardware interrupt
Hardware interrupt
• Interrupt : “It is an external
asynchronous input that inform the
‘up’ to complete the instruction that
it is currently executing and fetch a
new routine in order to offer a
service to that I/O devices. Once the
I/O device is serviced, the ‘up’ will
continue with execution of its normal
program.”
1-Aug-13 Prof.Nitin Ahire 147
Hardware interrupt
Hardware interrupt
• 8085 has ‘5’ hardware interrupt
1)Trap
2)RST 7.5
3)RST 6.5
4)RST 5.5
5)INTR
1-Aug-13 Prof.Nitin Ahire 148
Types of Hardware interrupt
Types of Hardware interrupt
• NMI( non maskable)
1) It can’t be masked or
made pending
2) Highest priority
3) This interrupt disable
all maskable interrupts
4) Used for emergency
purpose like power
failure, smoke detector
e.g. TRAP
• Maskable
1) It can be masked or
made pending
2) Lower priority
3) These interrupt dose
not disable non
maskable interrupt
4) Used to interface
peripherals.
e.g. RST 7.5
1-Aug-13 Prof.Nitin Ahire 149
Hardware Interrupt
Hardware Interrupt
Priority interrupt ISR address trigger
1 TRAP 0024h edge +level
2 RST 7.5 003Ch edge
3 RST 6.5 0034h level
4 RST 5.5 002Ch level
5 INTR No specific level
location
1-Aug-13 Prof.Nitin Ahire 150
Software interrupt
Software interrupt
• 8085 has ‘8’ software interrupt
1)RST0
2)RST1
3)RST2
4)RST3
5)RST4
6)RST5
7)RST6
8)RST7
1-Aug-13 Prof.Nitin Ahire 151
Software interrupt
Software interrupt
• These instruction ( RST0-RST7) allow
the ‘up’ to transfer the program
control from main program to the
subroutine program (i.e. ISR)
ISR: interrupt service routing
1-Aug-13 Prof.Nitin Ahire 152
Software interrupt
Software interrupt
Interrupt Restart locations
RST 0 0 X 8 = 0000h
RST 1 1 X 8 = 0008h
RST 2 2 x 8 = 0010h
RST 3 3 X 8 = 0018h
RST 4 4 X 8 = 0020h
RST 5 5 X 8 = 0028h
RST 6 6 X 8 = 0030h
RST 7 7 X 8 = 0038h
1-Aug-13 Prof.Nitin Ahire 153
Software interrupt / hardware
Software interrupt / hardware
interrupt
interrupt
• Software interrupt
1)It is as synchronous event
2)This interrupt is requested
by executing instruction
3)PC is incremented
4)The priority is highest
5)It can’t be ignored
6)It is not used to interface
the peripheral
Used in debugging
• Hardware interrupt
1)It is an asynchronous
event
2)This interrupt is
requested by external
device
3)PC is not incremented
4)The priority is lower
than softer interrupt
5)Can be masked
6)It is used to interface
peripheral devices
1-Aug-13 Prof.Nitin Ahire 154
Interrupt related
Interrupt related
instructions
instructions
1) EI : it is used to enable the all
maskable interrupt. It required 1-
byte, one MC (4T). It does not
affect on TRAP
2) DI : it is used to disable all
maskable interrupt. 1-byte (4T). It
does not affect on TRAP
1-Aug-13 Prof.Nitin Ahire 155
Interrupt related
Interrupt related
instructions
instructions
SIM : (set interrupt mask)
1-byte (4T) state.
• Used to enable or disable RST 7.5, RST
6.5, RST 5.5 interrupts.
• It does not affect on TRAP & INTR .
• It is used in serial data transmission
• It also transfer serial data bit ‘D7’of ‘A’
to the SOD pin
• Hence the CWR format must be load in
the ‘A’ before execution of SIM
instruction.
1-Aug-13 Prof.Nitin Ahire 156
SIM (bit pattern)
SIM (bit pattern)
• SOD pin
• D7= SOD
• D6= serial data enable 1=enable, 0=disable
• D5= Don’t care
• D4= Reset R7.5 F/F, 1=Reset 0=no effect
• D3=MSE Mask set enable 1=D2,D1,D0 bit are effective
0=D2,D1,D0 bit are ignored
• D2= M’7.5 Mask RST 7.5 1= Mask or disable R7.5
0= Enable RST 7.5
• D1=M’6.5 Mask RST 6.5 1= Mask or disable R6.5
0= Enable RST 6.5
• D0=M’5.5 Mask RST 5.5 1= Mask or disable R5.5
0= Enable RST 5.5
SOD SDE M’ 6.5
M’ 7.5
MSE
R 7.5
X M’ 5.5
1-Aug-13 Prof.Nitin Ahire 157
Interrupt related
Interrupt related
instructions
instructions
RIM : ( read interrupt mask)
1-byte (4T) state.
• It gives the status of the pending maskable
interrupt (RST 7.5 – RST 5.5)
• It does not affect on TRAP & INTR
• It can also transfer the contents of the serial
input data on the SID pin into the
accumulator (‘D7’ bit.)
• Hence after execution of this instruction
serial data get load in to the accumulator
1-Aug-13 Prof.Nitin Ahire 158
RIM (bit pattern)
RIM (bit pattern)
• SID pin
• D7= SID
• D6=
• D5= if 1 respective interrupt is pending
• D4= 0 respective interrupt is not pending
• D3=IE interrupt enable
• D2=
• D1= if 1 respective interrupt is Masked
• D0= 0 respective interrupt is unmasked
SID I 7.5 M 6.5
M 7.5
IE
I 5.5
I 6.5 M 5.5
8155 (PPI)
8155 (PPI)
Prof. Nitin Ahire
Prof. Nitin Ahire
XIE, Mahim
XIE, Mahim
1-Aug-13 Prof.Nitin Ahire 160
Features of 8155 (PPI)
Features of 8155 (PPI)
• It is a multifunction device designed to use in
minimum mode system
• It contain RAM, I/O ports and Timer
• Features
1) 2k static RAM cell organized as 256 bytes
2) 2 programmable 8 bit I/O ports (A,B)
3) 1 programmable 6 bit I/O port (c)
4) 1 programmable 14 bit binary down
counter/timer
5) An internal address latch to de multiplex AD0-
AD7 using ALE
6) Internal selection logic for memory and I/O.
using command register
1-Aug-13 Prof.Nitin Ahire 161
8155
8155
AD0-AD7
IO/M
CE
ALE
RD
WR
VCC GND
RESET TIMER IN TIMER OUT
PA0-PA7
PB0-PB7
PC0-PC5
A
B
C
256x8
Static RAM
Timer
CE – 8155
CE - 8156
1-Aug-13 Prof.Nitin Ahire 162
Pin out
Pin out
• ADo-AD7 : address and data lines
internally de multiplex by using
internal latch and ALE signal address
lines are used to access the memory
or I/O port depending on the status
of IO/M^ pin i/p
• D0-D7 lines act as data bus
1-Aug-13 Prof.Nitin Ahire 163
Pin out
Pin out
• ALE : used to de multiplex the AD0-
AD7
• IO/M^ : used to differentiate
between IO or memory
• CE^ : used to select the 8155
• RD^ : used for to read the data from
memory or I/O
• WR^: used for to write the data from
memory or I/O
1-Aug-13 Prof.Nitin Ahire 164
Pin out
Pin out
• Reset : used to reset the 8155 IC
• PA0-PA7,PB0-PB7 : Port A and Port B I/P 8 bit
pins they can be programmed either i/p or o/p
port using command register
• PC0-PC5 : these are 6 bit I/O pins they can be
used as simple Input output port or control port
when PA and/or PB are used in handshake mode
• Timer in: this is an i/p to the timer
• Timer out :This is an o/p pin depending on the
mode of the timer o/p can be either a square
wave or pulse.
• VCC, GND : +5 v resp. to GND
1-Aug-13 Prof.Nitin Ahire 165
I/O port or timer selection
I/O port or timer selection
IO/M^ A2 A1 A0
1 0 0 0 CWR
1 0 0 1 PORT A
1 0 1 0 PORT B
1 0 1 1 PORT C
1 1 0 0 Timer LSB
1 1 0 1 Timer MSB
0 Memory option
1-Aug-13 Prof.Nitin Ahire 166
Control Word of 8155
Control Word of 8155
• D0=Port A 0=Input
• D1=Port B 1=Output
• D2 &D3 used with port C
• D4 (IEA=interrupt Enable Port A) 1=Enable
• D5 (IEB=interrupt Enable Port B) 0=Disable
• D6&D7 used in timer mode
D7 D6 D1
D2
D3
D4
D5 D0
1-Aug-13 Prof.Nitin Ahire 167
D7 D6 timer commands
0 0 NOP
0 1 Stop counting if timer
is running
1 0 Stop after TC (stop after
at the count)
1 1 Start timer if is not
running
1-Aug-13 Prof.Nitin Ahire 168
Timer mode
Timer mode
• MSB
• LSB
• Mode 0 In this mode the timer o/p remains high for half the
count and goes low for the remaining
count, thus providing the single square wave. The
pulse width is determined by count and clk freq
• Mode 1 In this mode the initial count is automatically reloaded
at the end of each count. Provide the continuous square
wave.
• Mode 2 In this mode single clock pulse is provided at the end
of count
• Mode 3 This is similar to mode 2 except the initial count is
reloaded to provided a continuous wave form
M2 M1 D9
D10
D11
D12
D13 D8
D7 D6 D1
D2
D3
D4
D5 D0
1-Aug-13 Prof.Nitin Ahire 169
• For port C
D3 D2
0 0 = ALT 1(port C as Input mode)
1 1 = ALT 2(Port C as Output Mode)
0 1 = ALT 3 used in handshake mode
1 0 = ALT 4 along with Port A &B
1-Aug-13 Prof.Nitin Ahire 170
Example 1
Example 1
• Design a square wave generator with
a pulse width of 100 us by using the
8155 timer if clock freq is 3MHz.
Sol : T=1/F=1/3MHz=330ns
Timer count=pulse period/CLK period
= 200us/330ns=606
count = 025Eh
1-Aug-13 Prof.Nitin Ahire 171
• Assuming the port addresses
CWR=20h
Timer LSB=24h
Timer MSB=25h
Count =025Eh
Therefore 5Eh must be load in the LSB timer
Select mode 1 for square wave.
Therefore 42h (01000010)must be load in the
MSB timer
1-Aug-13 Prof.Nitin Ahire 172
• Control word
To start the timer D7 and D6 bit must
be 1
set the bit of CWR and send to
address 20h
therefore C0h (11000000) must be
load in CWR register.
1-Aug-13 Prof.Nitin Ahire 173
Program for square wave
Program for square wave
• MVI A,5Eh
OUT 24H
MVI A,42H
OUT 25H
MVI A,C0H
OUT 20H
HLT
8255(PPI)
8255(PPI)
1-Aug-13 Prof.Nitin Ahire 175
Feature of 8255
Feature of 8255
• It is programmable parallel I/O device
• It has 3,8 bit I/O Ports: Port A, Port B,
Port C, which are arranged in two
groups of 12 pins.
• TTL compatible
• Direct bit set/reset capability is
available for Port C
1-Aug-13 Prof.Nitin Ahire 176
8255 PIN DIAGRAM
8255 PIN DIAGRAM
PA0-PA7 I/O Port A Pins
PB0-PB7 I/O Port B Pins
PC0-PC7 I/O Port C Pins
D0-D7 I/O Data Pins
RESET I Reset pin
RD¯ I Read input
WR ¯ I Write input
A0-A1 I Address pins
CS ¯ I Chip select
Vcc , Gnd I +5volt supply
1-Aug-13 Prof.Nitin Ahire 177
8255 BLOCK DIAGRAM
8255 BLOCK DIAGRAM
1-Aug-13 Prof.Nitin Ahire 178
8255 BLOCK DIAGRAM
8255 BLOCK DIAGRAM
 Data Bus Buffer: It is an 8 bit data buffer used to
interface 8255 with 8085. It is connected to D0-D7
bits of 8255.
 Read/write control logic: It consists of inputs
RD‾,WR‾,A0,A1,CS‾ .
 RD‾,WR‾ are used for reading and writing on to
8255 and are connected to MEMR‾,MEMW‾ of 8085
respectively.
 A0,A1 are Port select signals used to select the
particular port .
 CS ‾ is used to select the 8255 device .
 It is controlled by the output of the 3:8 decoder
used to decode the address lines of 8085.
1-Aug-13 Prof.Nitin Ahire 179
8255 BLOCK DIAGRAM
8255 BLOCK DIAGRAM
A1 A0 Selected port
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control Register
A0,A1 decide the port to be used in 8255.
1-Aug-13 Prof.Nitin Ahire 180
8255 BLOCK DIAGRAM
8255 BLOCK DIAGRAM
 Group A and Group B Control:
 Group A control consists of Port A and Port C
upper.
 Group B control consists of Port B and Port C
lower.
 Each group is controlled through software.
 They receive commands from the RD‾, WR‾ pins
to allow access to bit pattern of 8085.
 The bit pattern consists of :
1. Information about which group is operated.
2. Information about mode of Operation.
1-Aug-13 Prof.Nitin Ahire 181
8255 BLOCK DIAGRAM
8255 BLOCK DIAGRAM
• PORT A,B: These are bi-directional 8 bit ports
each and are used to interface 8255 with CPU
or peripherals.
• Port A is controlled by Group A while Port B is
controlled by Group B Control.
• PORT C: This is a bi-directional 8 bit port
controlled partially by Group A control and
partially by Group B control .
• It is divided into two parts Port C upper and
Port C lower each of a nibble.
• It is used mainly for control signals and
interfacing with peripherals.
1-Aug-13 Prof.Nitin Ahire 182
8255 Operating Mode
8255 Operating Mode
• 8255 provides one control word register
• It is selected when
A0=1,A1=1,CS^=0,WR^=0
• The read operation is not allowed for CWR
• There are two CWR formats (mode)
1)BSR mode 2)I/O mode
• The two basic modes are selected by D7
bit of control register
• when D7=1 it is a I/O mode  D7=0 it is
BSR mode
1-Aug-13 Prof.Nitin Ahire 183
8255 MODES
8255 MODES
• BSR (Bit Set Reset) Mode
• Only C is available for bit mode access.
• Allows single bit manipulation for control
applications
• Mode 0 : Simple I/O
• Any of A, B, CL and CH can be programmed as
input or output
• Mode 1: I/O with Handshake
• A and B can be used for I/O
• C provides the handshake signals
• Mode 2: Bi-directional with handshake
• A is bi-directional with C providing handshake
signals
• B is simple I/O (mode-0) or handshake I/O
(mode-1)
1-Aug-13 Prof.Nitin Ahire 184
• Bit D7 must be zero for BSR mode
• The BSR mode is a port C bit set/reset mode.
• The indivisible bit of port C can be set or reset
by writing a control word in CWR.
• Port C bit set/reset ; if D0=0 reset
D0=1 set
• The port pin of port C is selected using bit
D3,D2,D1
• The BSR mode affect only one bit of port C at a
time
BSR mode
BSR mode
0 X b
b
b
x
x S/R
D7 D6 D1
D2
D3
D4
D5 D0
1-Aug-13 Prof.Nitin Ahire 185
Port C bit selection
Port C bit selection
D3/b D2/b D1/b Bit
0 0 0 Bit 0
0 0 1 Bit 1
0 1 0 Bit 2
0 1 1 Bit 3
1 0 0 Bit 4
1 0 1 Bit 5
1 1 0 Bit 6
1 1 1 Bit 7
1-Aug-13 Prof.Nitin Ahire 186
Example
Example
• Write a set of instruction to perform the
following
1)Set bit 4 of port C
2)Reset bit 4 of port C( Assume Port C Address
=12 h)
Sol: 1) MVI A, 09h
OUT 12h
2) MVI A,08h
OUT 12h
1-Aug-13 Prof.Nitin Ahire 187
I/O mode (CWR)
I/O mode (CWR)
• When the bit D7=1 then I/O mode is selected
• The bit D6 and D5 used for mode selection of Group A
• If the D4 =1port A act as I/P port
D4 = 0 port A act as O/P Port
• If the D3 = 1 Port C Upper act as I/P Port
D3 = 0 port C Upper act as O/P Port
• The bit D2 used for mode selection of Group B
• If the D1 = 1 port B act as I/P Port
• D1 = 0 port B act as O/P Port
• If the D0 = 1 Port C Lower act as I/P Port
D0 = 0 Port C Lower act as O/P Port
I/O,BSRMode A PB
Mode B
PCU
PA
Mode A PCL
D7 D6 D1
D2
D3
D4
D5 D0
1-Aug-13 Prof.Nitin Ahire 188
Example
Example
• Write a program to initialize 8255 in
the configuration given below:
1 Port A : Simple I/P
2 Port B : Simple O/P
3 Port CL: O/P
4 Port CU: I/P
Assume CWR address is 83h
1-Aug-13 Prof.Nitin Ahire 189
solutions
solutions
• MVI A,98h
OUT 83h
I/O,BSRMode A PB
Mode B
PCU
PA
Mode A PCL
1 0 0
0
1
1
0 0
1-Aug-13 Prof.Nitin Ahire 190
INTERFACING 8085  8255
INTERFACING 8085  8255
• Here 8255 is interfaced in I/O Mapped I/O mode.
Initially we write down the addresses and then
interface it .
A15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port
1 0 0 0 0 X X X X X X X X X 0 0 A
1 0 0 0 0 X X X X X X X X X 0 1 B
1 0 0 0 0 X X X X X X X X X 1 0 C
1 0 0 0 0 X X X X X X X X X 1 1 CW
1-Aug-13 Prof.Nitin Ahire 191
INTERFACING 8085  8255
INTERFACING 8085  8255
• Thus we get addresses ,considering don’t cares to
be zero as
Port A =80H
Port B =81H
Port C =82H
CWR =83H
• Then, we give A11,A12,A13 pins to A,B,C inputs of
Decoder to enable 8255 or Chip Select.
• A15 is logic 1 so it is given to active HIGH G1 pin
A14 ,IO/M ‾ are given to active low G2B ‾,G2A ‾
pins.
• Output from Latch is given as A0,A1 pins to 8255
while D0-D7 are given as data inputs.
1-Aug-13 Prof.Nitin Ahire 192
INTERFACING 8085  8255
INTERFACING 8085  8255
8255
8085 3:8 decoder
74373
(AD0-AD7)
D7-D0
A0-A7
/CS
A0
A1
O0
O1
O7
A13
A12
A11
ALE
RD ¯
WR ¯
RD¯
WR¯
G2A G2B G1
A15
A14
IO/M
A
B
C
PA
PB
PC
1-Aug-13 Prof.Nitin Ahire 193
INTERFACING 8085  8255
INTERFACING 8085  8255
Example:
Take data from 8255 port B.
Add FF H .
Output result to port A.
1-Aug-13 Prof.Nitin Ahire 194
MVI A,82H Initialize 8255.
OUT 83H
LDA 81H Take data from port B
ADI FFH Add FF H to data
OUT 80H. OUT Result to port A.
RST1. STOP.
Solution
Solution
1-Aug-13 Prof.Nitin Ahire 195
INTERFACING STEPPER
INTERFACING STEPPER
MOTOR with 8255
MOTOR with 8255
1-Aug-13 Prof.Nitin Ahire 196
Stepper motor
Stepper motor
• Hardware : A stepper motor is a
digital motor. It can be driven by
digital signals motor shown in the
figure ( ckt ) has two phases, with
center tap winding.
• The center taps of these winding are
connected to the +5Volt supply.
• Due to this, motor can be excited by
grounding 4 terminals of the 2
winding.
1-Aug-13 Prof.Nitin Ahire 197
Locking system for stepper
Locking system for stepper
motor
motor
• In the stepper motor it is not
desirable to excite both the ends of
the same winding simultaneously.
• This cancel the flux and motor
winding may damage.
• To avoid this digital clocking system
must be design.
Stepper Motor Programming
Stepper Motor Programming
• MVI A, 80H (CWR)
• OUT 43H (CWR ADDRESS)
• UP:MVI A,88H
• OUT 40H (PORT A ADDRESS)
• CALL 6666H (CALL Delay)
• MVI A,11H
• OUT 40H
• CALL 6666H
• MVI A,22H
• OUT 40H
• CALL 6666H
• MVI A,44H
• OUT 40H
• JMP UP
1-Aug-13 Prof.Nitin Ahire 198
1-Aug-13 Prof.Nitin Ahire 199
Data bit pass to the port A
Data bit pass to the port A
PA0 PA1 PA2 PA3
1 0 1 0 = 0A
1 0 0 1 = 09
0 1 0 1 = 05
0 1 1 0 = 06
1-Aug-13 Prof.Nitin Ahire 200
Data bits
Data bits
• 5000H 0AH
• 5001H 09H
• 5002H 05H
• 5003H 06H
1-Aug-13 Prof.Nitin Ahire 201
Initialized Port A as O/P Port
Initialized Port A as O/P Port
• Program for stepper motor
LXI SP,FFFFH
MVI A,80H ; to make port A as o/p port
OUT CWR
BACK: LXI H,5000H ;HL act as memory pointer
MVI C,04H ;counter for the steps
UP: MOV A,M ;data bits transfer on the lower nibble of
port A
OUT PORT A
CALL DELAY ; delay for the steps
INX H ; increment the HL pair for the next
data bits
DCR C ; decrement the counter
JNZ UP ;check zero flag
JMP BACK ; jump back for continuous loop ( motor
rotation)

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8085 microprocessor 8155, 8255

  • 1. Microprocessor & Microcontroller Microprocessor & Microcontroller - - I I T.E T.E Sem Sem V (Rev) V (Rev) Prof. Nitin Ahire Prof. Nitin Ahire XIE, Mahim XIE, Mahim
  • 2. 1-Aug-13 Prof.Nitin Ahire 2 Overview of Microprocessor Overview of Microprocessor MICROPROCESSOR ( C P U ) MEMORY INPUT OUTPUT (I/O) DEVICE
  • 3. 1-Aug-13 Prof.Nitin Ahire 3 Functional block Diagram Functional block Diagram • INPUT OUTPUT (I/O) DEVICE I/P :Key board, scanner, card reader etc O/P : Display, printer LED etc • MEMORY RAM, ROM • MICROPROCESSOR Central Processor Unit ( CPU ) include ALU, Timing & control unit for synchronizations
  • 4. 1-Aug-13 Prof.Nitin Ahire 4 Number System Number System • Decimal number system (DNS)(10) 0,1,2 ……,9,10 • Binary number system(2) 0,1,10,11,100 • Hexadecimal number system (16) 0,1,2,…..,9,A,B,C,D,E,F,10,11 • Advantages of Hex No over BCD No system (1111 1111)2 (FF)16 (255)10
  • 5. 1-Aug-13 Prof.Nitin Ahire 5 Review for Logic Devices Review for Logic Devices • Tri State Devices : 3 States are logic 1, logic 0 & high impedances state ( Z ) Enable Enable Active high Active Low
  • 6. 6 Tri Tri- -State Buffers State Buffers • An important circuit element that is used extensively in memory. • This buffer is a logic circuit that has three states: – Logic 0, logic1, and high impedance. – When this circuit is in high impedance mode it looks as if it is disconnected from the output completely. The Output is Low The Output is High High Impedance
  • 7. 7 The Tri The Tri- -State Buffer State Buffer • This circuit has two inputs and one output. – The first input behaves like the normal input for the circuit. – The second input is an “enable”. • If it is set high, the output follows the proper circuit behaviour. • If it is set low, the output looks like a wire connected to nothing. Input Output Enable Input Output Enable OR
  • 8. 1-Aug-13 Prof.Nitin Ahire 8 Review for Logic Devices Review for Logic Devices • Buffer e.g. 74LS244(unidirectionl) & 74LS245(Bidirection) • Buffer is a logic CKT that amplifies the current or power • It has one I/P line and one O/P line • The logic level of O/P is the same as that of the I/P • Basically used as to increase the driving capacity of logic CKT simple buffer Active low buffer
  • 9. 1-Aug-13 Prof.Nitin Ahire 9 Introduction to 8085 Introduction to 8085 • CPU built into a single semiconductor chip is called as microprocessor • The microprocessor work as a brain of a computer • It consist of ALU, registers and control unit • The microprocessor are usually characterized by speed, word length (bit), architecture, instruction set Etc
  • 10. 1-Aug-13 Prof.Nitin Ahire 10 8085 Features 8085 Features • 8085 is a 8-bit processor • Frequency of operation a) 8085 --- 3Mhz b) 8085-2 --- 5Mhz c) 8085-1 --- 6Mhz • 8085 has 16 bit address bus to access memory • 8 bit address bus to access I/O location
  • 11. 1-Aug-13 Prof.Nitin Ahire 11 8085 Features 8085 Features • It required only single +5V power supply • 8085 has following registers a) 8 bit accumulator b) six 8- bit general purpose registers c) 8-bit flag register d) 16 –bit PC and SP • It has 5 hardware and 8 software interrupt • 8085 required 6 Mhz crystal • It can transmit and receive serial data
  • 12. 1-Aug-13 Prof.Nitin Ahire 12 8085 PIN DIG 1 X1 40 VCC 2 X2 39 HOLD 3 RESET OUT 38 HLDA 4 SOD 37 CLOCK (OUT) 5 SID 36 RESET IN 6 TRAP 35 READY 7 RST 7.5 34IO/M 8 RST 6.5 33 S1 9 RST 5.5 32 RD 10 INTR 31 WR 11 INTA 30 ALE 12 AD0 29 S0 13 AD1 28 A15 14 AD2 27 A14 15 AD3 26 A13 16 AD4 25 A12 17 AD5 24 A11 18 AD6 23 A10 19 AD7 22 A9 20 VSS 21 A8 8085 (3 MHz ) X1 Crystal 6 MHz X2 PIN DIG 8085
  • 13. 1-Aug-13 Prof.Nitin Ahire 13 Serial I/O Serial I/O ports ports 8085 Functional Pin Diagram A8-A15 AD0- AD7 RST 6.5 RST 6.5 RST 5.5 RST 5.5 INTR INTR RESET IN RESET IN READY READY INTA INTA HOLD HOLD HLDA HLDA SOD SOD TRAP TRAP RST 7.5 RST 7.5 ALE ALE X1 X1 S0 S0 S1 S1 IO/M IO/M RESET OUT RESET OUT CLK OUT CLK OUT WR WR RD RD Externally Externally Initiated Initiated Signal Signal External External Acknowledge Acknowledge Signal Signal H.O.A.B H.O.A.B Multiplexed Multiplexed A/D Bus A/D Bus Control & Control & Status Status Signal Signal SID SID X2 X2 vcc vcc CLK CKT & CLK CKT & P.S. P.S.
  • 14. 1-Aug-13 Prof.Nitin Ahire 14 Interrupt control Serial I/O Control W 8 Z 8 D E C B H L SP 16 PC 16 Internal latch F/F 5 ALU 8 Temp. Reg Accumulator 8 I.R. 8 Inst. Decoder & M/C Encoder Timing and control unit Add. Buffer A/D. Buffer 8 bit Internal BUS AD0-AD7 A15-A8 SID SOD INTR INTA RST 7.5 to 5.5 TRAP X1 X2 READY WR RD ALE S0 S1 IO/M HLDA HOLD CLK OUT RESET IN RESET OUT P.S +5V GND DECODRE MUX
  • 15. 1-Aug-13 Prof.Nitin Ahire 15 Interrupt control Serial I/O Control W 8 Z 8 D E C B H L SP 16 PC 16 Internal latch F/F 5 ALU 8 Temp. Reg 8 Accumulator 8 I.R. 8 Inst. Decoder & M/C Encoder Timing and control unit Add. Buffer A/D. Buffer 8 bit Internal BUS AD0-AD7 A15-A8 SID SOD INTR INTA RST 7.5 to 5.5 TRAP X1 X2 READY WR RD ALE S0 S1 IO/M HLDA HOLD CLK OUT RESET IN RESET OUT P.S +5V GND DECODRE MUX
  • 16. 1-Aug-13 Prof.Nitin Ahire 16 Registers Registers • The register contains a set of binary storage cells/Flip Flop • 6 general purpose 8 bit Reg. B,C,D,E,H&L (or can be used as pair of 16 bit reg. like BC,DE,HL) • W & Z (Temp reg.) • 16 bit Reg are PC And SP • 8 bit flag register B C D E H L SP PC W Z A F
  • 17. 1-Aug-13 Prof.Nitin Ahire 17 Interrupts Interrupts • Hardware interrupt Trap (Non Mask able) (vectored) RST 7.5(Mask able) (vectored) RST 6.5 (Mask able) (vectored) RST 5.5(Mask able) (vectored) INTR (Mask able) (Non vectored) • Software interrupt RST 0 to RST 7 All are vectored interrupt
  • 18. 1-Aug-13 Prof.Nitin Ahire 18 Interrupts Interrupts • 8085 has 5 hardware interrupts 8 software interrupts • All software interrupt are vectored • Out of 5 hardware interrupt 4 are vector and 1 is non vector also 4 are maskable and one is non mask able
  • 19. 1-Aug-13 Prof.Nitin Ahire 19 Flags Register ( 8 bit ) Flags Register ( 8 bit ) D7 D6 D5 D4 D3 D2 D1 D0 • S –sign flag (for signed number) if D7=1 the number in accumulator will be –ve number D7=0 the number in accumulator will be +ve number • Z – zero flag if D6=1The zero flag is set if the result in accumulator is zero S Z -- AC - P -- C
  • 20. 1-Aug-13 Prof.Nitin Ahire 20 Flags Register ( 8 bit ) Flags Register ( 8 bit ) D7 D6 D5 D4 D3 D2 D1 D0 AC – Auxiliary carry in the arithmetic operation, when the carry is generated digit D3 and passed on digit D4 the AC flag is set P – parity flag after an arithmetic and logical operation, if the result has even number of ones the flag is set if it has odd numbers of ones, the flag is reset CY – Carry flag if an arithmetic operation results in carry, the carry flag is set otherwise it is reset. The carry flag also serves as a barrow flag for subtraction S Z AC P C
  • 21. 1-Aug-13 Prof.Nitin Ahire 21 Subtraction process in 8085 Subtraction process in 8085 • 1 : find 1’s complement of the subtrahend • 2 : find 2’s complement of the subtrahend • 3 : Adds 2’s complement of the subtrahend to the minuend • 4 : complements the CY flag. These steps are invisible to the user, only the result is available to the user. For unsigned number if CY is reset the result is positive and if CY is set the result is negative(2’complement)
  • 22. 1-Aug-13 Prof.Nitin Ahire 22 Sign flag (used only for sign No.) Sign flag (used only for sign No.) • Sign flag: This flag is used with signed numbers in the arithmetic operation. With sign number, bit D7 is reserved for indicating the sign and the remaining 7 bit are used to represent the magnitude of a number • Sign flag is irrelevant for unsigned number
  • 23. 1-Aug-13 Prof.Nitin Ahire 23 D D – – F/F (Latch) F/F (Latch) D F/F Latch clk I/P O/P clk I/P Q Q
  • 24. 1-Aug-13 Prof.Nitin Ahire 24 De multiplexing Of AD0 De multiplexing Of AD0- -AD7 AD7 8085 Latch AD0-AD7 D0-D7 ALE A0-A7 A8-A15 IO/M
  • 25. De multiplexing (AD0 De multiplexing (AD0- -AD7) AD7) 1-Aug-13 Prof.Nitin Ahire 25
  • 26. 1-Aug-13 Prof.Nitin Ahire 26 De multiplexing Of AD0 De multiplexing Of AD0- -AD7 AD7 8085 Latch AD0-AD7 D0-D7 ALE A0-A7 IO/M
  • 27. 1-Aug-13 Prof.Nitin Ahire 27 Differentiate between IO/M Differentiate between IO/M 8085 Latch AD0-AD7 A0-A7 D0-D7 IO/M Memory IO device ALE A8-A15 A0-A7 1
  • 28. 1-Aug-13 Prof.Nitin Ahire 28 1-Aug-13 Prof.Nitin Ahire 28 Differentiate between IO/M Differentiate between IO/M 8085 Latch AD0-AD7 A0-A7 D0-D7 IO/M Memory IO device ALE A8-A15 A0-A7 0
  • 29. 1-Aug-13 Prof.Nitin Ahire 29 Control & Status Signals Control & Status Signals S0 S1
  • 30. 1-Aug-13 Prof.Nitin Ahire 30 Generation of control Signals Generation of control Signals
  • 31. 1-Aug-13 Prof.Nitin Ahire 31 Instruction, Data format Instruction, Data format and storage and storage • Part of instruction each instruction has two parts 1 opcode: one is the task to be perform (operational code) 2 operand: data to be operated on (data) The data can be specified in the various form it may in the memory or I/O or in the instruction it self.
  • 32. 1-Aug-13 Prof.Nitin Ahire 32 Opcode Opcode • Opcode : operational code • Operand : Data • Mnemonics : Instructions Memory Locations Opcode Mnemonics Operand 2000 3E MVI A, 20 2001 20 2002 06 MVI B, 12 2003 12 2004 4F MOV C, A
  • 33. 1-Aug-13 Prof.Nitin Ahire 33 ALU (A) INST. DECODER CONTROL LOGIC B C D E H L SP PC (2000) 2000 2001 2002 2003 2004 3E MERD MEMORY LOCATION ADD BUS Internal Data BUS DECODER DATA BUS 3E 20 06 12 4F
  • 34. 1-Aug-13 Prof.Nitin Ahire 34 ALU (A) INST. DECODER CONTROL LOGIC B C D E H L SP PC (2001) 2000 2001 2002 2003 2004 20 MERD MEMORY LOCATION ADD BUS Internal Data BUS DECODER DATA BUS 3E 20 06 12 4F 3E
  • 35. 1-Aug-13 Prof.Nitin Ahire 35 ALU (A) INST. DECODER CONTROL LOGIC B C D E H L SP PC (2002) 2000 2001 2002 2003 2004 06 MERD MEMORY LOCATION ADD BUS Internal Data BUS DECODER DATA BUS 3E 20 06 12 4F 20
  • 36. 1-Aug-13 Prof.Nitin Ahire 36 ALU (A) INST. DECODER CONTROL LOGIC B C D E H L SP PC (2003) 2000 2001 2002 2003 2004 12 MERD MEMORY LOCATION ADD BUS Internal Data BUS DECODER DATA BUS 3E 20 06 12 4F 20
  • 37. 1-Aug-13 Prof.Nitin Ahire 37 ALU (A) INST. DECODER CONTROL LOGIC B C D E H L SP PC (2004) 2000 2001 2002 2003 2004 4F MERD MEMORY LOCATION ADD BUS Internal Data BUS DECODER DATA BUS 3E 20 06 12 4F 20
  • 38. 1-Aug-13 Prof.Nitin Ahire 38 Instruction classification Instruction classification • “Instruction” is a command to the microprocessor to perform a given task on specified data”. • The instruction can be classified into following fundamental categories 1 Data transfer 2 Arithmetic & Logical operation 3 Branching operation 4 Machine control operation
  • 39. 1-Aug-13 Prof.Nitin Ahire 39 Instruction classification Instruction classification • 1 Data transfer (copy) basically used to copies data from source to destination without modifying the content of the source like, Opcode operand MOV rd, rs MVI r, 8-bit IN 8 bit port add. OUT 8 bit port add.
  • 40. 1-Aug-13 Prof.Nitin Ahire 40 Instruction classification Instruction classification • 1 Data transfer (copy) • LXI Rp, 16-bit add. • MOV R,M • MOV M,R • LDA 16-bit add. • STA 16-bit add. • LDAX R* • STAX R* • LHLD 16-bit add (1st memory location copy to L & 2nd memory location to H) • SHLD 16-bit add *R – Register pair
  • 41. LHLD 4000H & SHLD 4000H LHLD 4000H & SHLD 4000H H L memory » 4000 » 4001 1-Aug-13 Prof.Nitin Ahire 41 03 70 03 70
  • 42. 1-Aug-13 Prof.Nitin Ahire 42 Instruction classification Instruction classification • Arithmetic operation These instruction perform arithmetic operation such as addition subtraction, increment, decrement. • ADD R • ADI data • ADC R • ADC M • ACI data • DAD Rp
  • 43. 1-Aug-13 Prof.Nitin Ahire 43 Instruction classification Instruction classification • SUB R • SUB M • SBB R • SBB M • SUI Data • SBI Data • DAA
  • 44. 1-Aug-13 Prof.Nitin Ahire 44 Instruction classification Instruction classification • INR R • DCR R • INR M • DCR M • INX Rp • DCX Rp
  • 45. 1-Aug-13 Prof.Nitin Ahire 45 Instruction classification Instruction classification • Logical instruction. These instruction perform various logical operation with the content of the accumulator e.g. 1) AND,OR,EX-OR(ANA R,ANI Data, XRA R) 2) Rotate (RAL,RAR,RLC,RRC) 3) Compare (CMP B,CPI Data) 4) Complement (CMC, CMA,STC)
  • 47. More about More about CMP R CMP R instruction instruction • CMP R • This instruction compare the contents of accumulator with the contents of register specified • The operation of comparing is performed by subtracting (Acc. – Reg.) • The contents of Acc or Reg. are not altered • The result of comparison is indicated by flags When A>R ; CY=0 & Z=0 When A=R ; CY=0 & Z=1 When A<R ; CY=1 & Z=0 1-Aug-13 Prof.Nitin Ahire 47
  • 48. 1-Aug-13 Prof.Nitin Ahire 48 Instruction classification Instruction classification • Branching operation These group of instruction alter the sequence of program execution either conditionally or unconditionally e.g. JUMP (conditionally or unconditionally) CALL & RET (conditionally or unconditionally)
  • 49. 1-Aug-13 Prof.Nitin Ahire 49 Instruction classification Instruction classification • Machine control instruction These instruction control the machine function such as Halt (HLT), interrupt (RST 1) or do noting (NOP)
  • 50. More about More about DAA DAA instruction instruction • Decimal Adjust Accumulator • If lower nibble of A > 9 or AC =1 then, lower nibble of A = lower nibble of A + 06H. • If Higher nibble of A > 9 or CY =1 then, Higher nibble of A = Higher nibble of A + 06H. 1-Aug-13 Prof.Nitin Ahire 50
  • 51. • E.g. 1) 55 h + 06 h = 5B h 55 + 06 = 61 D 1-Aug-13 Prof.Nitin Ahire 51
  • 52. Programming Programming • Write a generalized program for addition of two 8 -bit numbers and get the result in BCD • 1st No. is located at memory location C200h • 2ndNo. is located at memory location C201h • Save the result at next location C202 1-Aug-13 Prof.Nitin Ahire 52
  • 53. 1-Aug-13 Prof.Nitin Ahire 53 Addition of two 8 bit Addition of two 8 bit number number located at C200h & C201h located at C200h & C201h LXI H, C200H; load HL pair by C200h MOV A,M; Move 1st No. in the Reg. A INX H ; increment the HL pair by 1 ADD M; Add A+(M)=A DAA INX H; increment the HL pair by 1 MOV M,A; move the result in M HLT; Stop
  • 54. Programming Programming • Write a generalized program for addition of two 8 -bit numbers located at (with carry) • 1st No. is located at memory location C200h • 2ndNo. is located at memory location C201h • Save the result at next memory location C202h • And save the status of carry at next memory location C203h 1-Aug-13 Prof.Nitin Ahire 54
  • 55. Addition of two 8 Addition of two 8- -bit numbers bit numbers • MVI C,00H ; use reg. C to know the status of CY flag • LXI H,C200h ; set memory pointer at C200h • MOV A,M ; transfer the 1st No. from memory to Acc. • INX H; go to the next memory location point to 2nd No. • ADD M; Add A+M =A • JNC Down (Put 16-bit memory address of target instruction) • INR C ; If there is carry increment the reg. C by 1 • Down: STA C202H ; load the Acc. Data at C202h • MOV A,C ; load Carry to Acc • STA C203H ; load Acc. Data (carry) at C203h • RST 1/ HLT ; Stop 1-Aug-13 Prof.Nitin Ahire 55
  • 56. Programming Programming • Write a generalized program for addition of two 16-bit numbers located at (with carry) • 1st No. is located at memory location C200h & C201h • 2ndNo. is located at memory location C202h & C203h • Save the result at next memory location C204h & C205h • And save the status of carry at next memory location C206h 1-Aug-13 Prof.Nitin Ahire 56
  • 57. 1-Aug-13 Prof.Nitin Ahire 57 Addition of two 16 bit number Addition of two 16 bit number MOV C,00h ; Reg. C for to save the status of carry flag LHLD C200H ; Here C200h-L=34, C201h H=12 XCHG ; exchange HL with DE LHLD C202H ; Here L= 21, H=43 DAD D ; DE+HL = HL JNC down INR C Down: SHLD C204H ; store the result MOV A,C STA C206H ; store the carry HLT ; stop
  • 58. Find the largest number from the series of 10 Find the largest number from the series of 10 numbers numbers • The 10 numbers are saved from memory location 8500h to 8509h • Save the largest number at memory location 8550h 1-Aug-13 Prof.Nitin Ahire 58 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 99 66 AA DF DD 97 F3 44 FE 67 8550 XX
  • 59. Find the largest number from the series of 10 numbers Find the largest number from the series of 10 numbers • MVI C,O9H ; counter • LXI H,8500H ; memory pointer • MOV A,M; move 1ST No. to Acc. • UP:INX H ; Increment HL pair point to 2nd No. • CMP M; Compare 1st No. with 2nd No. • JNC DOWN; Jump on no carry ( A > M) • MOV A,M ; If carry change the No. ( A < M) • DOWN:DCR C ; Decrement the counter by 1 • JNZ UP; Check for zero flag ( counter = zero) • STA 8550H ; Save the result ( Acc to 8850h) • HLT; Stop 1-Aug-13 Prof.Nitin Ahire 59
  • 60. Memory location Opcode, Operand Mnemonics Remark 8000 0E ,09 MVI C,09H COUNTER 8002 21,00,85 LXI H,8500H MEMORY POINTER 8005 7E MOV A,M 1ST No. to Acc. 8006 23 UP:INX H Increment HL pair 8007 BE CMP M Compare 8008 D2,0C,80 JNC DOWN Jump on no carry 800B 7E MOV A,M If carry change the No. 800C 0D DOWN:DCR C Decrement the counter 800D C2,06,80 JNZ UP Check for zero flag 8010 32,50,85 STA 8550H Save the result 8013 76 HLT Stop 1-Aug-13 Prof.Nitin Ahire 60
  • 61. 1-Aug-13 Prof.Nitin Ahire 61 8550 FE • After the execution of program status of memory location
  • 62. Block Transfer Block Transfer • Write a program to transfer a block of data from 8500H to 8509H. Store the data from 8570H to 8579H . 1-Aug-13 Prof.Nitin Ahire 62 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 99 66 AA DF DD 97 F3 44 FE 67 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 xx xx xx xx xx xx xx xx xx xx
  • 63. Program Program 1-Aug-13 Prof.Nitin Ahire 63 LXI H ,8500H ; source location LXI H ,8500H ; source location LXI B LXI B ,8570H ; Destination location ,8570H ; Destination location MVI MVI D,0AH ; Counter D,0AH ; Counter UP UP MOV MOV A,M ; 1 A,M ; 1st st No. transfer in Acc. No. transfer in Acc. STAX B; STAX B; Save Acc. Content at memory location pointed by BC Save Acc. Content at memory location pointed by BC Reg Reg INX INX H H INX B INX B DCR D DCR D JNZ JNZ UP UP HLT HLT
  • 64. • After the execution of program status of memory location 1-Aug-13 Prof.Nitin Ahire 64 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 99 66 AA DF DD 97 F3 44 FE 67 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 99 66 AA DF DD 97 F3 44 FE 67
  • 65. Draw a minimum mode system of 8085 Draw a minimum mode system of 8085 • The minimum number of components required to make a system using 8085 is called minimum system or minimum mode system. 1-Aug-13 Prof.Nitin Ahire 65
  • 66. 1-Aug-13 Prof.Nitin Ahire 66 8 0 8 5 74 LS 373 74 LS 138 Memory I/O MERD MEWR IORD IOWR A0-A15 D0-D7 A0-A7 ALE AD0-AD7 A8-A15 RD IO/M WR TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA READY SOD SID RESET OUT RESET IN VCC Minimum mode system Minimum mode system(8085 (8085) ) X1 X2
  • 67. 1-Aug-13 Prof.Nitin Ahire 67 Instruction classification Instruction classification • The 8085 instruction set is classified into the following 3 group according to word size or byte size 1) 1- byte instruction 2) 2- byte instruction 3) 3 –byte instruction
  • 68. 1-Aug-13 Prof.Nitin Ahire 68 1 1- - byte instruction byte instruction • A 1- byte instruction includes the opcode and the operand in the same byte e.g. Opcode operand hex code 1 MOV C, A (4F) (opcode) 2 ADD B (80) (Data) each instruction required 1 memory location ( 8-bit)
  • 69. 1-Aug-13 Prof.Nitin Ahire 69 2 2- - byte instruction byte instruction • In the 2- byte instruction the first byte specifies the operation code and the second byte specifies the operand e.g. Opcode operand hex code MVI A, 12H 3E (opcode) 12 (Data) These instruction required 2 memory location
  • 70. 1-Aug-13 Prof.Nitin Ahire 70 3 3- - byte instruction byte instruction • In 3-byte instruction the first byte specifies the opcode and the following 2 bytes specify the 16- bit address e.g. Opcode operand hex code LDA 2050 3A (Opcode) 50 (Data) 20 (Data) Note the second byte is the lower address and the third byte is the high order address These instruction required 3 memory location
  • 71. 1-Aug-13 Prof.Nitin Ahire 71 Addressing Addressing mode mode • The different methods (mode) to select the operands or address are called addressing mode • For 8085 they are 1 Immediate addressing 2 Register addressing 3 Direct addressing 4 Indirect addressing 5 Implied addressing
  • 72. 1-Aug-13 Prof.Nitin Ahire 72 Addressing mode Addressing mode 1 Immediate addressing • In the immediate addressing mode the data is specified in the instruction it self. • The immediate addressing mode instruction are either 2- byte or 3- byte long. • The instruction contain the letter “I” indicate the immediate addressing mode. e.g. 1 MVI A,12h 2 LXI H,2000h
  • 73. 1-Aug-13 Prof.Nitin Ahire 73 Addressing mode Addressing mode 2 Register addressing mode • In register addressing mode the source and destination operands are general purpose registers • The register addressing mode instructions are generally of 1 –byte e.g. 1 MOV A,B 2 ADD B 3 PCHL 4 XRA A
  • 74. 1-Aug-13 Prof.Nitin Ahire 74 Addressing mode Addressing mode 3 Direct addressing • In the direct addressing mode the 16 bit address of the data or operand is directly specified in the instruction • These instruction are 3 –byte instruction. e.g. 1 LDA 2000h 2 STA 2060h
  • 75. 1-Aug-13 Prof.Nitin Ahire 75 Addressing mode Addressing mode 4 Indirect addressing • In the Indirect addressing mode the instruction reference the memory through the register pair i.e. the memory address where the data is located is specified by the register pair e.g.1 MOV A,M 2 LDAX B
  • 76. 1-Aug-13 Prof.Nitin Ahire 76 Addressing mode Addressing mode 5 Implied addressing • The Implied mode of addressing does not required any operand • The data is specified within the opcode it- self • Generally these instructions are 1-byte instruction • The data is supposed to be present in the Accumulator e.g. 1 RAL 2 CMC
  • 77. 1-Aug-13 Prof.Nitin Ahire 77 Timing diagram Timing diagram • For better understanding of each instruction it is very essential to understand the Timing diagram of each instruction. • The graphical representation of each instruction with respective to time i.e. CLOCK is called “Timing Diagram”
  • 78. 1-Aug-13 Prof.Nitin Ahire 78 Timing diagram Timing diagram • Instruction cycle (IC) : The essential step required by CPU to fetch and execute an instruction is called IC IC=FC+EC • Machine cycle (MC) : Time required by microprocessor to complete the operation of accessing memory or I/O device is called MC. • T –state :Each clock cycle is called T-state
  • 79. 1-Aug-13 Prof.Nitin Ahire 79 Timing diagram • The µP operates with reference to clock signal. • Each clock cycle is called a T state and a collection of several T states gives a machine cycle. • Important machine cycles are : 1. Op-code fetch. 2. Memory read. 3. Memory write. 4. I/O-read. 5. I/O write.
  • 80. Timing diagram Timing diagram • Timing diagram for the 1- byte instruction • single MC = opcode fetch 1-Aug-13 Prof.Nitin Ahire 80 Memory location /(PC) Opcode Instruction 2005 4F MOV C,A
  • 82. 1-Aug-13 Prof.Nitin Ahire 82 Control & Status Signals Control & Status Signals S0 S1
  • 83. 1-Aug-13 Prof.Nitin Ahire 83 Timing diagram Timing diagram • Step 1 (State T1) In the state, 8085 sends the status signals, IO/M=0, S1=1 and S0=1 • The 8085 send a 16 bit address on A8-A15 and AD0- AD7 • The high order bytes of PC (20) is placed on the A8-A15 lines, and it remain there upto T3 state. • The low order bytes of PC (05) placed on the AD0- AD7,lines which remain there only for T1 • During this state, ALE gives a positive pulse signal is used to latch the add A0-A7. • No control signal is generated in state. ( RD & WR )
  • 84. 1-Aug-13 Prof.Nitin Ahire 84 Timing diagram Timing diagram • Step2 (T2): The content of PC lower byte will disappear on AD0-AD7 lines, so the same line can be used as data line . The contents of A0-A7 are still available for memory from external Latch. • The control signal RD is made low by the processor which enables the read ckt of addressed memory device. • Then the memory device send the content on the data bus D0-D7 (4F) • In addition to these the processor increments PC content by one
  • 85. 1-Aug-13 Prof.Nitin Ahire 85 Timing diagram Timing diagram • Step3 (T3): during this cycle the data from memory (opcode) is transfer in the instruction Reg. and RD control signal made HIGH
  • 86. 1-Aug-13 Prof.Nitin Ahire 86 Timing diagram Timing diagram Step 4 (T4): the microprocessor perform only internal operation. The opcode decoded by the CPU and 8085 decide 1) Whether it should enter T5 and T6 states or not 2) How my bytes of instruction it is ? If instruction doesn’t required T5 &T6 states, it go to the next MC
  • 87. 1-Aug-13 Prof.Nitin Ahire 87 Timing diagram Timing diagram • Step 5 (T5 &T6): T5 and T6 states, states are required to complete decoding and some operations inside the 8085 it depend on the type of instruction
  • 88. 1-Aug-13 Prof.Nitin Ahire 88 Timing diagram Timing diagram • Following instruction required T5 & T6 states for the opcode fetch MC 1 CALL 2 CALL conditional 3 DCX Rp 4 INX Rp 5 PCHL 6 SPHL 7 PUSH Rp 8 RET conditional All other instruction except the above instruction required opcode fetch of T1 to T4 states only.
  • 89. 1-Aug-13 Prof.Nitin Ahire 89 Timing diagram Timing diagram • Machine cycle (type) Few more MC 1 opcode fetch 2 operand fetch 3 Memory read 4 Memory write 5 I/O read 6 I/O write 7 Interrupt Ack M-cycle 8 Ideal M-cycle
  • 90. Timing diagram Timing diagram • Timing diagram for the 2- byte instruction • 2 MC = 1 opcode fetch & 2 Data fetch 1-Aug-13 Prof.Nitin Ahire 90 Memory location /(PC) Opcode Instruction 2000 06 MVI B , 43 h 2001 43
  • 92. 1-Aug-13 Prof.Nitin Ahire 92 Stack control and branching group Stack control and branching group • Stack is the reserved area of the memory in RAM where temporary information may be stored • Stack pointer (SP): an 16-bit SP is used to hold the address of the most recent stack entry. It work on the principle of LIFO or FILO.
  • 93. STACK MEMORY STACK MEMORY 1-Aug-13 Prof.Nitin Ahire 93 STACK Memory (Reserve area) Total Memory Size Reserve area
  • 94. 1-Aug-13 Prof.Nitin Ahire 94 Stack Related Instructions Stack Related Instructions • LXI SP,16-bit address • LXI SP, 2000 h • LXI SP,FFFF h • PUSH Rp(PUSH B, PUSH H, PUSH D,PUSH PSW) • POP RP (POP B, POP D,POP H,POP PSW) • SPHL ( HL SP) • XTHL ( HL SP) • PCHL ( HL PC)
  • 95. 1-Aug-13 Prof.Nitin Ahire 95 Stack Related Instructions Stack Related Instructions • PUSH B Let BC=3010, B=30h, C=10h suppose SP initialized at FFFF h after execution of instruction PUSH B SP=SP-1=FFFF-1=FFFE B [FFFE] =30h again SP=SP-1=FFFE-1=FFFD C [FFFD]=10h SP=[FFFD] New location of SP
  • 96. 1-Aug-13 Prof.Nitin Ahire 96 PUSH H Contents on the stack & in the register after the PUSH instruction 42 42 F2 F2 F C E L A B D H SP F2 42 X 2097 2098 2099 2097 8085 Register Memory Initially SP at 2900 & H=42 , L=F2 1 2
  • 97. 1-Aug-13 Prof.Nitin Ahire 97 Stack Related Instructions Stack Related Instructions • POP B initially B=20, C=40h SP at=[FFFD]=10h at=[FFFE]=30h After execution of POP B SP=[FFFD]=10h [C] SP=SP+1=[FFFE]=30h [B] Again SP=SP+1=[FFFF] Now B=30h, C=10h and SP=[FFFF]
  • 98. POP H POP H 1-Aug-13 Prof.Nitin Ahire 98 Initially SP at 2097 After POP H , H= 42 L= F2 Contents on the stack and in the registers after the POP instruction 42 F2 2099 F2 2097 42 2098 X 2099 F C E L A B D H SP 8085 Register 1 2
  • 99. 1-Aug-13 Prof.Nitin Ahire 99 Subroutines Subroutines • Whenever we need to use a group of instruction several times throughout a program there is a way we can avoid having to write the group of instructions each time we want to use them. • One way is to write the group of instruction separately, Called Subroutines • Whenever we want to execute that group of instruction we can call that Subroutine. • The return address has to be stored back on the stack memory
  • 100. 1-Aug-13 Prof.Nitin Ahire 100 Subroutines Subroutines e.g. 6FFD 31 LXI SP, FFFF h FF FF 7000 CD CALL C200h 7001 00 7002 C2 7003 Next instruction When this instruction is executed PC contents 7003h (next instruction) will stored on to the stack and microprocessor will load PC with C200h and start executing instruction from C200h
  • 101. 1-Aug-13 Prof.Nitin Ahire 101 Subroutines Subroutines • If SP= FFFF h • CALL C200. PC stack (memory) (SP-1)=Pc H FFFF (SP-2)=Pc L FFFE SP=SP-2 FFED PC=new C200 70 03 03 70
  • 102. 1-Aug-13 Prof.Nitin Ahire 102 Subroutines Subroutines • Conditional Call instructions When condition is true, then CALL at NEW address else execute the next instruction of the program 1) CZ Add 2) CNZ Add 3) CP Add 4) CM Add 5) CPO Add 6) CPE Add 7) CC Add 8) CNC Add If condition false 9T True16T
  • 103. 1-Aug-13 Prof.Nitin Ahire 103 Subroutines Subroutines • RET unconditionally 1 SP (PC L) PC Stack 2 SP+1 (PC H) 3 SP+2=SP Initially SP at FFFD After execution of RET SP=FFFF 70 03 03 70 FFFD FFFE FFFF
  • 104. 1-Aug-13 Prof.Nitin Ahire 104 Subroutines Subroutines • RET conditionally When condition is true, then RET at the main program 1) RZ 2) RNZ 3) RP 4) RM 5) RPO 6) RPE 7) RC 8) RNC
  • 105. 1-Aug-13 Prof.Nitin Ahire 105 Nested Subroutines Nested Subroutines • Whenever one subroutine calls another subroutine in order to complete a specific task, the operation is called as nesting. • The First subroutine may call the second subroutine and in turn the second subroutine may called first or third subroutine such routines called NESTED subroutines
  • 106. 1-Aug-13 Prof.Nitin Ahire 106 Nested subroutines Nested subroutines . sub 1 sub 2 . . . call sub 1 call sub 2 . . . . . . . . RET RET
  • 107. 1-Aug-13 Prof.Nitin Ahire 107 • There are two kinds of subroutines 1) Re-entrant subroutines. 2) Recursive subroutines. Nested Subroutines Nested Subroutines
  • 108. 1-Aug-13 Prof.Nitin Ahire 108 Re entrant Re entrant Subroutines Subroutines 1)Re-entrant Subroutine It may happened a Subroutine ‘1’ is called from main program and ‘2’ Subroutine is called from Subroutine ‘1’ and Subroutine ‘2’ may called Subroutine ‘1’ then the program re entrant in Subroutine ‘1’ this is called re-entrant Subroutine
  • 109. 1-Aug-13 Prof.Nitin Ahire 109 Re entrant Re entrant subroutine subroutine • Main Program • Next • line SUB 1 SUB 2 CALL CALL RET RET
  • 110. 1-Aug-13 Prof.Nitin Ahire 110 Recursive Recursive subroutine subroutine • A procedure which called it self is called a recursive subroutine • The recursive subroutine loop takes long time to execute • In this type of subroutine we normally define N ( recursive depth) it is decrement by one after each subroutine is call until N=0
  • 111. 1-Aug-13 Prof.Nitin Ahire 111 Recursive Recursive subroutine subroutine • Main Program N=3 N=2 N=1 • Next • line SUB 1 SUB 2 CALL CALL RET RET RET SUB 3 CALL
  • 112. 1-Aug-13 Prof.Nitin Ahire 112 Software Software Delay Delay • Delay : operating after an some time interval. • Microprocessor take fixed amount of time to execute each instruction • Microprocessor driven by fixed frequency (crystal) • So using instruction we can generate a Delay.
  • 113. 1-Aug-13 Prof.Nitin Ahire 113 Software Delay Software Delay • E.g. delay using NOP instruction NOP ( 1-byte instruction- 4T state) assume crystal freq= 4Mhz.. CLK freq = 2Mhz (T=0.5 microsecond) Delay using NOP = 4 X 0.5 microsecond = 2.0 microsecond
  • 114. 1-Aug-13 Prof.Nitin Ahire 114 Software Delay Software Delay • If we want the more delay than 4T,then we go on increasing NOP after NOP. • Impractical (size of program increase)
  • 115. 1-Aug-13 Prof.Nitin Ahire 115 Delay using 8 Delay using 8 – –bit counter bit counter Delay Initializes 8-bit counter Decrement counter RET yes No
  • 116. 1-Aug-13 Prof.Nitin Ahire 116 Delay using 8 Delay using 8 – –bit counter bit counter • MVI C, Count 7T up: DCR C 4T JNZ :up 10T/7T RET 10T The loop is executed ( count-1 ) times
  • 117. 1-Aug-13 Prof.Nitin Ahire 117 Delay using 8 Delay using 8 – –bit counter bit counter • Formula for delay value Td=[ M + {(count) X N} -3 ] T M=No. of T state out side the loop N=No. of T state inside the loop M=10+7=17 T; N=10+4=14T
  • 118. 1-Aug-13 Prof.Nitin Ahire 118 Delay using 8 Delay using 8 – –bit counter bit counter JNZ instruction required 10 or 7 T state based on the condition ( Z=0 or 1) (when condition is satisfied it take 10T state and if not satisfied it take 7T state) so 3 T must be subtracted from total value
  • 119. 1-Aug-13 Prof.Nitin Ahire 119 Delay using 8 Delay using 8 – –bit counter bit counter • Td max= [17+[ {255} X 14 ] -3] T = 3584 T = 3584 X 0.5 microsecond = 1792 microsecond (FF)=(255)
  • 120. 1-Aug-13 Prof.Nitin Ahire 120 Delay using 16 bit counter Delay using 16 bit counter • LXI B, (count)H 10T up: DCX B 6T MOV A,C 4T ORA B 4T JNZ :up 10/7T RET 10T DCX not affect the zero flag.
  • 121. 1-Aug-13 Prof.Nitin Ahire 121 Delay using 16 bit counter Delay using 16 bit counter Td=[ M + {(count) X N} -3 ] T M=No. of T state out side the loop N=No. of T state inside the loop M=20 T; N=24T
  • 122. 1-Aug-13 Prof.Nitin Ahire 122 Delay using 16 bit counter Delay using 16 bit counter • Td max= [20+[ {65535}X 24 ] -3] T = 1572857 T =1572857 X 0.5 microsecond = 78642 microsecond (FFFF)=(65535) largest count.
  • 123. 1-Aug-13 Prof.Nitin Ahire 123 Memory and I/O interfacing Memory and I/O interfacing • Types of memory 1 ROM (EPROM) 2 RAM
  • 124. 1-Aug-13 Prof.Nitin Ahire 124 Memory structure & it’s Memory structure & it’s requirement's requirement's • The read write memories consist of an array of registers, where in each register has a unique address • M=No. of register • N=No. of bits MXN I/P decoder I/P Buffer O/P Buffer A1 A0 AM Data i/Ps Data o/p s WR RD CS
  • 125. 1-Aug-13 Prof.Nitin Ahire 125 Memory structure & it’s Memory structure & it’s requirement's requirement's • If the memory having 13 address line and 8 data lines, then it can access 213 address lines = 8192 and N= 8 bit or 1-byte • No of address lines of the ‘up’ is to be used to find how much memory array can be access by that processor.
  • 126. 1-Aug-13 Prof.Nitin Ahire 126 No. of address line No. of address line required to accessed the memory required to accessed the memory • No of lines size of memory 1 21= 2 2 22= 4 3 23= 8 4 24 =16 10 210= 1K= 1024 11 211 =2K= 2048 16 216 =64K= 65536
  • 127. 1-Aug-13 Prof.Nitin Ahire 127 EPROM IC available in the EPROM IC available in the market market IC NO size 2716 2k X 8 2732 4k X 8 2764 8k X 8 27128 16k X 8 27256 32K x 8 27512 64k X 8
  • 128. 1-Aug-13 Prof.Nitin Ahire 128 RAM IC available in the RAM IC available in the market market IC NO size 6116 2k X 8 6264 8k X 8 62512 64k X 8 2114 1k X 4
  • 129. 1-Aug-13 Prof.Nitin Ahire 129 Comparison between full Comparison between full and partial decoding and partial decoding • full decoding 1) Also referred to be as absolute decoding 2) All address lines are consider 3) More hardware required • partial decoding 1) Also referred to be as liner decoding 2) Few address lines are ignored 3) Decoder hardware is simple
  • 130. 1-Aug-13 Prof.Nitin Ahire 130 8085 Memory Interfacing
  • 131. 1-Aug-13 Prof.Nitin Ahire 131 Memory and I/O interfacing Memory and I/O interfacing • Types of memory 1 ROM (EPROM) 2 RAM
  • 132. 1-Aug-13 Prof.Nitin Ahire 132 Memory structure & it’s Memory structure & it’s requirement's requirement's • The read write memories consist of an array of registers, where in each register has a unique address • M=No. of register • N=No. of bits MXN I/P decoder I/P Buffer O/P Buffer A1 A0 AM Data i/Ps Data o/p s WR RD CS
  • 133. 1-Aug-13 Prof.Nitin Ahire 133 Memory structure & it’s Memory structure & it’s requirement's requirement's • If the memory having 13 address line and 8 data lines, then it can access 213 address lines = 8192 and N= 8 bit or 1-byte • No of address lines of the ‘up’ is to be used to find how much memory array can be access by that processor.
  • 134. 1-Aug-13 Prof.Nitin Ahire 134 No. of address line No. of address line required to accessed the memory required to accessed the memory • No of lines size of memory 1 21= 2 2 22= 4 3 23= 8 4 24 =16 10 210= 1K= 1024 11 211 =2K= 2048 16 216 =64K= 65536
  • 135. 1-Aug-13 Prof.Nitin Ahire 135 EPROM IC available in the EPROM IC available in the market market IC NO size 2716 2k X 8 2732 4k X 8 2764 8k X 8 27128 16k X 8 27256 32K x 8 27512 64k X 8
  • 136. 1-Aug-13 Prof.Nitin Ahire 136 RAM IC available in the RAM IC available in the market market IC NO size 6116 2k X 8 6264 8k X 8 62512 64k X 8 2114 1k X 4
  • 137. 1-Aug-13 Prof.Nitin Ahire 137 Comparison between full Comparison between full and partial decoding and partial decoding • full decoding 1) Also referred to be as absolute decoding 2) All address lines are consider 3) More hardware required • partial decoding 1) Also referred to be as liner decoding 2) Few address lines are ignored 3) Decoder hardware is simple
  • 138. 1-Aug-13 Prof.Nitin Ahire 138 8085 Memory Interfacing 8085 Memory Interfacing • Generally µP 8085 can address 64 kB of memory . • Generally EPROMS are used as program memory and RAM as data memory. • We can interface Multiple RAMs and EPROMS to single µP . • Memory interfacing includes 3 steps : 1. Select the chip. 2. Identify register. 3. Enable appropriate buffer. 4. linkmemory_interfacing.ppt
  • 139. 1-Aug-13 Prof.Nitin Ahire 139 8085 Memory Interfacing 8085 Memory Interfacing • Example: Interface 2Kbytes of Memory to 8085 with starting address 8000H. Initially we realize that 2K memory requires 11 address lines (2^11=2048). So we use A0-A10 . • Write down A15 –A0 A15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADD 8000H 87FFH
  • 140. 1-Aug-13 Prof.Nitin Ahire 140 8085 Memory Interfacing 8085 Memory Interfacing • Address lines A0-A10 are used to interface memory while A11,A12,A13,A14,A15 are given to 3:8 Decoder to provide an output signal used to select the memory chip CS‾or Chip select input. • MEMR‾ and MEMW‾are given to RD‾and WR‾pins of Memory chip. • Data lines D0-D7 are given to D0-D7 pins of the memory chip. • In this way memory interfacing can be achieved.
  • 141. 1-Aug-13 Prof.Nitin Ahire 141 8085 Memory Interfacing 8085 Memory Interfacing • The diagram of 2k interfacing is shown below: A15-A8 Latch AD7-AD0 D7- D0 A7- A0 8085 ALE IO/M RD WR 2K Byte Memory Chip WR RD CS A10- A0 A15- A11 3:8DECODER
  • 142. Microprocessor & Microcontroller Microprocessor & Microcontroller - - I I T.E Sem V (Rev) T.E Sem V (Rev) Prof. Nitin Ahire Prof. Nitin Ahire XIE, Mahim XIE, Mahim
  • 143. 1-Aug-13 Prof.Nitin Ahire 143 Connection of I/O devices. Connection of I/O devices. • Polling method • Interrupt method
  • 144. 1-Aug-13 Prof.Nitin Ahire 144 Interrupt system of 8085 Interrupt system of 8085 • Definition: “It is a mechanism by which an I/O device ( Hardware interrupt) or an instruction (software interrupt) can suspend the normal execution of the processor and get it self serviced.”
  • 145. 1-Aug-13 Prof.Nitin Ahire 145 Types of interrupt Types of interrupt • 1) Hardware interrupt • 2) Software interrupt
  • 146. 1-Aug-13 Prof.Nitin Ahire 146 Hardware interrupt Hardware interrupt • Interrupt : “It is an external asynchronous input that inform the ‘up’ to complete the instruction that it is currently executing and fetch a new routine in order to offer a service to that I/O devices. Once the I/O device is serviced, the ‘up’ will continue with execution of its normal program.”
  • 147. 1-Aug-13 Prof.Nitin Ahire 147 Hardware interrupt Hardware interrupt • 8085 has ‘5’ hardware interrupt 1)Trap 2)RST 7.5 3)RST 6.5 4)RST 5.5 5)INTR
  • 148. 1-Aug-13 Prof.Nitin Ahire 148 Types of Hardware interrupt Types of Hardware interrupt • NMI( non maskable) 1) It can’t be masked or made pending 2) Highest priority 3) This interrupt disable all maskable interrupts 4) Used for emergency purpose like power failure, smoke detector e.g. TRAP • Maskable 1) It can be masked or made pending 2) Lower priority 3) These interrupt dose not disable non maskable interrupt 4) Used to interface peripherals. e.g. RST 7.5
  • 149. 1-Aug-13 Prof.Nitin Ahire 149 Hardware Interrupt Hardware Interrupt Priority interrupt ISR address trigger 1 TRAP 0024h edge +level 2 RST 7.5 003Ch edge 3 RST 6.5 0034h level 4 RST 5.5 002Ch level 5 INTR No specific level location
  • 150. 1-Aug-13 Prof.Nitin Ahire 150 Software interrupt Software interrupt • 8085 has ‘8’ software interrupt 1)RST0 2)RST1 3)RST2 4)RST3 5)RST4 6)RST5 7)RST6 8)RST7
  • 151. 1-Aug-13 Prof.Nitin Ahire 151 Software interrupt Software interrupt • These instruction ( RST0-RST7) allow the ‘up’ to transfer the program control from main program to the subroutine program (i.e. ISR) ISR: interrupt service routing
  • 152. 1-Aug-13 Prof.Nitin Ahire 152 Software interrupt Software interrupt Interrupt Restart locations RST 0 0 X 8 = 0000h RST 1 1 X 8 = 0008h RST 2 2 x 8 = 0010h RST 3 3 X 8 = 0018h RST 4 4 X 8 = 0020h RST 5 5 X 8 = 0028h RST 6 6 X 8 = 0030h RST 7 7 X 8 = 0038h
  • 153. 1-Aug-13 Prof.Nitin Ahire 153 Software interrupt / hardware Software interrupt / hardware interrupt interrupt • Software interrupt 1)It is as synchronous event 2)This interrupt is requested by executing instruction 3)PC is incremented 4)The priority is highest 5)It can’t be ignored 6)It is not used to interface the peripheral Used in debugging • Hardware interrupt 1)It is an asynchronous event 2)This interrupt is requested by external device 3)PC is not incremented 4)The priority is lower than softer interrupt 5)Can be masked 6)It is used to interface peripheral devices
  • 154. 1-Aug-13 Prof.Nitin Ahire 154 Interrupt related Interrupt related instructions instructions 1) EI : it is used to enable the all maskable interrupt. It required 1- byte, one MC (4T). It does not affect on TRAP 2) DI : it is used to disable all maskable interrupt. 1-byte (4T). It does not affect on TRAP
  • 155. 1-Aug-13 Prof.Nitin Ahire 155 Interrupt related Interrupt related instructions instructions SIM : (set interrupt mask) 1-byte (4T) state. • Used to enable or disable RST 7.5, RST 6.5, RST 5.5 interrupts. • It does not affect on TRAP & INTR . • It is used in serial data transmission • It also transfer serial data bit ‘D7’of ‘A’ to the SOD pin • Hence the CWR format must be load in the ‘A’ before execution of SIM instruction.
  • 156. 1-Aug-13 Prof.Nitin Ahire 156 SIM (bit pattern) SIM (bit pattern) • SOD pin • D7= SOD • D6= serial data enable 1=enable, 0=disable • D5= Don’t care • D4= Reset R7.5 F/F, 1=Reset 0=no effect • D3=MSE Mask set enable 1=D2,D1,D0 bit are effective 0=D2,D1,D0 bit are ignored • D2= M’7.5 Mask RST 7.5 1= Mask or disable R7.5 0= Enable RST 7.5 • D1=M’6.5 Mask RST 6.5 1= Mask or disable R6.5 0= Enable RST 6.5 • D0=M’5.5 Mask RST 5.5 1= Mask or disable R5.5 0= Enable RST 5.5 SOD SDE M’ 6.5 M’ 7.5 MSE R 7.5 X M’ 5.5
  • 157. 1-Aug-13 Prof.Nitin Ahire 157 Interrupt related Interrupt related instructions instructions RIM : ( read interrupt mask) 1-byte (4T) state. • It gives the status of the pending maskable interrupt (RST 7.5 – RST 5.5) • It does not affect on TRAP & INTR • It can also transfer the contents of the serial input data on the SID pin into the accumulator (‘D7’ bit.) • Hence after execution of this instruction serial data get load in to the accumulator
  • 158. 1-Aug-13 Prof.Nitin Ahire 158 RIM (bit pattern) RIM (bit pattern) • SID pin • D7= SID • D6= • D5= if 1 respective interrupt is pending • D4= 0 respective interrupt is not pending • D3=IE interrupt enable • D2= • D1= if 1 respective interrupt is Masked • D0= 0 respective interrupt is unmasked SID I 7.5 M 6.5 M 7.5 IE I 5.5 I 6.5 M 5.5
  • 159. 8155 (PPI) 8155 (PPI) Prof. Nitin Ahire Prof. Nitin Ahire XIE, Mahim XIE, Mahim
  • 160. 1-Aug-13 Prof.Nitin Ahire 160 Features of 8155 (PPI) Features of 8155 (PPI) • It is a multifunction device designed to use in minimum mode system • It contain RAM, I/O ports and Timer • Features 1) 2k static RAM cell organized as 256 bytes 2) 2 programmable 8 bit I/O ports (A,B) 3) 1 programmable 6 bit I/O port (c) 4) 1 programmable 14 bit binary down counter/timer 5) An internal address latch to de multiplex AD0- AD7 using ALE 6) Internal selection logic for memory and I/O. using command register
  • 161. 1-Aug-13 Prof.Nitin Ahire 161 8155 8155 AD0-AD7 IO/M CE ALE RD WR VCC GND RESET TIMER IN TIMER OUT PA0-PA7 PB0-PB7 PC0-PC5 A B C 256x8 Static RAM Timer CE – 8155 CE - 8156
  • 162. 1-Aug-13 Prof.Nitin Ahire 162 Pin out Pin out • ADo-AD7 : address and data lines internally de multiplex by using internal latch and ALE signal address lines are used to access the memory or I/O port depending on the status of IO/M^ pin i/p • D0-D7 lines act as data bus
  • 163. 1-Aug-13 Prof.Nitin Ahire 163 Pin out Pin out • ALE : used to de multiplex the AD0- AD7 • IO/M^ : used to differentiate between IO or memory • CE^ : used to select the 8155 • RD^ : used for to read the data from memory or I/O • WR^: used for to write the data from memory or I/O
  • 164. 1-Aug-13 Prof.Nitin Ahire 164 Pin out Pin out • Reset : used to reset the 8155 IC • PA0-PA7,PB0-PB7 : Port A and Port B I/P 8 bit pins they can be programmed either i/p or o/p port using command register • PC0-PC5 : these are 6 bit I/O pins they can be used as simple Input output port or control port when PA and/or PB are used in handshake mode • Timer in: this is an i/p to the timer • Timer out :This is an o/p pin depending on the mode of the timer o/p can be either a square wave or pulse. • VCC, GND : +5 v resp. to GND
  • 165. 1-Aug-13 Prof.Nitin Ahire 165 I/O port or timer selection I/O port or timer selection IO/M^ A2 A1 A0 1 0 0 0 CWR 1 0 0 1 PORT A 1 0 1 0 PORT B 1 0 1 1 PORT C 1 1 0 0 Timer LSB 1 1 0 1 Timer MSB 0 Memory option
  • 166. 1-Aug-13 Prof.Nitin Ahire 166 Control Word of 8155 Control Word of 8155 • D0=Port A 0=Input • D1=Port B 1=Output • D2 &D3 used with port C • D4 (IEA=interrupt Enable Port A) 1=Enable • D5 (IEB=interrupt Enable Port B) 0=Disable • D6&D7 used in timer mode D7 D6 D1 D2 D3 D4 D5 D0
  • 167. 1-Aug-13 Prof.Nitin Ahire 167 D7 D6 timer commands 0 0 NOP 0 1 Stop counting if timer is running 1 0 Stop after TC (stop after at the count) 1 1 Start timer if is not running
  • 168. 1-Aug-13 Prof.Nitin Ahire 168 Timer mode Timer mode • MSB • LSB • Mode 0 In this mode the timer o/p remains high for half the count and goes low for the remaining count, thus providing the single square wave. The pulse width is determined by count and clk freq • Mode 1 In this mode the initial count is automatically reloaded at the end of each count. Provide the continuous square wave. • Mode 2 In this mode single clock pulse is provided at the end of count • Mode 3 This is similar to mode 2 except the initial count is reloaded to provided a continuous wave form M2 M1 D9 D10 D11 D12 D13 D8 D7 D6 D1 D2 D3 D4 D5 D0
  • 169. 1-Aug-13 Prof.Nitin Ahire 169 • For port C D3 D2 0 0 = ALT 1(port C as Input mode) 1 1 = ALT 2(Port C as Output Mode) 0 1 = ALT 3 used in handshake mode 1 0 = ALT 4 along with Port A &B
  • 170. 1-Aug-13 Prof.Nitin Ahire 170 Example 1 Example 1 • Design a square wave generator with a pulse width of 100 us by using the 8155 timer if clock freq is 3MHz. Sol : T=1/F=1/3MHz=330ns Timer count=pulse period/CLK period = 200us/330ns=606 count = 025Eh
  • 171. 1-Aug-13 Prof.Nitin Ahire 171 • Assuming the port addresses CWR=20h Timer LSB=24h Timer MSB=25h Count =025Eh Therefore 5Eh must be load in the LSB timer Select mode 1 for square wave. Therefore 42h (01000010)must be load in the MSB timer
  • 172. 1-Aug-13 Prof.Nitin Ahire 172 • Control word To start the timer D7 and D6 bit must be 1 set the bit of CWR and send to address 20h therefore C0h (11000000) must be load in CWR register.
  • 173. 1-Aug-13 Prof.Nitin Ahire 173 Program for square wave Program for square wave • MVI A,5Eh OUT 24H MVI A,42H OUT 25H MVI A,C0H OUT 20H HLT
  • 175. 1-Aug-13 Prof.Nitin Ahire 175 Feature of 8255 Feature of 8255 • It is programmable parallel I/O device • It has 3,8 bit I/O Ports: Port A, Port B, Port C, which are arranged in two groups of 12 pins. • TTL compatible • Direct bit set/reset capability is available for Port C
  • 176. 1-Aug-13 Prof.Nitin Ahire 176 8255 PIN DIAGRAM 8255 PIN DIAGRAM PA0-PA7 I/O Port A Pins PB0-PB7 I/O Port B Pins PC0-PC7 I/O Port C Pins D0-D7 I/O Data Pins RESET I Reset pin RD¯ I Read input WR ¯ I Write input A0-A1 I Address pins CS ¯ I Chip select Vcc , Gnd I +5volt supply
  • 177. 1-Aug-13 Prof.Nitin Ahire 177 8255 BLOCK DIAGRAM 8255 BLOCK DIAGRAM
  • 178. 1-Aug-13 Prof.Nitin Ahire 178 8255 BLOCK DIAGRAM 8255 BLOCK DIAGRAM Data Bus Buffer: It is an 8 bit data buffer used to interface 8255 with 8085. It is connected to D0-D7 bits of 8255. Read/write control logic: It consists of inputs RD‾,WR‾,A0,A1,CS‾ . RD‾,WR‾ are used for reading and writing on to 8255 and are connected to MEMR‾,MEMW‾ of 8085 respectively. A0,A1 are Port select signals used to select the particular port . CS ‾ is used to select the 8255 device . It is controlled by the output of the 3:8 decoder used to decode the address lines of 8085.
  • 179. 1-Aug-13 Prof.Nitin Ahire 179 8255 BLOCK DIAGRAM 8255 BLOCK DIAGRAM A1 A0 Selected port 0 0 Port A 0 1 Port B 1 0 Port C 1 1 Control Register A0,A1 decide the port to be used in 8255.
  • 180. 1-Aug-13 Prof.Nitin Ahire 180 8255 BLOCK DIAGRAM 8255 BLOCK DIAGRAM Group A and Group B Control: Group A control consists of Port A and Port C upper. Group B control consists of Port B and Port C lower. Each group is controlled through software. They receive commands from the RD‾, WR‾ pins to allow access to bit pattern of 8085. The bit pattern consists of : 1. Information about which group is operated. 2. Information about mode of Operation.
  • 181. 1-Aug-13 Prof.Nitin Ahire 181 8255 BLOCK DIAGRAM 8255 BLOCK DIAGRAM • PORT A,B: These are bi-directional 8 bit ports each and are used to interface 8255 with CPU or peripherals. • Port A is controlled by Group A while Port B is controlled by Group B Control. • PORT C: This is a bi-directional 8 bit port controlled partially by Group A control and partially by Group B control . • It is divided into two parts Port C upper and Port C lower each of a nibble. • It is used mainly for control signals and interfacing with peripherals.
  • 182. 1-Aug-13 Prof.Nitin Ahire 182 8255 Operating Mode 8255 Operating Mode • 8255 provides one control word register • It is selected when A0=1,A1=1,CS^=0,WR^=0 • The read operation is not allowed for CWR • There are two CWR formats (mode) 1)BSR mode 2)I/O mode • The two basic modes are selected by D7 bit of control register • when D7=1 it is a I/O mode D7=0 it is BSR mode
  • 183. 1-Aug-13 Prof.Nitin Ahire 183 8255 MODES 8255 MODES • BSR (Bit Set Reset) Mode • Only C is available for bit mode access. • Allows single bit manipulation for control applications • Mode 0 : Simple I/O • Any of A, B, CL and CH can be programmed as input or output • Mode 1: I/O with Handshake • A and B can be used for I/O • C provides the handshake signals • Mode 2: Bi-directional with handshake • A is bi-directional with C providing handshake signals • B is simple I/O (mode-0) or handshake I/O (mode-1)
  • 184. 1-Aug-13 Prof.Nitin Ahire 184 • Bit D7 must be zero for BSR mode • The BSR mode is a port C bit set/reset mode. • The indivisible bit of port C can be set or reset by writing a control word in CWR. • Port C bit set/reset ; if D0=0 reset D0=1 set • The port pin of port C is selected using bit D3,D2,D1 • The BSR mode affect only one bit of port C at a time BSR mode BSR mode 0 X b b b x x S/R D7 D6 D1 D2 D3 D4 D5 D0
  • 185. 1-Aug-13 Prof.Nitin Ahire 185 Port C bit selection Port C bit selection D3/b D2/b D1/b Bit 0 0 0 Bit 0 0 0 1 Bit 1 0 1 0 Bit 2 0 1 1 Bit 3 1 0 0 Bit 4 1 0 1 Bit 5 1 1 0 Bit 6 1 1 1 Bit 7
  • 186. 1-Aug-13 Prof.Nitin Ahire 186 Example Example • Write a set of instruction to perform the following 1)Set bit 4 of port C 2)Reset bit 4 of port C( Assume Port C Address =12 h) Sol: 1) MVI A, 09h OUT 12h 2) MVI A,08h OUT 12h
  • 187. 1-Aug-13 Prof.Nitin Ahire 187 I/O mode (CWR) I/O mode (CWR) • When the bit D7=1 then I/O mode is selected • The bit D6 and D5 used for mode selection of Group A • If the D4 =1port A act as I/P port D4 = 0 port A act as O/P Port • If the D3 = 1 Port C Upper act as I/P Port D3 = 0 port C Upper act as O/P Port • The bit D2 used for mode selection of Group B • If the D1 = 1 port B act as I/P Port • D1 = 0 port B act as O/P Port • If the D0 = 1 Port C Lower act as I/P Port D0 = 0 Port C Lower act as O/P Port I/O,BSRMode A PB Mode B PCU PA Mode A PCL D7 D6 D1 D2 D3 D4 D5 D0
  • 188. 1-Aug-13 Prof.Nitin Ahire 188 Example Example • Write a program to initialize 8255 in the configuration given below: 1 Port A : Simple I/P 2 Port B : Simple O/P 3 Port CL: O/P 4 Port CU: I/P Assume CWR address is 83h
  • 189. 1-Aug-13 Prof.Nitin Ahire 189 solutions solutions • MVI A,98h OUT 83h I/O,BSRMode A PB Mode B PCU PA Mode A PCL 1 0 0 0 1 1 0 0
  • 190. 1-Aug-13 Prof.Nitin Ahire 190 INTERFACING 8085 8255 INTERFACING 8085 8255 • Here 8255 is interfaced in I/O Mapped I/O mode. Initially we write down the addresses and then interface it . A15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port 1 0 0 0 0 X X X X X X X X X 0 0 A 1 0 0 0 0 X X X X X X X X X 0 1 B 1 0 0 0 0 X X X X X X X X X 1 0 C 1 0 0 0 0 X X X X X X X X X 1 1 CW
  • 191. 1-Aug-13 Prof.Nitin Ahire 191 INTERFACING 8085 8255 INTERFACING 8085 8255 • Thus we get addresses ,considering don’t cares to be zero as Port A =80H Port B =81H Port C =82H CWR =83H • Then, we give A11,A12,A13 pins to A,B,C inputs of Decoder to enable 8255 or Chip Select. • A15 is logic 1 so it is given to active HIGH G1 pin A14 ,IO/M ‾ are given to active low G2B ‾,G2A ‾ pins. • Output from Latch is given as A0,A1 pins to 8255 while D0-D7 are given as data inputs.
  • 192. 1-Aug-13 Prof.Nitin Ahire 192 INTERFACING 8085 8255 INTERFACING 8085 8255 8255 8085 3:8 decoder 74373 (AD0-AD7) D7-D0 A0-A7 /CS A0 A1 O0 O1 O7 A13 A12 A11 ALE RD ¯ WR ¯ RD¯ WR¯ G2A G2B G1 A15 A14 IO/M A B C PA PB PC
  • 193. 1-Aug-13 Prof.Nitin Ahire 193 INTERFACING 8085 8255 INTERFACING 8085 8255 Example: Take data from 8255 port B. Add FF H . Output result to port A.
  • 194. 1-Aug-13 Prof.Nitin Ahire 194 MVI A,82H Initialize 8255. OUT 83H LDA 81H Take data from port B ADI FFH Add FF H to data OUT 80H. OUT Result to port A. RST1. STOP. Solution Solution
  • 195. 1-Aug-13 Prof.Nitin Ahire 195 INTERFACING STEPPER INTERFACING STEPPER MOTOR with 8255 MOTOR with 8255
  • 196. 1-Aug-13 Prof.Nitin Ahire 196 Stepper motor Stepper motor • Hardware : A stepper motor is a digital motor. It can be driven by digital signals motor shown in the figure ( ckt ) has two phases, with center tap winding. • The center taps of these winding are connected to the +5Volt supply. • Due to this, motor can be excited by grounding 4 terminals of the 2 winding.
  • 197. 1-Aug-13 Prof.Nitin Ahire 197 Locking system for stepper Locking system for stepper motor motor • In the stepper motor it is not desirable to excite both the ends of the same winding simultaneously. • This cancel the flux and motor winding may damage. • To avoid this digital clocking system must be design.
  • 198. Stepper Motor Programming Stepper Motor Programming • MVI A, 80H (CWR) • OUT 43H (CWR ADDRESS) • UP:MVI A,88H • OUT 40H (PORT A ADDRESS) • CALL 6666H (CALL Delay) • MVI A,11H • OUT 40H • CALL 6666H • MVI A,22H • OUT 40H • CALL 6666H • MVI A,44H • OUT 40H • JMP UP 1-Aug-13 Prof.Nitin Ahire 198
  • 199. 1-Aug-13 Prof.Nitin Ahire 199 Data bit pass to the port A Data bit pass to the port A PA0 PA1 PA2 PA3 1 0 1 0 = 0A 1 0 0 1 = 09 0 1 0 1 = 05 0 1 1 0 = 06
  • 200. 1-Aug-13 Prof.Nitin Ahire 200 Data bits Data bits • 5000H 0AH • 5001H 09H • 5002H 05H • 5003H 06H
  • 201. 1-Aug-13 Prof.Nitin Ahire 201 Initialized Port A as O/P Port Initialized Port A as O/P Port • Program for stepper motor LXI SP,FFFFH MVI A,80H ; to make port A as o/p port OUT CWR BACK: LXI H,5000H ;HL act as memory pointer MVI C,04H ;counter for the steps UP: MOV A,M ;data bits transfer on the lower nibble of port A OUT PORT A CALL DELAY ; delay for the steps INX H ; increment the HL pair for the next data bits DCR C ; decrement the counter JNZ UP ;check zero flag JMP BACK ; jump back for continuous loop ( motor rotation)