VLSI                                                                              email id:vlsi@pantechmail.com SI.No     ...
VLSI                                                                               email id:vlsi@pantechmail.comPSVLS 27  ...
VLSI                                                                              email id:vlsi@pantechmail.comPSVLS 54   ...
VLSI                                                                              email id:vlsi@pantechmail.comPSVLS 82   ...
VLSI                                                                               email id:vlsi@pantechmail.comPSVLS 109 ...
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IEEE 2012 Low Power & vlsi_2012-13_titles


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IEEE 2012 Low Power & vlsi_2012-13_titles

  1. 1. VLSI email id:vlsi@pantechmail.com SI.No Topics FieldPSVLS 1 Real Time Hardware Co-simulation of Edge Detection for Video Processing System System Generator & SignalPSVLS 2 BPSK System on Spartan 3E FPGA Processing IEEE 2012PSVLS 3 Implementation of PSK and QAM demodulators on FPGAPSVLS 4 Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA ImplementationPSVLS 5 Platform-Independent Customizable UART Soft-CorePSVLS 6 VLSI Architecture of Arithmetic Coder Used in SPIHTPSVLS 7 Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM DesignPSVLS 8 Single Phase Clocked Quasi Static Adiabatic Tree AdderPSVLS 9 Enhanced Power Gating Schemes for Low Leakage Low Ground Bounce Noise in Deep Low Power Design Submicron Circuits IEEE 2012PSVLS 10 Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement SchemePSVLS 11 Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution NetworksPSVLS 12 Design of Low Voltage Low Power Operational AmplifierPSVLS 13 Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS CircuitsPSVLS 14 A Novel Architecture for VLSI Implementation of RSA CryptosystemPSVLS 15 FPGA Hardware of the LSB Steganography Method Communication Cryptography & IEEE 2012PSVLS 16 A Fast Cryptography Pipelined Hardware developed in FPGA with VHDLPSVLS 17 An efficient FPGA implementation of the Advanced Encryption Standard algorithmPSVLS 18 A Novel Data Embedding Method Using Adaptive Pixel Pair MatchingPSVLS 19 VHDL Implementation of a Flexible and Synthesizable FFT ProcessorPSVLS 20 An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image FusionPSVLS 21 Medical Image Fusion Based on Redundancy DWT and Mamdani Type Min-sum Mean-of- Soft Core Processor Design max Techniques with Quantitative AnalysisPSVLS 22 Edge Detection of Angiogram Images Using the Classical Image Processing Techniques IEEE 2012PSVLS 23 Input/Output Peripheral Devices Control through Serial Communication using Microblaze ProcessorPSVLS 24 Variable Scaling Factor based Invisible Image Watermarking using Hybrid DWT – SVD Compression - Decompression TechniquePSVLS 25 A Level Set Based Deformable Model for Segmenting Tumors in Medical ImagesPSVLS 26 Adaptive Steganalysis of Least Significant Bit Replacement in Grayscale Natural Images 14 www.pantechsolutions.net I www.pantechproed.com I www.pantechprojects.com ©2012Pantech ProEd Pvt Ltd
  2. 2. VLSI email id:vlsi@pantechmail.comPSVLS 27 Analysis of CT and MRI Image Fusion using Wavelet TransformPSVLS 28 Design of Modified Low Power Booth MultiplierPSVLS 29 An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet TransformPSVLS 30 Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications Applications Soft Core Processor DesignPSVLS 31 Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA A Novel Architecture for an Efficient Implementation of Image Compression Using 2D-DWT IEEE 2012PSVLS 32PSVLS 33 Background Subtraction Algorithm for Moving Object Detection in FPGAPSVLS 34 Design and Implementation of the Discrete Wavelet Transform on an FPGA Platform to Process Data Sets of up to Three DimensionsPSVLS 35 Gesture Recognition Using Field Programmable Gate ArraysPSVLS 36 Median Filter on FPGAsPSVLS 37 An Autoadaptive Edge-Detection Algorithm for Flame and Fire Image ProcessingPSVLS 38 An Efficient Denoising Architecture for Removal of Impulse Noise in ImagesPSVLS 39 Real Time Smart Car Lock Security System Using Face Detection and RecognitionPSVLS 40 A Novel Non-payment Vehicle Searching Method for Multilane-Free-Flow Electronic-Toll- Collection Systems (ecurity & System GeneratorPSVLS 41 Implementation of a Home Automation System through a Central FPGA ControllerPSVLS 42 Design of Intelligent Home Appliance Control System Based on FPGA and ZIGBEE IEEE 2012PSVLS 43 New Clock Generation Techniques for Synchronous Sampling of 16-QAM RF SignalsPSVLS 44 QPSK Modulator on FPGAPSVLS 45 Implementation of a QPSK System on FPGAPSVLS 46 Models Simulation based on HDL-Simulink PlatformPSVLS 47 Simulation and Implementation of a BPSK Modulator on FPGAPSVLS 48 An improved three-factor authentication scheme using smart card with biometric privacy protection Wireless CommunicationPSVLS 49 The Ship Monitoring and Control Network System Design IEEE 2011PSVLS 50 Autonomous Navigation for an Unmanned Mobile Robot in Urban AreasPSVLS 51 A Generic Framework for Three-Factor Authentication: Preserving Security and Privacy in Distributed SystemsPSVLS 52 A Low-Cost GPS&INS Integrated System Based on a FPGA PlatformPSVLS 53 An embedded high sensitivity navigation receiver for GPS 15 www.pantechsolutions.net I www.pantechproed.com I www.pantechprojects.com ©2012Pantech ProEd Pvt Ltd
  3. 3. VLSI email id:vlsi@pantechmail.comPSVLS 54 Hardware Efficiency Comparison of AES ImplementationsPSVLS 55 Efficient Design and Implementation of FFTPSVLS 56 Enhancing NBTI Recovery in SRAM Arrays Through Recovery BoostingPSVLS 57 Design of Sequential Elements for Low Power Clocking SystemPSVLS 58 Low-Power, Energy-Efficient Full Adder for Deep-Submicron DesignPSVLS 59 Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS CircuitsPSVLS 60 Parameterized FPGA-Based Architecture For Parallel 1-D Filtering Algorithms Low Power DesignPSVLS 61 A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors IEEE 2011PSVLS 62 Low Power Single Bitline 6T SRAM Cell With High Read StabilityPSVLS 63 Low Power Subthreshold D Flip FlopPSVLS 64 Low Leakage Power SRAM Cell for Embedded MemoryPSVLS 65 A Novel Low-Leakage 8T Differential SRAM CellPSVLS 66 Adiabatic Technique for Energy Efficient Logic Circuits DesignPSVLS 67 A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM DesignPSVLS 68 Performance Analysis of Power Gating designs in Low Power VLSI CircuitsPSVLS 69 Low-Power and Area-Efficient Carry Select AdderPSVLS 70 Operation Improvement of Indoor Robot by Gesture Recognition Security BasedPSVLS 71 Improving ATM Security Via Face Recognition IEEE 2011PSVLS 72 Design of Vehicle Positioning System Based on FPGAPSVLS 73 A Novel Area-Throughput Optimized Architecture for the AES AlgorithmPSVLS 74 Thwarting Control-Channel Jamming Attacks from Inside JammersPSVLS 75 Image Processing in Dynamic Reconfigurable PlatformPSVLS 76 Real-Time Object Tracking System on FPGAs Image ProcessingPSVLS 77 Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT IEEE 2011PSVLS 78 A Universal Background Subtraction Algorithm for Video SequencesPSVLS 79 A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet TransformPSVLS 80 Power Efficient Motion Estimation Algorithm and Architecture Based on Pixel TruncationPSVLS 81 Architectural Implementation of High Speed Optical Flow Computation Based on Lucas- Kanade Algorithm 16 www.pantechsolutions.net I www.pantechproed.com I www.pantechprojects.com ©2012Pantech ProEd Pvt Ltd
  4. 4. VLSI email id:vlsi@pantechmail.comPSVLS 82 Discrete Wavelet Transform-Based Satellite Image Resolution EnhancementPSVLS 83 An Efficient Denoising Architecture for Removal of Impulse Noise in ImagesPSVLS 84 Dynamic Hand Gesture Recognition for Human- Computer Interactions Dynamic Power Estimation for Motion Estimation Hardware Image ProcessingPSVLS 85 IEEE 2011PSVLS 86 Realization of a LSB Information Hiding algorithm Based on Lifting Wavelet Transform ImagePSVLS 87 Blind Image Watermarking Using a Sample Projection ApproachPSVLS 88 A Novel Power Reduction Technique for Block Matching Motion Estimation HardwarePSVLS 89 An improved method of image edge detection based on wavelet transformPSVLS 90 Mathematical Morphological Edge Detection For Remote Sensing ImagesPSVLS 91 A New Adaptive Weight Algorithm for Salt and Pepper Noise RemovalPSVLS 92 FPGA Implementation of AES Algorithm Wireless Jamming Attacks under Dynamic Traffic Uncertainty Wireless communicationPSVLS 93PSVLS 94 Car Monitoring, Alerting and Tracking Model IEEE 2010PSVLS 95 FPGA-Based GPS Application System DesignPSVLS 96 An Embedded System and RFID Solution For Transport Related IssuesPSVLS 97 Keyless Car Entry through Face Recognition Using FPGAPSVLS 98 Design of AM Modulation Signal Generator Based on Matlab/DSP BuilderPSVLS 99 Ground Bounce Noise Reduction of Low leakage 1-bit Nano-CMOS based Full Adder Cells for Mobile ApplicationsPSVLS 100 CMOS Full-Adders for Energy-Efficient Arithmetic ApplicationsPSVLS 101 Variability Resilient Low-power 7T-SRAM Design for nano-Scaled TechnologiesPSVLS 102 A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS Technology Power AnalysisPSVLS 103 Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI IEEE 2010 DesignPSVLS 104 Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI SystemsPSVLS 105 Optimal Design For Ground Bounce Noise Reduction Using Sleep TransistorPSVLS 106 A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip–Flops With Embedded LogicPSVLS 107 Design of A Low Power Flip-Flop Using CMOS Deep Submicron TechnologyPSVLS 108 A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems 17 www.pantechsolutions.net I www.pantechproed.com I www.pantechprojects.com ©2012Pantech ProEd Pvt Ltd
  5. 5. VLSI email id:vlsi@pantechmail.comPSVLS 109 Optimization of Processor Architecture for Image Edge Detection FilterPSVLS 110 Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster NumberPSVLS 111 Message Encoding in Images Using Lifting SchemesPSVLS 112 Medical Image Retrieval using Energy Efficient Wavelet TransformPSVLS 113 A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet TransformPSVLS 114 Design of Pipelined FFT Processor Based on FPGAPSVLS 115 An FPGA-based Architecture for Linear and Morphological Image Filtering Image Processing IEEE 2010PSVLS 116 Motion human detection based on background subtractionPSVLS 117 GPS-GSM Integration for Enhancing Public Transportation Management ServicesPSVLS 118 A Color Image Segmentation algorithm Based on Region GrowingPSVLS 119 Reconfigurable Hardware for Median Filtering for Image Processing ApplicationsPSVLS 120 Adaptive 2-D Wavelet Transform Based on the Lifting Scheme with Preserved Vanishing MomentsPSVLS 121 Performance Evaluation of DES and Blowfish AlgorithmsPSVLS 122 A new and efficient algorithm for the removal of high density salt and pepper noise in images and videosPSVLS 123 Ocean Wave Observation by GPS SignalPSVLS 124 Performance Comparison and Analysis of PSK and QAM 18 www.pantechsolutions.net I www.pantechproed.com I www.pantechprojects.com ©2012Pantech ProEd Pvt Ltd