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Power Management In Mobiles

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  1. 1. Power Management in Mobile Phones<br />Need and Techniques<br />
  2. 2. Agenda<br />What is Power Management?<br />Why Power Management?<br />Power Management Techniques<br />HW support ..<br />Role of Applications ..<br />Power Management and Media use cases<br />
  3. 3. What is power Management?<br />Technique for effective use of energy<br />Desired performance at minimal power consumption<br />Automated without user intervention<br />A little help from Applications is always welcome!!<br />
  4. 4. Why Power Management?<br />Applications and usage have become sophisticated<br />Requiring More complicated chips<br />Freq of operation directly proportional to power consumed<br />Main chip is not the only consumer<br />Bigger color touch screen consumes more power<br />More RAM requires more power<br />Each new peripheral like WLAN and BT requires power<br />But resource & energy constrained!<br />Breakthrough in battery technology is not at same pace of the <br />Most phones will have about 1000 mAh battery<br />Let us see how long this battery last?<br />Only 80% of the battery is usable <br />At 500mA it will last less then two hours<br />Some figures 0.6mW/MHz (0.13µm, 1.2V) including cache controllers for ARM11<br />This means processor only consumes .5mA/MHz or ~300mA at full 600MHz<br />
  5. 5. Why Power Management?..<br />All capabilities are not always used<br />Most applications do not require 100% MIPS<br />Most HW accelerators or component are not used often<br />Most peripherals not used often<br />There is an Idle time between active use<br />How to handle such cases<br />Its like complicated switch board with multiple switches<br />Some On/Off some variable dimmer<br />Effective management of this required <br />
  6. 6. Power Management Technique<br />Simple energy management directives:<br />Power off component when not in use (USB)<br />Slow down whenever possible (processor)<br />Efficient schemes:<br />Dynamic power management (DPM)<br />system switches dynamically between high- and low-consumption system power modes based on activity<br />Dynamic voltage and frequency scaling (DVFS)<br />DVFS is a technique through which the idle time of the system is minimized. It uses the optimal operating frequency and voltage to allow a task to be performed in the required amount of time. This reduces the active power consumption (power consumed while executing a task) of the device while still meeting task requirements.<br />
  7. 7. DPM<br />
  8. 8. Power Management Technique…<br />Decision: DVFS or DPM?<br />DPM - High latency for Power Off to Power On <br />Voltage stabilization time<br />Clock stabilization time<br />Dependencies chain make it even more<br />DVFS also require clock stabilization<br />There are other techniques like cutting clock - low latency<br />Not that useful as in 45 nm considerable Power is lost even when not switching – leakage current<br />ARM in sleep will also consume power<br />But until we have sufficient sleep time we cannot switch off<br />
  9. 9. HW Support ..<br />Support Multiple Voltage Levels (Voltage domain)<br />Power = V*I , lower voltage means lower power<br />Chip is divided in multiple Voltage domains<br />Voltage level controlled by SW “DVFS”<br />Support Multiple Power Domains<br />Having switches for controlling power to sections of chip<br />But the number and dependencies is unmanageable<br />HW helps here by managing dependencies<br />Support for Clock Gating (Clock domain)<br />Switching consumes power <br />Some power can be saved by cutting clock<br />This is quickest thing to do<br />Here also number of clocks and there dependencies are complex <br />HW helps here in managing dependencies<br />
  10. 10. Role of Applications..<br />Allow processor to go to sleep<br />For longer sleep duration DPM kicks in<br />Avoid periodic polling<br />This impacts the sleep duration and type<br />Unnecessary wakeups increases power consumptions<br />Instead waiting for events/interrupts<br />If required and possible try using deferrable timers<br />Some OS provides it e.g. Symbian <br />Optimize computation to reduce MIPS<br />For higher MIPS, HW chooses high freq/voltage<br />Utilize HWA as much as possible<br />Use OEM supplied libraries and routines for complex algorithms<br />E.g. Video decode, these are profiled and Tuned for optimal power consumption<br />
  11. 11. Power Management and Media UC<br />Media Play (MP3) Scenario<br />Classification:<br />Final frame rendering at fixed rate<br />Much slower then time it may take to decode a frame<br />Recommendation<br />Fetch and Decode frames in chunk<br />While decoded frames are rendered only audio peripheral, system DMA , memory etc. will be powered and not processor<br />Impact<br />High power consuming resource remain idle for a large chunk of time<br />With single frame decode total idle for processor is X but it wakes-up frequently inhabiting deeper sleeps<br />With multiple frame total idle time still remains X but system wakes-up less frequently<br />So while Media is playing processor does go to sleep<br />App should still refrain from periodic polling<br />
  12. 12. Thanks <br />
  13. 13. Power Management Value chain(Backup) <br />