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SDAccel Design Contest: Vivado Slide 1 SDAccel Design Contest: Vivado Slide 2 SDAccel Design Contest: Vivado Slide 3 SDAccel Design Contest: Vivado Slide 4 SDAccel Design Contest: Vivado Slide 5 SDAccel Design Contest: Vivado Slide 6 SDAccel Design Contest: Vivado Slide 7 SDAccel Design Contest: Vivado Slide 8 SDAccel Design Contest: Vivado Slide 9 SDAccel Design Contest: Vivado Slide 10 SDAccel Design Contest: Vivado Slide 11 SDAccel Design Contest: Vivado Slide 12 SDAccel Design Contest: Vivado Slide 13 SDAccel Design Contest: Vivado Slide 14 SDAccel Design Contest: Vivado Slide 15 SDAccel Design Contest: Vivado Slide 16 SDAccel Design Contest: Vivado Slide 17 SDAccel Design Contest: Vivado Slide 18 SDAccel Design Contest: Vivado Slide 19 SDAccel Design Contest: Vivado Slide 20 SDAccel Design Contest: Vivado Slide 21 SDAccel Design Contest: Vivado Slide 22 SDAccel Design Contest: Vivado Slide 23 SDAccel Design Contest: Vivado Slide 24 SDAccel Design Contest: Vivado Slide 25 SDAccel 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SDAccel Design Contest: Vivado

  1. 1. Courses @ NECST Lorenzo Di Tucci <lorenzo.ditucci@polimi.it> Emanuele Del Sozzo <emanuele.delsozzo@polimi.it> Marco D. Santambrogio <marco.santambrogio@polimi.it> Xilinx Vivado 25/01/2018
  2. 2. Agenda • Hardware Design Flow (2nd step) • Xilinx Vivado –Synthesis –Place & Route –Bitstream Generation • Hands on example: implementation of both master AXI and AXI stream designs for vector addition using Vivado and SDK
  3. 3. Reminder! Use this Google Doc to provide your data https://goo.gl/FRCG6y First, install the VPN we have provided you. (Mac: Tunnelblick - Windows/Linux: OpenVPN) To SSH to the machine: ssh <name>.<surname>@nags31.local.necst.it password: user
  4. 4. Reminder! You can change your password here: http://changepassword.local.necst.it/ You can also RDP to the instance using • Microsoft Remote Desktop (Microsoft/Mac OS) • Remmina (Linux) To connect to the machine, or change your password you must have started the VPN.
  5. 5. Hardware Design Flow for HPC • Hardware Design Flow (HDF): process to realize a hardware module • HDF for FPGAs can be seen as a 2 step process
  6. 6. The Hardware Design Flow
  7. 7. The Hardware Design Flow System integration, driver generation and runtime management
  8. 8. The Hardware Design Flow System integration, driver generation and runtime management
  9. 9. The Hardware Design Flow System integration, driver generation and runtime management
  10. 10. Vivado Design Suite • Vivado Design Suite is a software suite for synthesis and analysis of HDL designs • Vivado enables developers to synthesize designs, perform timing analysis, examine RTL diagrams, simulate designs, and configure the target FPGA • Starting from HDL, Vivado performs several steps to eventually generate the bitstream
  11. 11. Vivado Main Steps • Synthesis: translation from HDL to gate level • Place: placing of all the logic components on the FPGA • Route: design of all the wires needed to connect the placed components • Bitstream: generation of FPGA configuration file
  12. 12. Synthesis
  13. 13. Place & Route
  14. 14. Bitstream
  15. 15. Launch Vivado Source settings64.sh file and launch vivado
  16. 16. Vivado GUI • text
  17. 17. New Project • text
  18. 18. Project Name • text
  19. 19. Project Type • text
  20. 20. Add Sources • text
  21. 21. Add Constraints • text
  22. 22. Parts/Boards • text
  23. 23. Board Selection • text
  24. 24. Project Summary • text
  25. 25. Project Window • text Run / Generate Bitstream / Settings / Project Summary
  26. 26. Create Block Design • text
  27. 27. Block Design • text Add IP Validate Design Regenerate Layout Tcl Console Settings
  28. 28. Add IP • text
  29. 29. Add Memory Interface Generator • text
  30. 30. Run Block Automation • text
  31. 31. Block Automation Settings • text
  32. 32. Run Connection Automation • text
  33. 33. Connection Automation Settings • text
  34. 34. MIG Block • text
  35. 35. Customize MIG Block • text
  36. 36. MIG Customization • text
  37. 37. MIG Customization • text
  38. 38. MIG Customization • text
  39. 39. MIG Customization • text
  40. 40. MIG Customization • text
  41. 41. MIG Customization • text
  42. 42. MIG Customization • text This page allows to add / customize clock signals MIG will generate two clocks: - ui_clk (200Mhz) - ui_addn_clk_0 (100Mhz)
  43. 43. MIG Customization • text
  44. 44. MIG Customization • text
  45. 45. MIG Customization • text
  46. 46. MIG Customization • text
  47. 47. MIG Customization • text
  48. 48. MIG Customization • text
  49. 49. MIG Customization • text
  50. 50. MIG Customization • text
  51. 51. MIG Customization • text
  52. 52. MIG Customization • text
  53. 53. MIG Customization • text
  54. 54. MIG Customization • text
  55. 55. Add IP • text
  56. 56. Add Microblaze • text
  57. 57. Run Block Automation • text
  58. 58. Block Automation Settings • text
  59. 59. Run Connection Automation • text
  60. 60. Connection Automation Settings • text
  61. 61. Run Connection Automation • text
  62. 62. Connection Automation Settings • text
  63. 63. MIG + Microblaze Design • text
  64. 64. IP Settings • text
  65. 65. Settings • text
  66. 66. Repository • text
  67. 67. Add IP Repository • text
  68. 68. Path to IP Repository • text
  69. 69. IP Found • text
  70. 70. Repository Added • text
  71. 71. Add IP • text
  72. 72. Add Kernel • text
  73. 73. Connect Kernel Clock • text Connect Kernel Clock to Microblaze clock
  74. 74. Connection Automation Settings • text
  75. 75. Customize MDM • text
  76. 76. Enable JTAG UART • text
  77. 77. Run Connection Automation • text
  78. 78. Connection Automation Settings • text
  79. 79. Add IP • text
  80. 80. Add AXI Timer • text
  81. 81. Run Connection Automation • text
  82. 82. Connection Automation Settings • text
  83. 83. Customize Microblaze • text
  84. 84. Microblaze Settings • text
  85. 85. Validate Design • text
  86. 86. Validation Successful • text
  87. 87. Sources • text
  88. 88. HDL Wrapper • text
  89. 89. HDL Wrapper Creation • text
  90. 90. Generate Bitstream • text
  91. 91. Launch Synthesis And Implementation • text
  92. 92. Run Settings • text
  93. 93. Bitstream Generation Completed • text
  94. 94. Device Occupation • text
  95. 95. Resource Utilization • text
  96. 96. Export Hardware • text
  97. 97. Export Hardware Settings • text This command will create an HDF archive containing the bitstream and drivers for SDK
  98. 98. Launch SDK • text
  99. 99. Launch SDK Settings • text
  100. 100. SDK Window • text
  101. 101. Application Project • text
  102. 102. New Project • text
  103. 103. Templates • text
  104. 104. Program FPGA • text
  105. 105. Program FPGA settings • text
  106. 106. Programming FPGA • text
  107. 107. Run Configurations • text
  108. 108. Application (GDB) • text
  109. 109. Target Setup • text
  110. 110. Bitstream Selection • text
  111. 111. Target Setup done • text
  112. 112. Application • text
  113. 113. Project Selection • text
  114. 114. Application done • text
  115. 115. STDIO Connection • text
  116. 116. STDIO Connection done • text
  117. 117. Hello World Execution • text
  118. 118. Lscript • text
  119. 119. Running Our Design • text
  120. 120. AXI Stream Design • Let’s know implement the design for the streaming version of the vector addition • For this design, we will use the DMA IP • All the steps until the “MIG + Microblaze Design” slide do not change
  121. 121. IP Settings • text
  122. 122. Settings • text
  123. 123. Repository • text
  124. 124. Add IP Repository • text
  125. 125. Path to IP Repository • text
  126. 126. IP Found • text
  127. 127. Repository Added • text
  128. 128. Add IP • text
  129. 129. Add AXI DMA (0) • text
  130. 130. Customize DMA (0) • text
  131. 131. DMA Settings (0) • text
  132. 132. Connect DMA (0) clocks • text
  133. 133. Connection Automation Settings • text
  134. 134. Add IP • text
  135. 135. Add Kernel • text
  136. 136. Connect Kernel clock • text
  137. 137. Connect Kernel Reset • text
  138. 138. Connect port b to DMA (0) • text
  139. 139. Connect port a to DMA (0) • text
  140. 140. Add IP • text
  141. 141. Add AXI DMA (1) • text
  142. 142. Customize DMA (1) • text
  143. 143. DMA Settings (1) • text
  144. 144. Connect DMA (1) clocks • text
  145. 145. Connection Automation Settings • text
  146. 146. Connect port c to DMA (1) • text
  147. 147. Add IP • text
  148. 148. Add AXI DMA (2) • text
  149. 149. Customize DMA (2) • text
  150. 150. DMA (2) Settings • text
  151. 151. Connect DMA (2) clocks • text
  152. 152. Connection Automation Settings • text
  153. 153. Connect port d to DMA (2) • text
  154. 154. Next steps It is now possible to repeat the steps done for the previous design: –enable JTAG UART on the MDM block –add AXI Timer IP –Run Validation –Create HDL Wrapper –Run Generate Bitstream –Export Hardware –Run SDK
  155. 155. Device Occupation • text
  156. 156. Resource Utilization • text
  157. 157. SDK steps After exporting the hardware from Vivado: – Launch SDK – Create the project – Test the “helloworld” – Use the provided code to evaluate the design
  158. 158. Summary • Vivado toolchain allows developers to design both the IP they want to accelerate and the overall system • Vivado/Vivado HLS examples, and SDK code are available on nags31 server in /sdaccel_contest folder • Next lectures will focus on SDAccel toolchain
  159. 159. Feedbacks • We are working at improving this course, would you share your feedback for this lesson? https://goo.gl/tLcWQj
  160. 160. Thank You for the Attention! Lorenzo Di Tucci lorenzo.ditucci@polimi.it Emanuele Del Sozzo emanuele.delsozzo@polimi.it Marco D. Santambrogio marco.santambrogio@polimi.it

SDAccel Design Contest: Vivado

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