(Processor Design)
” (Processor)“      “   ”                  ” CPU“ ” CPU              (Processor)                          “      ”        ...
CPU   Intel
CPU   AMD
CPU
Arithmetic &Logical Unit : ALU ,             Control Unit: CU Memory                              Arithmetic & Logical Uni...
Control Unit                                           BusControl Bus,Data Bus       Address Bus   ALU,                ,  ...
CISC              RISC                     /                            . . 19902                                      CIS...
CISC : ComplexInstruction Set Computing              Cycle                        CISC                        Pentium 4
RISC : Reduces       Instruction Set ComputingRISC : Reduces Instruction Set Computing                Pipeline            ...
RISC                             RISC1                        One Instruction perCycle               RISC           1     ...
RISC           RISC1
RISC                                   RISC                    Instruction      Fixed Instruction Length                 ...
RISC                          RISC   load              store              RISC                       OperandRegister     ...
RISC                               RISC                      RISC               2                Register Register Indire...
CISC                              CISC           RISC                             RISC                                    ...
CISC                                   7           9       RISC                                                           ...
CISC      CISC (Complex                                 RISC                          RISC (Reduce InstructionInstruction ...
CISC                RISC      CISC (Complex       RISC (Reduce InstructionInstruction Set Computer)      Set Computer)    ...
CISC       CISC (Complex                                  RISC                                RISC (Reduce InstructionInst...
CISC           RISC     1. CISC (Complex Instruction Set Computer)                              CISC -                 Add...
CISC         RISC2. RISC (Reduce Instruction Set Computer)                     RISC--------
RISC Computer1.2.3.                  1 instruction format4.                   orthogonal ( Overlap     instruction   )5.  ...
RISC Computer6.                              Load and Store Architecture (              Load     Store                    ...
CISC              RISC                           CISC   RISCCISC                ,                    RISC       CISC    RISC
CISC                   RISC––                           Overlap)–                                        Pipelining    Sup...
CISC : Motorola                 MC68000•• CPU register• Memory
CISC : Motorola         MC68000Addressing Mode
CISC : Motorola          MC68000             MC    InstructionFormats
RISC : The SPARC•          SPARC•                                    Integer register    Floating-point register•      Bra...
RISC : The SPARC
RISC : The SPARC
RISC : The SPARC                                      SPARC  Addressing Mode• register register• register sign-extended, i...
RISC : The SPARC             SPARCInstruction Formats
RISC : The SPARC                          Address              (Addressing Modes)• Immediate Addressing Mode              ...
RISC : The SPARC                         Address               (Addressing Modes)• Register Addressing Mode• 8088         ...
RISC : The SPARC                            Address                (Addressing Modes)• Direct Addressing Mode             ...
RISC : The SPARC                           Address                (Addressing Modes)• Base Relative Addressing Mode       ...
RISC : The SPARC                            Address               (Addressing Modes)• Base Indexed Addressing Mode        ...
(IndexedAddressing)
(Register Indirect Addressing)
(DirectAddressing)
(DirectAddressing)     B  01010101              B
(DirectAddressing)2               1         256
(DirectAddressing)                            1              2
Immediate Addressing)
Inherent Addressing)•                          1                 (inherent)     implied address)          MOV A
6800   6800
6800•                       2           1•    1 86       04 (    2 04
6800•    1 96      00F2 (    2 F2               A
6502•                           6502    MOS Technology)                                    6800           6502         680...
6502
6502•                                       6502                    6800                             6502                4...
6502                1 B52 02       02       X
6502                       (pre - indexedindirect mode)                 X          16                 X                   ...
6502•           1 A1           2 05                          05                       X•                     X    50 (    ...
6502
6502                       (post -indexed mode)       16                        Y
6502    1 B1    2 05                                07                 Y                    0007                          ...
65024.                absolute indexedmode)               6502                         6800                        6800   ...
65021 BD              2 02       2A08          3 2A   X
6502•             (implied mode)       6502            6800•                00FF                0350              0351    ...
6502
:                      ,                                                                      MCS-51 .          : TBS Prod...
052 062  064 090
การออกแบบโปรเซสเซอร์
Upcoming SlideShare
Loading in …5
×

การออกแบบโปรเซสเซอร์

674 views

Published on

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
674
On SlideShare
0
From Embeds
0
Number of Embeds
3
Actions
Shares
0
Downloads
10
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

การออกแบบโปรเซสเซอร์

  1. 1. (Processor Design)
  2. 2. ” (Processor)“ “ ” ” CPU“ ” CPU (Processor) “ ” , ALU , Control ,
  3. 3. CPU Intel
  4. 4. CPU AMD
  5. 5. CPU
  6. 6. Arithmetic &Logical Unit : ALU , Control Unit: CU Memory Arithmetic & Logical Unit : ALU Arithmetic Logic Numeric Character 0-1, - - ALU ALU Multi-Processor
  7. 7. Control Unit BusControl Bus,Data Bus Address Bus ALU, , (Central Processing Unit: CPU) Main Memory
  8. 8. CISC RISC / . . 19902 CISC : Complex Instruction SetComputing RISC : ReducesInstruction Set Computing
  9. 9. CISC : ComplexInstruction Set Computing Cycle CISC Pentium 4
  10. 10. RISC : Reduces Instruction Set ComputingRISC : Reduces Instruction Set Computing Pipeline CISC CISC RISC
  11. 11. RISC RISC1 One Instruction perCycle RISC 1 1 Clock Cycle pipeline 1 1
  12. 12. RISC RISC1
  13. 13. RISC RISC  Instruction Fixed Instruction Length 1 RISC 1 Word CPU RISC Word 32 Bit 1Word , Operation, Operand , Result
  14. 14. RISC RISC load store RISC OperandRegister 1Word Operand 2 load store traffic
  15. 15. RISC RISC RISC 2 Register Register IndirectIndex Register RegisterRegister Index Operation
  16. 16. CISC CISC RISC RISC CISC RISC 1 1 CISC 100 1 CISC Program CISC ProcessorProgram CISC RISC Processor Processor Processor CISC RISC
  17. 17. CISC 7 9 RISC 7 9 7 9 1 9 Compiler 97 7 CISC 5 7 9 5 4 3
  18. 18. CISC CISC (Complex RISC RISC (Reduce InstructionInstruction Set Computer) Set Computer) (CISC) (RISC) CISC RISC ( 128 FIX , , , )CODE 128 BIT 2 6 6 BIT BIT FIX CODE 6 CISC 1 BIT 6 BIT Memory Waste Space RISC FIX CODEMemory
  19. 19. CISC RISC CISC (Complex RISC (Reduce InstructionInstruction Set Computer) Set Computer) (CISC) (RISC)1 CISC Complex 1 CISCInstruction RISC RISC CISC LOAD STORE LOAD Polynomial REGISTER CISC REGISTER CLOCK STORE RISC MEMORY2 Computer DECODE CPU , REGISTER , CISC MEMORY , DISK 2 CLOCK CYCLE FIX-ENCODING DECODE 3 RISC REGISTER
  20. 20. CISC CISC (Complex RISC RISC (Reduce InstructionInstruction Set Computer) Set Computer) (CISC) (RISC) CISC RISC 128 CPU CPUCODE LOAD STORECompiler MEMORY REGISTER CPU CompilerSoftware Support Hardware Compiler CPU Hardware RISC RISCSoftware CPU CompilerComplex Instruction CISC
  21. 21. CISC RISC 1. CISC (Complex Instruction Set Computer) CISC - Addressing Mode) Instruction Type) - - CISC Addressing Mode - -
  22. 22. CISC RISC2. RISC (Reduce Instruction Set Computer) RISC--------
  23. 23. RISC Computer1.2.3. 1 instruction format4. orthogonal ( Overlap instruction )5. 1 Addressing Mode
  24. 24. RISC Computer6. Load and Store Architecture ( Load Store register – to – register instruction)7. Instruction set Architecture (ISA) data type 2 integer floating point8. execute 1 clock cycle9. RISC chip Strength Software10. registers Speed CPU (Speed up)
  25. 25. CISC RISC CISC RISCCISC , RISC CISC RISC
  26. 26. CISC RISC–– Overlap)– Pipelining Superscalar– Fetch)– Execute)– Superscalar)
  27. 27. CISC : Motorola MC68000•• CPU register• Memory
  28. 28. CISC : Motorola MC68000Addressing Mode
  29. 29. CISC : Motorola MC68000 MC InstructionFormats
  30. 30. RISC : The SPARC• SPARC• Integer register Floating-point register• Branch delay (PC)• Processor state•• (IR)•• MMU (Memory Mapping Unit)
  31. 31. RISC : The SPARC
  32. 32. RISC : The SPARC
  33. 33. RISC : The SPARC SPARC Addressing Mode• register register• register sign-extended, immediate -bit constant
  34. 34. RISC : The SPARC SPARCInstruction Formats
  35. 35. RISC : The SPARC Address (Addressing Modes)• Immediate Addressing Mode 8 16 ( op-code ) 8 -128 ( 80H ) 127 ( 7FH ) 16 -32768 ( 8000H ) 32767 ( 7FFFH ) 8 16 0 8 255 ( 0FFH ) 16 65535 ( 0FFFFH )
  36. 36. RISC : The SPARC Address (Addressing Modes)• Register Addressing Mode• 8088 8 16 1. MOV AX,CX 2. INC AX 3. ADD SI,CX 4. DEC DX
  37. 37. RISC : The SPARC Address (Addressing Modes)• Direct Addressing Mode Direct addressing mode EA op-code 8088 EA• Register Addressing Mode register indirect addressing EA BX, BP register indirect addressing mode
  38. 38. RISC : The SPARC Address (Addressing Modes)• Base Relative Addressing Mode base relative addressing mode EA BX BP• Direct Indexed Addressing Mode direct indexed addressing mode EA DI SI
  39. 39. RISC : The SPARC Address (Addressing Modes)• Base Indexed Addressing Mode base indexed addressing mode Ea base indexed addressing mode 2
  40. 40. (IndexedAddressing)
  41. 41. (Register Indirect Addressing)
  42. 42. (DirectAddressing)
  43. 43. (DirectAddressing) B 01010101 B
  44. 44. (DirectAddressing)2 1 256
  45. 45. (DirectAddressing) 1 2
  46. 46. Immediate Addressing)
  47. 47. Inherent Addressing)• 1 (inherent) implied address) MOV A
  48. 48. 6800 6800
  49. 49. 6800• 2 1• 1 86 04 ( 2 04
  50. 50. 6800• 1 96 00F2 ( 2 F2 A
  51. 51. 6502• 6502 MOS Technology) 6800 6502 6800 6502 8 X Y( 6800 16 SP 8 9800 SP 16 6502• 9800• absolute mode) 6502 6800
  52. 52. 6502
  53. 53. 6502• 6502 6800 6502 4 X Y 1. (base page indexed mode) X 256 255 (FF ( 11111111) 100000001 8 00000001
  54. 54. 6502 1 B52 02 02 X
  55. 55. 6502 (pre - indexedindirect mode) X 16 X 64 K16
  56. 56. 6502• 1 A1 2 05 05 X• X 50 ( 50 0055 0055 0056 64 K
  57. 57. 6502
  58. 58. 6502 (post -indexed mode) 16 Y
  59. 59. 6502 1 B1 2 05 07 Y 0007 0007 0008 16 0007 0008 0150 Y 020150 + 02 = 0152 Y
  60. 60. 65024. absolute indexedmode) 6502 6800 6800 8 166502 16 8
  61. 61. 65021 BD 2 02 2A08 3 2A X
  62. 62. 6502• (implied mode) 6502 6800• 00FF 0350 0351 0400 0050 50 0051 03
  63. 63. 6502
  64. 64. : , MCS-51 . : TBS Product, 2547http://rossukhon.blogspot.com/2007/08/processor-central-processing-unit-cpu.htmlhttp://it.excise.go.th/asr2.htm#tophttp://kanokporn-kcom.blogspot.com/2011/11/processor.htmlhttp://www.bcoms.net/hardware/cpu.asphttp://lailao2007.tripod.com/cpu.htmhttp://www.sorncomputer.com/index.php?topic=3.0http://noolek03.exteen.com/20080726/entry?n=yhttp://blog-azmeeit.blogspot.com/http://library.uru.ac.th/webdb/images/RISCCISC.html
  65. 65. 052 062 064 090

×