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Go, hardware, Go! My Golab 2018 talk on the BondMachine Project

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Slides of the talk at Golab 2018 in florence

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Go, hardware, Go! My Golab 2018 talk on the BondMachine Project

  1. 1. Go, hardware, Go ! The BondMachine Project Mirko Mariotti Department of Physics and Geology - University of Perugia INFN Perugia October 22, 2018
  2. 2. Introduction Introduction The BondMachine: a comprehensive approach to computing. In this presentation i will talk about: Technological background of the project. Ideas behind the BondMachine. The Bondgo compiler and ancillary tools. Clustering. Conclusion. Mirko Mariotti Go, hardware, Go ! October 22, 2018 2/42
  3. 3. Technological Background Programmable Logic FPGA What is it ? A field-programmable gate array (FPGA) is an integrated circuit whose logic is re-programmable. It’s used to build reconfigurable digital circuits. FPGAs contain an array of pro- grammable logic blocks, and a hierarchy of reconfigurable intercon- nects that allow the blocks to be "wired together". Logic blocks can be configured to per- form complex combinational func- tions. The FPGA configuration is generally specified using a hard- ware description language (HDL). Mirko Mariotti Go, hardware, Go ! October 22, 2018 3/42
  4. 4. Technological Background Programmable Logic FPGA What is it ? A field-programmable gate array (FPGA) is an integrated circuit whose logic is re-programmable. It’s used to build reconfigurable digital circuits. FPGAs contain an array of pro- grammable logic blocks, and a hierarchy of reconfigurable intercon- nects that allow the blocks to be "wired together". Logic blocks can be configured to per- form complex combinational func- tions. The FPGA configuration is generally specified using a hard- ware description language (HDL). Mirko Mariotti Go, hardware, Go ! October 22, 2018 3/42
  5. 5. Technological Background Programmable Logic FPGA What is it ? A field-programmable gate array (FPGA) is an integrated circuit whose logic is re-programmable. It’s used to build reconfigurable digital circuits. FPGAs contain an array of pro- grammable logic blocks, and a hierarchy of reconfigurable intercon- nects that allow the blocks to be "wired together". Logic blocks can be configured to per- form complex combinational func- tions. The FPGA configuration is generally specified using a hard- ware description language (HDL). Mirko Mariotti Go, hardware, Go ! October 22, 2018 3/42
  6. 6. Technological Background Programmable Logic FPGA What is it ? A field-programmable gate array (FPGA) is an integrated circuit whose logic is re-programmable. It’s used to build reconfigurable digital circuits. FPGAs contain an array of pro- grammable logic blocks, and a hierarchy of reconfigurable intercon- nects that allow the blocks to be "wired together". Logic blocks can be configured to per- form complex combinational func- tions. The FPGA configuration is generally specified using a hard- ware description language (HDL). Mirko Mariotti Go, hardware, Go ! October 22, 2018 3/42
  7. 7. Technological Background Programmable Logic FPGA Why is used ? Prototyping, hardware testing, etc. Low development cost and short time to market. Computing Mirko Mariotti Go, hardware, Go ! October 22, 2018 4/42
  8. 8. Technological Background Programmable Logic FPGA Why is used ? Prototyping, hardware testing, etc. Low development cost and short time to market. Computing Mirko Mariotti Go, hardware, Go ! October 22, 2018 4/42
  9. 9. Technological Background Programmable Logic FPGA Why is used ? Prototyping, hardware testing, etc. Low development cost and short time to market. Computing Mirko Mariotti Go, hardware, Go ! October 22, 2018 4/42
  10. 10. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  11. 11. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  12. 12. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  13. 13. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  14. 14. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  15. 15. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  16. 16. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  17. 17. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  18. 18. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  19. 19. Technological Background Architectures Computer Architectures Multi-core and Heterogeneous Today’s computer architecture are: Multi-core,Two or more independent actual processing units execute multiple instructions at the same time. The power is given by the number of cores. Parallelism has to be addressed. Heterogeneous, different types of processing units. Cell, GPU, Parallela, TPU. The power is given by the specialization. The units data transfer has to be addressed. The scheduling has to be addressed. Mirko Mariotti Go, hardware, Go ! October 22, 2018 5/42
  20. 20. BondMachine The Idea The BondMachine The idea High level source code: Go Building a new kind of computer architecture (multi-core and heterogeneous both in cores types and interconnections) which dynamically adapt to the specific computational problem rather than be static. BM architecture Layer FPGA Concurrency and Special- ization Mirko Mariotti Go, hardware, Go ! October 22, 2018 6/42
  21. 21. BondMachine The Idea The BondMachine The idea High level source code: Go Building a new kind of computer architecture (multi-core and heterogeneous both in cores types and interconnections) which dynamically adapt to the specific computational problem rather than be static. BM architecture Layer FPGA Concurrency and Special- ization Mirko Mariotti Go, hardware, Go ! October 22, 2018 6/42
  22. 22. BondMachine The Idea The BondMachine The idea High level source code: Go Building a new kind of computer architecture (multi-core and heterogeneous both in cores types and interconnections) which dynamically adapt to the specific computational problem rather than be static. BM architecture Layer FPGA Concurrency and Special- ization Mirko Mariotti Go, hardware, Go ! October 22, 2018 6/42
  23. 23. BondMachine The Idea The BondMachine The idea High level source code: Go Building a new kind of computer architecture (multi-core and heterogeneous both in cores types and interconnections) which dynamically adapt to the specific computational problem rather than be static. BM architecture Layer FPGA Concurrency and Special- ization Mirko Mariotti Go, hardware, Go ! October 22, 2018 6/42
  24. 24. BondMachine The Idea The BondMachine The idea High level source code: Go Building a new kind of computer architecture (multi-core and heterogeneous both in cores types and interconnections) which dynamically adapt to the specific computational problem rather than be static. BM architecture Layer FPGA Concurrency and Special- ization Mirko Mariotti Go, hardware, Go ! October 22, 2018 6/42
  25. 25. BondMachine Architecture Introducing the BondMachine (BM) The BondMachine is a software ecosystem for the dynamic generation of computer architectures that: Are composed by many, possibly hundreds, computing cores. Have very small cores and not necessarily of the same type (different ISA and ABI). Have a not fixed way of interconnecting cores. May have some elements shared among cores (for example channels and shared memories). Mirko Mariotti Go, hardware, Go ! October 22, 2018 7/42
  26. 26. BondMachine Architecture Introducing the BondMachine (BM) The BondMachine is a software ecosystem for the dynamic generation of computer architectures that: Are composed by many, possibly hundreds, computing cores. Have very small cores and not necessarily of the same type (different ISA and ABI). Have a not fixed way of interconnecting cores. May have some elements shared among cores (for example channels and shared memories). Mirko Mariotti Go, hardware, Go ! October 22, 2018 7/42
  27. 27. BondMachine Architecture Introducing the BondMachine (BM) The BondMachine is a software ecosystem for the dynamic generation of computer architectures that: Are composed by many, possibly hundreds, computing cores. Have very small cores and not necessarily of the same type (different ISA and ABI). Have a not fixed way of interconnecting cores. May have some elements shared among cores (for example channels and shared memories). Mirko Mariotti Go, hardware, Go ! October 22, 2018 7/42
  28. 28. BondMachine Architecture Introducing the BondMachine (BM) The BondMachine is a software ecosystem for the dynamic generation of computer architectures that: Are composed by many, possibly hundreds, computing cores. Have very small cores and not necessarily of the same type (different ISA and ABI). Have a not fixed way of interconnecting cores. May have some elements shared among cores (for example channels and shared memories). Mirko Mariotti Go, hardware, Go ! October 22, 2018 7/42
  29. 29. BondMachine Architecture Introducing the BondMachine (BM) The BondMachine is a software ecosystem for the dynamic generation of computer architectures that: Are composed by many, possibly hundreds, computing cores. Have very small cores and not necessarily of the same type (different ISA and ABI). Have a not fixed way of interconnecting cores. May have some elements shared among cores (for example channels and shared memories). Mirko Mariotti Go, hardware, Go ! October 22, 2018 7/42
  30. 30. BondMachine Architecture The BondMachine An example Mirko Mariotti Go, hardware, Go ! October 22, 2018 8/42
  31. 31. BondMachine Connecting Processors Connecting Processor (CP) The computational unit of the BM The atomic computational unit of a BM is the “connecting processor” (CP) and has: Some general purpose registers of size Rsize. Some I/O dedicated registers of size Rsize. A set of implemented opcodes chosen among many available. Dedicated ROM and RAM. There possible operating modes. Mirko Mariotti Go, hardware, Go ! October 22, 2018 9/42
  32. 32. BondMachine Connecting Processors Connecting Processor (CP) The computational unit of the BM The atomic computational unit of a BM is the “connecting processor” (CP) and has: Some general purpose registers of size Rsize. Some I/O dedicated registers of size Rsize. A set of implemented opcodes chosen among many available. Dedicated ROM and RAM. There possible operating modes. Mirko Mariotti Go, hardware, Go ! October 22, 2018 9/42
  33. 33. BondMachine Connecting Processors Connecting Processor (CP) The computational unit of the BM The atomic computational unit of a BM is the “connecting processor” (CP) and has: Some general purpose registers of size Rsize. Some I/O dedicated registers of size Rsize. A set of implemented opcodes chosen among many available. Dedicated ROM and RAM. There possible operating modes. Mirko Mariotti Go, hardware, Go ! October 22, 2018 9/42
  34. 34. BondMachine Connecting Processors Connecting Processor (CP) The computational unit of the BM The atomic computational unit of a BM is the “connecting processor” (CP) and has: Some general purpose registers of size Rsize. Some I/O dedicated registers of size Rsize. A set of implemented opcodes chosen among many available. Dedicated ROM and RAM. There possible operating modes. Mirko Mariotti Go, hardware, Go ! October 22, 2018 9/42
  35. 35. BondMachine Connecting Processors Connecting Processor (CP) The computational unit of the BM The atomic computational unit of a BM is the “connecting processor” (CP) and has: Some general purpose registers of size Rsize. Some I/O dedicated registers of size Rsize. A set of implemented opcodes chosen among many available. Dedicated ROM and RAM. There possible operating modes. Mirko Mariotti Go, hardware, Go ! October 22, 2018 9/42
  36. 36. BondMachine Connecting Processors Connecting Processor (CP) The computational unit of the BM The atomic computational unit of a BM is the “connecting processor” (CP) and has: Some general purpose registers of size Rsize. Some I/O dedicated registers of size Rsize. A set of implemented opcodes chosen among many available. Dedicated ROM and RAM. There possible operating modes. Mirko Mariotti Go, hardware, Go ! October 22, 2018 9/42
  37. 37. BondMachine Shared Objects Shared Objects (SO) The non-computational element of the BM Alongside CPs, BondMachines include non-computing units called “Shared Objects” (SO). Examples of their purposes are: Data storage (Memories). Message passing. CP synchronization. A single SO can be shared among different CPs. To use it CPs have special instructions (opcodes) oriented to the specific SO. Four kind of SO have been developed so far: the Channel, the Shared Memory, the Barrier and a Pseudo Random Numbers Generator. Mirko Mariotti Go, hardware, Go ! October 22, 2018 10/42
  38. 38. BondMachine Shared Objects Shared Objects (SO) The non-computational element of the BM Alongside CPs, BondMachines include non-computing units called “Shared Objects” (SO). Examples of their purposes are: Data storage (Memories). Message passing. CP synchronization. A single SO can be shared among different CPs. To use it CPs have special instructions (opcodes) oriented to the specific SO. Four kind of SO have been developed so far: the Channel, the Shared Memory, the Barrier and a Pseudo Random Numbers Generator. Mirko Mariotti Go, hardware, Go ! October 22, 2018 10/42
  39. 39. BondMachine Shared Objects Shared Objects (SO) The non-computational element of the BM Alongside CPs, BondMachines include non-computing units called “Shared Objects” (SO). Examples of their purposes are: Data storage (Memories). Message passing. CP synchronization. A single SO can be shared among different CPs. To use it CPs have special instructions (opcodes) oriented to the specific SO. Four kind of SO have been developed so far: the Channel, the Shared Memory, the Barrier and a Pseudo Random Numbers Generator. Mirko Mariotti Go, hardware, Go ! October 22, 2018 10/42
  40. 40. BondMachine Shared Objects Shared Objects (SO) The non-computational element of the BM Alongside CPs, BondMachines include non-computing units called “Shared Objects” (SO). Examples of their purposes are: Data storage (Memories). Message passing. CP synchronization. A single SO can be shared among different CPs. To use it CPs have special instructions (opcodes) oriented to the specific SO. Four kind of SO have been developed so far: the Channel, the Shared Memory, the Barrier and a Pseudo Random Numbers Generator. Mirko Mariotti Go, hardware, Go ! October 22, 2018 10/42
  41. 41. BondMachine Shared Objects Shared Objects (SO) The non-computational element of the BM Alongside CPs, BondMachines include non-computing units called “Shared Objects” (SO). Examples of their purposes are: Data storage (Memories). Message passing. CP synchronization. A single SO can be shared among different CPs. To use it CPs have special instructions (opcodes) oriented to the specific SO. Four kind of SO have been developed so far: the Channel, the Shared Memory, the Barrier and a Pseudo Random Numbers Generator. Mirko Mariotti Go, hardware, Go ! October 22, 2018 10/42
  42. 42. BondMachine Shared Objects Shared Objects (SO) The non-computational element of the BM Alongside CPs, BondMachines include non-computing units called “Shared Objects” (SO). Examples of their purposes are: Data storage (Memories). Message passing. CP synchronization. A single SO can be shared among different CPs. To use it CPs have special instructions (opcodes) oriented to the specific SO. Four kind of SO have been developed so far: the Channel, the Shared Memory, the Barrier and a Pseudo Random Numbers Generator. Mirko Mariotti Go, hardware, Go ! October 22, 2018 10/42
  43. 43. BondMachine Tools Handle the BM computer architecture The BM computer architecture is managed by a set of tools to: build a specify architecture modify a pre-existing architecture simulate or emulate the behavior Generate the Register Tranfer Code (RTL) Processor Builder Selects the single processor, assem- bles and disassem- bles, saves on disk as JSON, creates the RTL code of a CP BondMachine Builder Connects CPs and SOs together in custom topologies, loads and saves on disk as JSON, create BM’s RTL code Simulation Framework Simulates the be- haviour, emulates a BM on a standard Linux workstation Mirko Mariotti Go, hardware, Go ! October 22, 2018 11/42
  44. 44. BondMachine Tools Handle the BM computer architecture The BM computer architecture is managed by a set of tools to: build a specify architecture modify a pre-existing architecture simulate or emulate the behavior Generate the Register Tranfer Code (RTL) Processor Builder Selects the single processor, assem- bles and disassem- bles, saves on disk as JSON, creates the RTL code of a CP BondMachine Builder Connects CPs and SOs together in custom topologies, loads and saves on disk as JSON, create BM’s RTL code Simulation Framework Simulates the be- haviour, emulates a BM on a standard Linux workstation Mirko Mariotti Go, hardware, Go ! October 22, 2018 11/42
  45. 45. BondMachine Tools Handle the BM computer architecture The BM computer architecture is managed by a set of tools to: build a specify architecture modify a pre-existing architecture simulate or emulate the behavior Generate the Register Tranfer Code (RTL) Processor Builder Selects the single processor, assem- bles and disassem- bles, saves on disk as JSON, creates the RTL code of a CP BondMachine Builder Connects CPs and SOs together in custom topologies, loads and saves on disk as JSON, create BM’s RTL code Simulation Framework Simulates the be- haviour, emulates a BM on a standard Linux workstation Mirko Mariotti Go, hardware, Go ! October 22, 2018 11/42
  46. 46. BondMachine Tools Handle the BM computer architecture The BM computer architecture is managed by a set of tools to: build a specify architecture modify a pre-existing architecture simulate or emulate the behavior Generate the Register Tranfer Code (RTL) Processor Builder Selects the single processor, assem- bles and disassem- bles, saves on disk as JSON, creates the RTL code of a CP BondMachine Builder Connects CPs and SOs together in custom topologies, loads and saves on disk as JSON, create BM’s RTL code Simulation Framework Simulates the be- haviour, emulates a BM on a standard Linux workstation Mirko Mariotti Go, hardware, Go ! October 22, 2018 11/42
  47. 47. Moulding API and Libraries Use the BM computer architecture Mapping specific computational problems to BMs Symbond Map symbolic mathematical expressoin to BM Boolbond Map boolean sys- tems to BM Matrixwork Basic matrix com- putation Neuralbond Map neural net- works to BM Evolutive BM Evolutionary com- puting to BM tf2bm Map TensorFlow graphs to BM Mirko Mariotti Go, hardware, Go ! October 22, 2018 12/42
  48. 48. Moulding API and Libraries Use the BM computer architecture Mapping specific computational problems to BMs Symbond Map symbolic mathematical expressoin to BM Boolbond Map boolean sys- tems to BM Matrixwork Basic matrix com- putation Neuralbond Map neural net- works to BM Evolutive BM Evolutionary com- puting to BM tf2bm Map TensorFlow graphs to BM Mirko Mariotti Go, hardware, Go ! October 22, 2018 12/42
  49. 49. Moulding API and Libraries Use the BM computer architecture Mapping specific computational problems to BMs Symbond Map symbolic mathematical expressoin to BM Boolbond Map boolean sys- tems to BM Matrixwork Basic matrix com- putation Neuralbond Map neural net- works to BM Evolutive BM Evolutionary com- puting to BM tf2bm Map TensorFlow graphs to BM Mirko Mariotti Go, hardware, Go ! October 22, 2018 12/42
  50. 50. Moulding API and Libraries Use the BM computer architecture Mapping specific computational problems to BMs Symbond Map symbolic mathematical expressoin to BM Boolbond Map boolean sys- tems to BM Matrixwork Basic matrix com- putation Neuralbond Map neural net- works to BM Evolutive BM Evolutionary com- puting to BM tf2bm Map TensorFlow graphs to BM Mirko Mariotti Go, hardware, Go ! October 22, 2018 12/42
  51. 51. Moulding API and Libraries Use the BM computer architecture Mapping specific computational problems to BMs Symbond Map symbolic mathematical expressoin to BM Boolbond Map boolean sys- tems to BM Matrixwork Basic matrix com- putation Neuralbond Map neural net- works to BM Evolutive BM Evolutionary com- puting to BM tf2bm Map TensorFlow graphs to BM Mirko Mariotti Go, hardware, Go ! October 22, 2018 12/42
  52. 52. Moulding API and Libraries Use the BM computer architecture Mapping specific computational problems to BMs Symbond Map symbolic mathematical expressoin to BM Boolbond Map boolean sys- tems to BM Matrixwork Basic matrix com- putation Neuralbond Map neural net- works to BM Evolutive BM Evolutionary com- puting to BM tf2bm Map TensorFlow graphs to BM Mirko Mariotti Go, hardware, Go ! October 22, 2018 12/42
  53. 53. Moulding API and Libraries Use the BM computer architecture Mapping specific computational problems to BMs Symbond Map symbolic mathematical expressoin to BM Boolbond Map boolean sys- tems to BM Matrixwork Basic matrix com- putation Neuralbond Map neural net- works to BM Evolutive BM Evolutionary com- puting to BM tf2bm Map TensorFlow graphs to BM Mirko Mariotti Go, hardware, Go ! October 22, 2018 12/42
  54. 54. Moulding Bondgo Bondgo The major innovation of the BondMachine Project is its compiler. Bondgo is the name chosen for the compiler developed for the BondMachine. The compiler source language is Go as the name suggest. Mirko Mariotti Go, hardware, Go ! October 22, 2018 13/42
  55. 55. Moulding Bondgo Bondgo Bondgo does something different from standard compilers ... Mirko Mariotti Go, hardware, Go ! October 22, 2018 14/42
  56. 56. Moulding Bondgo Bondgo Bondgo does something different from standard compilers ... high level GO source Mirko Mariotti Go, hardware, Go ! October 22, 2018 14/42
  57. 57. Moulding Bondgo Bondgo Bondgo does something different from standard compilers ... high level GO source assembly file Compiling Mirko Mariotti Go, hardware, Go ! October 22, 2018 14/42
  58. 58. Moulding Bondgo Bondgo Bondgo does something different from standard compilers ... high level GO source assembly file Compiling CP specs Arch generating Mirko Mariotti Go, hardware, Go ! October 22, 2018 14/42
  59. 59. Moulding Bondgo Bondgo Bondgo does something different from standard compilers ... high level GO source assembly file Compiling CP specs Arch generating machine code Assembling Mirko Mariotti Go, hardware, Go ! October 22, 2018 14/42
  60. 60. Moulding Bondgo Bondgo Bondgo does something different from standard compilers ... high level GO source assembly file Compiling CP specs Arch generating machine code Assembling Processor implementation Mirko Mariotti Go, hardware, Go ! October 22, 2018 14/42
  61. 61. Moulding Bondgo Bondgo Bondgo does something different from standard compilers ... high level GO source assembly file Compiling CP specs Arch generating machine code Assembling Processor implementation Mirko Mariotti Go, hardware, Go ! October 22, 2018 14/42
  62. 62. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  63. 63. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  64. 64. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  65. 65. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  66. 66. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  67. 67. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  68. 68. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  69. 69. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  70. 70. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  71. 71. Moulding Bondgo Bondgo A first example counter go source package main import ( "bondgo" ) func main () { var outgoing bondgo.Output var reg_int uint8 outgoing = bondgo.Make(bondgo.Output , 3) reg_int = 0 for { bondgo.IOWrite(outgoing , reg_int) reg_int ++ } } bondgo –input-file counter.go -mpm BM JSON rapresentation counter asm clr r0 rset r1 0 cpy r0 r1 cpy r1 r0 r2o r1 o0 inc r0 j 3 bondmachine tool BM HDL code FPGA procbuilder tool Binary Mirko Mariotti Go, hardware, Go ! October 22, 2018 15/42
  72. 72. Moulding Bondgo Bondgo ... bondgo may not only create the binaries, but also the CP architecture, and ... Mirko Mariotti Go, hardware, Go ! October 22, 2018 16/42
  73. 73. Moulding Bondgo Bondgo ... it can do even much more interesting things when compiling concurrent programs. Mirko Mariotti Go, hardware, Go ! October 22, 2018 17/42
  74. 74. Moulding Bondgo Bondgo ... it can do even much more interesting things when compiling concurrent programs. high level GO source Mirko Mariotti Go, hardware, Go ! October 22, 2018 17/42
  75. 75. Moulding Bondgo Bondgo ... it can do even much more interesting things when compiling concurrent programs. high level GO source assembly CP 1 assembly CP 2assembly CP 3assembly CP 4assembly CP ... assembly CP N Compiling Mirko Mariotti Go, hardware, Go ! October 22, 2018 17/42
  76. 76. Moulding Bondgo Bondgo ... it can do even much more interesting things when compiling concurrent programs. high level GO source assembly CP 1 assembly CP 2assembly CP 3assembly CP 4assembly CP ... assembly CP N Compiling CP 1 specs CP 2 CP 3 CP 4 CP ... CP N Archs generating Mirko Mariotti Go, hardware, Go ! October 22, 2018 17/42
  77. 77. Moulding Bondgo Bondgo ... it can do even much more interesting things when compiling concurrent programs. high level GO source assembly CP 1 assembly CP 2assembly CP 3assembly CP 4assembly CP ... assembly CP N Compiling CP 1 specs CP 2 CP 3 CP 4 CP ... CP N Archs generating Asm and Binaries Mirko Mariotti Go, hardware, Go ! October 22, 2018 17/42
  78. 78. Moulding Bondgo Bondgo ... it can do even much more interesting things when compiling concurrent programs. high level GO source assembly CP 1 assembly CP 2assembly CP 3assembly CP 4assembly CP ... assembly CP N Compiling CP 1 specs CP 2 CP 3 CP 4 CP ... CP N Archs generating Asm and Binaries Interconnections Mirko Mariotti Go, hardware, Go ! October 22, 2018 17/42
  79. 79. Moulding Bondgo Bondgo ... it can do even much more interesting things when compiling concurrent programs. high level GO source assembly CP 1 assembly CP 2assembly CP 3assembly CP 4assembly CP ... assembly CP N Compiling CP 1 specs CP 2 CP 3 CP 4 CP ... CP N Archs generating Asm and Binaries BondMachine Mirko Mariotti Go, hardware, Go ! October 22, 2018 17/42
  80. 80. Moulding Bondgo Bondgo A multi-core example multi-core counter package main import ( "bondgo" ) func pong () { var in0 bondgo.Input var out0 bondgo.Output in0 = bondgo.Make(bondgo.Input , 3) out0 = bondgo.Make(bondgo.Output , 5) for { bondgo.IOWrite(out0 , bondgo.IORead(in0)+1) } } func main () { var in0 bondgo.Input var out0 bondgo.Output in0 = bondgo.Make(bondgo.Input , 5) out0 = bondgo.Make(bondgo.Output , 3) device_0: go pong () for { bondgo.IOWrite(out0 , bondgo.IORead(in0)) } } Mirko Mariotti Go, hardware, Go ! October 22, 2018 18/42
  81. 81. Moulding Bondgo Bondgo A multi-core example Compiling the code with the bondgo compiler: bondgo -input-file ds.go -mpm The toolchain perform the following steps: Map the two goroutines to two hardware cores. Creates two types of core, each one optimized to execute the assigned goroutine. Creates the two binaries. Connected the two core as inferred from the source code, using special IO registers. The result is a multicore BondMachine: Mirko Mariotti Go, hardware, Go ! October 22, 2018 19/42
  82. 82. Moulding Bondgo Bondgo A multi-core example Mirko Mariotti Go, hardware, Go ! October 22, 2018 20/42
  83. 83. Moulding Bondgo Compiling Architectures One of the most important result The architecture creation is a part of the compilation process. Mirko Mariotti Go, hardware, Go ! October 22, 2018 21/42
  84. 84. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  85. 85. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  86. 86. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  87. 87. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  88. 88. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  89. 89. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  90. 90. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  91. 91. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  92. 92. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  93. 93. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  94. 94. Moulding Bondgo Bondgo Go in hardware Bondgo implements a sort of “Go in hardware”. High level Go source code is directly mapped to interconnected processors without Operating Systems or runtimes. Goroutines Cores Channels Channel SOs Variables (local) CP RAM segments Variables (by val) CH messages or IO regs Variables (by ref) Shared RAM segments Mirko Mariotti Go, hardware, Go ! October 22, 2018 22/42
  95. 95. Moulding Bondgo Bondgo An example bondgo stream processing example package main import ( "bondgo" ) func streamprocessor (a *[] uint8 , b *[] uint8 , c *[] uint8 , gid uint8) { (*c)[gid] = (*a)[gid] + (*b)[gid] } func main () { a := make ([] uint8 , 256) b := make ([] uint8 , 256) c := make ([] uint8 , 256) // ... some a and b values fill for i := 0; i < 256; i++ { go streamprocessor (&a, &b, &c, uint8(i)) } } The compilation of this example results in the creation of a 257 CPs where 256 are the stream processors executing the code in the function called streamprocessor, and one is the coordinating CP. Each stream processor is optimized and capable only to make additions since it is the only operation requested by the source code. The three slices created on the main function are passed by reference to the Goroutines then a shared RAM is created by the Bondgo compiler available to the generated CPs. Mirko Mariotti Go, hardware, Go ! October 22, 2018 23/42
  96. 96. Hardware Hardware implementation FPGA The RTL code for the BondMachine is written in Verilog and System Verilog, and has been tested on these devices/system: Digilent Basys3 - Xilinx Artix-7 - Vivado. Kintex7 Evaluation Board - Vivado. Digilent Zedboard - Xilinx Zynq 7020 - Vivado. Linux - Iverilog. Terasic De10nano - Intel Cyclone V - Quartus Within the project other firmwares have been written or tested: Microchip ENC28J60 Ethernet interface controller. Microchip ENC424J600 10/100 Base-T Ethernet interface controller. ESP8266 Wi-Fi chip. Mirko Mariotti Go, hardware, Go ! October 22, 2018 24/42
  97. 97. Prototype The Prototype The project has been selected for the participation at MakerFaire 2016 Rome (The Europen Edition) and a prototype has been assembled and presented. First run: https://youtube.com/embed/hukTrGxTb7A Mirko Mariotti Go, hardware, Go ! October 22, 2018 25/42
  98. 98. Prototype Toolchains A set of toolchains allow the build and the direct deploy to a target device of BondMachines. Bondgo Toolchain example A file local.mk contains references to the source code as well all the build necessities. make bondmachine creates the JSON representation of the BM and assemble its code. make show displays a graphical representation of the BM. make simulate start a simulation. make videosim create a simulation video. make flash the device into the destination target. Mirko Mariotti Go, hardware, Go ! October 22, 2018 26/42
  99. 99. Clustering BondMachine Clustering So far we saw: An user friendly approach to create processors (single core). Optimizing a single device to support intricate computational work-flows (multi-cores) over an heterogeneous layer. Interconnected BondMachines What if we could extend the this layer to multiple interconnected devices ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 27/42
  100. 100. Clustering BondMachine Clustering So far we saw: An user friendly approach to create processors (single core). Optimizing a single device to support intricate computational work-flows (multi-cores) over an heterogeneous layer. Interconnected BondMachines What if we could extend the this layer to multiple interconnected devices ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 27/42
  101. 101. Clustering BondMachine Clustering So far we saw: An user friendly approach to create processors (single core). Optimizing a single device to support intricate computational work-flows (multi-cores) over an heterogeneous layer. Interconnected BondMachines What if we could extend the this layer to multiple interconnected devices ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 27/42
  102. 102. Clustering BondMachine Clustering So far we saw: An user friendly approach to create processors (single core). Optimizing a single device to support intricate computational work-flows (multi-cores) over an heterogeneous layer. Interconnected BondMachines What if we could extend the this layer to multiple interconnected devices ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 27/42
  103. 103. Clustering BondMachine Clustering The same logic existing among CP have been extended among different BondMachines organized in clusters. Protocols, one ethernet called etherbond and one using UDP called udpbond have been created for the purpose. FPGA based BondMachines, standard Linux Workstations, Emulated BondMachines might join a cluster an contribute to a single distributed computational problem. Mirko Mariotti Go, hardware, Go ! October 22, 2018 28/42
  104. 104. Clustering BondMachine Clustering The same logic existing among CP have been extended among different BondMachines organized in clusters. Protocols, one ethernet called etherbond and one using UDP called udpbond have been created for the purpose. FPGA based BondMachines, standard Linux Workstations, Emulated BondMachines might join a cluster an contribute to a single distributed computational problem. Mirko Mariotti Go, hardware, Go ! October 22, 2018 28/42
  105. 105. Clustering BondMachine Clustering The same logic existing among CP have been extended among different BondMachines organized in clusters. Protocols, one ethernet called etherbond and one using UDP called udpbond have been created for the purpose. FPGA based BondMachines, standard Linux Workstations, Emulated BondMachines might join a cluster an contribute to a single distributed computational problem. Mirko Mariotti Go, hardware, Go ! October 22, 2018 28/42
  106. 106. Clustering BondMachine Clustering Mirko Mariotti Go, hardware, Go ! October 22, 2018 29/42
  107. 107. Clustering BondMachine Clustering A distributed example distributed counter package main import ( "bondgo" ) func pong () { var in0 bondgo.Input var out0 bondgo.Output in0 = bondgo.Make(bondgo.Input , 3) out0 = bondgo.Make(bondgo.Output , 5) for { bondgo.IOWrite(out0 , bondgo.IORead(in0)+1) } } func main () { var in0 bondgo.Input var out0 bondgo.Output in0 = bondgo.Make(bondgo.Input , 5) out0 = bondgo.Make(bondgo.Output , 3) device_1: go pong () for { bondgo.IOWrite(out0 , bondgo.IORead(in0)) } } Mirko Mariotti Go, hardware, Go ! October 22, 2018 30/42
  108. 108. Clustering BondMachine Clustering A distributed example Mirko Mariotti Go, hardware, Go ! October 22, 2018 31/42
  109. 109. Clustering BondMachine Clustering A distributed example The result is: https://youtube.com/embed/g9xYHK0zca4 A general result Parts of the system can be redeployed among different devices without changing the system behavior (only the performances). Mirko Mariotti Go, hardware, Go ! October 22, 2018 32/42
  110. 110. Clustering BondMachine Clustering Results Results User can deploy an entire HW/SW cluster starting from a code written in Go. Workstation with emulated BondMachines, workstation with etherbond drivers, standalone BondMachines (FPGA) may join these clusters. Mirko Mariotti Go, hardware, Go ! October 22, 2018 33/42
  111. 111. Clustering BondMachine Clustering Results Results User can deploy an entire HW/SW cluster starting from a code written in Go. Workstation with emulated BondMachines, workstation with etherbond drivers, standalone BondMachines (FPGA) may join these clusters. Mirko Mariotti Go, hardware, Go ! October 22, 2018 33/42
  112. 112. Project History Project History May 2016 - Idea presented at INFN-computing and Networking Commission Workshop 2016. September 2016 - The first prototype is built. October 2016 - It is Selected and the prototype is presented at “Makerfaire 2016 Rome (The European edition)”. November 2016 - Presented at “Umbria Business Match 2016”. March 2017 - First tests for Physics applications. November 2017 - Presented at “Umbria Business Match 2017”. December 2107 - Submitted at InnovateFPGA 2018 Mirko Mariotti Go, hardware, Go ! October 22, 2018 34/42
  113. 113. Project History Project History May 2016 - Idea presented at INFN-computing and Networking Commission Workshop 2016. September 2016 - The first prototype is built. October 2016 - It is Selected and the prototype is presented at “Makerfaire 2016 Rome (The European edition)”. November 2016 - Presented at “Umbria Business Match 2016”. March 2017 - First tests for Physics applications. November 2017 - Presented at “Umbria Business Match 2017”. December 2107 - Submitted at InnovateFPGA 2018 Mirko Mariotti Go, hardware, Go ! October 22, 2018 34/42
  114. 114. Project History Project History May 2016 - Idea presented at INFN-computing and Networking Commission Workshop 2016. September 2016 - The first prototype is built. October 2016 - It is Selected and the prototype is presented at “Makerfaire 2016 Rome (The European edition)”. November 2016 - Presented at “Umbria Business Match 2016”. March 2017 - First tests for Physics applications. November 2017 - Presented at “Umbria Business Match 2017”. December 2107 - Submitted at InnovateFPGA 2018 Mirko Mariotti Go, hardware, Go ! October 22, 2018 34/42
  115. 115. Project History Project History InnovateFPGA 2018 Feb 2018 - Reached the EMEA Semifinal. Jun 2018 - Reached the EMEA Regional final. Jul 2018 - EMEA Silver Award, Reached the Grand Final. Aug 2018 - Presented at Intel Campus, Santa Jose (CA) . Aug 2018 - Won the Iron Award in the Grand Final. Mirko Mariotti Go, hardware, Go ! October 22, 2018 35/42
  116. 116. Project History Project History InnovateFPGA 2018 Feb 2018 - Reached the EMEA Semifinal. Jun 2018 - Reached the EMEA Regional final. Jul 2018 - EMEA Silver Award, Reached the Grand Final. Aug 2018 - Presented at Intel Campus, Santa Jose (CA) . Aug 2018 - Won the Iron Award in the Grand Final. Mirko Mariotti Go, hardware, Go ! October 22, 2018 36/42
  117. 117. Project History Project History InnovateFPGA 2018 Feb 2018 - Reached the EMEA Semifinal. Jun 2018 - Reached the EMEA Regional final. Jul 2018 - EMEA Silver Award, Reached the Grand Final. Aug 2018 - Presented at Intel Campus, Santa Jose (CA) . Aug 2018 - Won the Iron Award in the Grand Final. Mirko Mariotti Go, hardware, Go ! October 22, 2018 37/42
  118. 118. Project History Project History InnovateFPGA 2018 Feb 2018 - Reached the EMEA Semifinal. Jun 2018 - Reached the EMEA Regional final. Jul 2018 - EMEA Silver Award, Reached the Grand Final. Aug 2018 - Presented at Intel Campus, Santa Jose (CA) . Aug 2018 - Won the Iron Award in the Grand Final. Mirko Mariotti Go, hardware, Go ! October 22, 2018 38/42
  119. 119. Project History Project History InnovateFPGA 2018 Feb 2018 - Reached the EMEA Semifinal. Jun 2018 - Reached the EMEA Regional final. Jul 2018 - EMEA Silver Award, Reached the Grand Final. Aug 2018 - Presented at Intel Campus, Santa Jose (CA) . Aug 2018 - Won the Iron Award in the Grand Final. Mirko Mariotti Go, hardware, Go ! October 22, 2018 39/42
  120. 120. Conclusions Conclusions The BondMachine is a new kind of computing device made possible in practice only by the emerging of new re-programmable hardware technologies such as FPGA. Keeping the register machine abstraction it is possible to use language like Go, removing the need of having a general purpose architecture. The result of this process is the construction of a computer architec- ture that is not anymore a static constraint where computing occurs but its creation becomes a part of the computing process, gaining computing power and flexibility. Over this abstraction is it possible to create a full computing Ecosys- tem. Mirko Mariotti Go, hardware, Go ! October 22, 2018 40/42
  121. 121. Future work Future work The project is a prototype. Include new processor shared objects and currently unsupported opcodes. Extend the compiler to include more data structures. Improve the networking including new interconnection firmwares. Work on BondMachine as accelerators. What would an OS for BondMachines look like ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 41/42
  122. 122. Future work Future work The project is a prototype. Include new processor shared objects and currently unsupported opcodes. Extend the compiler to include more data structures. Improve the networking including new interconnection firmwares. Work on BondMachine as accelerators. What would an OS for BondMachines look like ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 41/42
  123. 123. Future work Future work The project is a prototype. Include new processor shared objects and currently unsupported opcodes. Extend the compiler to include more data structures. Improve the networking including new interconnection firmwares. Work on BondMachine as accelerators. What would an OS for BondMachines look like ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 41/42
  124. 124. Future work Future work The project is a prototype. Include new processor shared objects and currently unsupported opcodes. Extend the compiler to include more data structures. Improve the networking including new interconnection firmwares. Work on BondMachine as accelerators. What would an OS for BondMachines look like ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 41/42
  125. 125. Future work Future work The project is a prototype. Include new processor shared objects and currently unsupported opcodes. Extend the compiler to include more data structures. Improve the networking including new interconnection firmwares. Work on BondMachine as accelerators. What would an OS for BondMachines look like ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 41/42
  126. 126. Future work Future work The project is a prototype. Include new processor shared objects and currently unsupported opcodes. Extend the compiler to include more data structures. Improve the networking including new interconnection firmwares. Work on BondMachine as accelerators. What would an OS for BondMachines look like ? Mirko Mariotti Go, hardware, Go ! October 22, 2018 41/42
  127. 127. Future work If you have question/curiosity/interest for joining the project: Mirko Mariotti mirko.mariotti@unipg.it http://bondmachine.fisica.unipg.it Mirko Mariotti Go, hardware, Go ! October 22, 2018 42/42

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