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The Front-End Electronics of the HADES timing RPCs wall. Daniel Belver Fernández  LabCAF-University of Santiago de Compost...
<ul><li>The HADES tRPC TOF wall. </li></ul><ul><li>The Front-End Electronics (FEE) developed for the RPCs. </li></ul><ul><...
HADES tRPC TOF wall
The RPC Front-End Electronics (FEE) t 1 t 2 FEE-DBOs (108 DBOs/sector x6) FEE-MBOs (16 MBOs/sector x6) Mechanical support ...
FEE and DAQ system 4 MBOs/TRB  8 DBOs/MBO  4 cells/DBO 4 TRB/sector  2 LV/sector See M. Traxler talk Trigger ∑ Front-End M...
<ul><li>4-channel & 6-layer board  connected to 4 RPC cells. </li></ul><ul><li>1 amplifier (G=35.5 dB, BW=2 GHz, NF=4.5 dB...
TI OPA690 amp integrates the amplified signal (QtoW algorithm) PHILIPS BGM1013 amp (35.5 dB at 1 GHz) Protected by PHILIPS...
MAX9601 dual PECL discriminator: LE   used for cut/shape the output pulse TI SN65LVDS100 PECL-LVDS converter PHILIPS BFT92...
MotherBOard (MBO) <ul><li>Interfaces board between DBO and DAQ system (TRB). </li></ul><ul><li>8-layer board  providing me...
<ul><ul><li>Delivers the  timing signals  from 8 DBOs to the TRB. </li></ul></ul><ul><ul><li>DBO supply voltages ( + 5V,-5...
FEE performances: time resolution Q=V max  x e -t/R in C R in C>>t r Q=C x V σ t(FEE+TRB)  <40 ps/ch ToF threshold=-20mV σ...
<ul><li>Charge measurements through QtoW algorithm, using pulser signals and RPC signals measurements. </li></ul>FEE perfo...
In-beam results QtoW spectrums for one cell ToF threshold=-50 mV σ t =76 ps  3σ tails=2.2%
Summary of the FEE performances
<ul><li>Immediately  application of the FEE to the TRASGO project. </li></ul>FEE adaptation to TRASGO Possible FEE positio...
<ul><li>Power consumption for 128 channels: </li></ul><ul><li>•  1 TRB   10-20 W. </li></ul><ul><li>•  4 MBOs+32 DBOs    9...
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D Belver FEE for Trasgos

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D Belver FEE for Trasgos

  1. 1. The Front-End Electronics of the HADES timing RPCs wall. Daniel Belver Fernández LabCAF-University of Santiago de Compostela
  2. 2. <ul><li>The HADES tRPC TOF wall. </li></ul><ul><li>The Front-End Electronics (FEE) developed for the RPCs. </li></ul><ul><li>FEE performances. </li></ul><ul><ul><li>Time resolution. </li></ul></ul><ul><ul><li>Calibration of the ‘Charge to Width’ algorithm. </li></ul></ul><ul><ul><li>In beam results. </li></ul></ul><ul><li>Summary of the main FEE performances. </li></ul><ul><li>Adaptation of the FEE to TRASGO detector. </li></ul>OUTLINE
  3. 3. HADES tRPC TOF wall
  4. 4. The RPC Front-End Electronics (FEE) t 1 t 2 FEE-DBOs (108 DBOs/sector x6) FEE-MBOs (16 MBOs/sector x6) Mechanical support board, providing power supply, test signal and threshold DAQs. Amplifying and timing discrimination board (QtoW algorithm).
  5. 5. FEE and DAQ system 4 MBOs/TRB 8 DBOs/MBO 4 cells/DBO 4 TRB/sector 2 LV/sector See M. Traxler talk Trigger ∑ Front-End MBO DBO RPC signals RPC signals RPC cells DC-DC converter Commercial power supply Low voltage system 5 3.3 -5 5V,-5V,3.3V 48V Ethernet TRB Data acquisition system
  6. 6. <ul><li>4-channel & 6-layer board connected to 4 RPC cells. </li></ul><ul><li>1 amplifier (G=35.5 dB, BW=2 GHz, NF=4.5 dB) . </li></ul><ul><li>Generates timing and trigger signals. </li></ul><ul><li>Time & charge encoded in a single LVDS digital output (low power consumption and high noise immunity). </li></ul><ul><li>- Leading edge  Arrival time (ToF measure). </li></ul><ul><li>- Pulse width  Charge (QtoW algorithm). </li></ul>DaughterBOard (DBO) All SMT available components (R & C 0402 size) SAMTEC connector (40 pins, 0.8 mm pitch) Area=5x4.5 cm 2 1 3 2 4 Width ~charge (QtoW) Arrival time LVDS
  7. 7. TI OPA690 amp integrates the amplified signal (QtoW algorithm) PHILIPS BGM1013 amp (35.5 dB at 1 GHz) Protected by PHILIPS BAV199 2-diodes RPC cell One DBO channel: analog stage Analog stage Digital stage Amplified RPC signal Integrated signal
  8. 8. MAX9601 dual PECL discriminator: LE used for cut/shape the output pulse TI SN65LVDS100 PECL-LVDS converter PHILIPS BFT92 PNP wideband (5 GHz) transistor for multiplicity trigger sum One DBO channel: digital stage Analog stage Digital stage Discriminator output Latch Enable (LE) Latch Enable/ (LE/)
  9. 9. MotherBOard (MBO) <ul><li>Interfaces board between DBO and DAQ system (TRB). </li></ul><ul><li>8-layer board providing mechanical support to 32 channels (8 DBOs) or 12 channels (3 DBOs). </li></ul>Area 40x6 cm 2 Area 16.5x6.5 cm 2
  10. 10. <ul><ul><li>Delivers the timing signals from 8 DBOs to the TRB. </li></ul></ul><ul><ul><li>DBO supply voltages ( + 5V,-5V,+3.3V) Low-Dropout Regulators (ripple filtering). </li></ul></ul><ul><ul><li>DACs for the thresholds of the discriminator (DAC program interface). </li></ul></ul><ul><ul><li>Test signals distribution. </li></ul></ul><ul><ul><li>Combines the 32 multiplicity DBOS signals low level trigger signal . </li></ul></ul>MBO schematic
  11. 11. FEE performances: time resolution Q=V max x e -t/R in C R in C>>t r Q=C x V σ t(FEE+TRB) <40 ps/ch ToF threshold=-20mV σ t(FEE) < 17 ps/ch (Q>90 fC)
  12. 12. <ul><li>Charge measurements through QtoW algorithm, using pulser signals and RPC signals measurements. </li></ul>FEE performances: QtoW calibration Streamer region Avalanche region
  13. 13. In-beam results QtoW spectrums for one cell ToF threshold=-50 mV σ t =76 ps 3σ tails=2.2%
  14. 14. Summary of the FEE performances
  15. 15. <ul><li>Immediately application of the FEE to the TRASGO project. </li></ul>FEE adaptation to TRASGO Possible FEE positions Cut view of the TRASGO DBOs placed over one MBO TRB between RPC planes
  16. 16. <ul><li>Power consumption for 128 channels: </li></ul><ul><li>• 1 TRB 10-20 W. </li></ul><ul><li>• 4 MBOs+32 DBOs 90-100 W. </li></ul><ul><li>Possible solutions (new FEE approach): </li></ul><ul><ul><li>Adapt other RPC-FEE as NINO (CERN) or PADI (GSI). </li></ul></ul><ul><ul><li>Integrate the FEE in an integrated circuit (ASIC). </li></ul></ul>Power consumption ≈120 W per TRB FEE improvements for TRASGO Easy for the power supply but not for solar panels.
  17. 17. Thanks for your attention!

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