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Lecture 2

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Amplifier Deisgn

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Lecture 2

  1. 1. Microelectronic Circuits Amplifier design Bits, pilani
  2. 2. MOSFET AMPLIFIER Bits, pilani
  3. 3. Aim Design an amplifier of gain 30 v/v Choose the device (MOS , BJT) Set DC bias Choose a circuit topology Design Analyse Re-design Bits, pilani
  4. 4. MOSFET TRANSCONDUCTANCE ----defines gain Bits, pilani
  5. 5. SYMBOLS Bits, pilani
  6. 6. CHOICE OF INPUT AND OUTPUT 3 parameters---VGS, VDS, ID, (Vsb= for advanced course) ID α (VGS, VDS) ID---captures variation----output either VGS / VDS can be input but if VDS is input, no other terminal is available for output so only VGS can be the input Now what should be Vds?
  7. 7. Where to bias ? Max gain-------MAX IDRD------------MAX ID Min distortion ID= f (VGS)------SATURATION REGION Max current, ID captures variations of VGS faithfully ID= f (VGS, VDS)-----------LINEAR REGION Min current, ID varies with VGS , VDS ---(extra variation) Bits, pilani
  8. 8. MOS equations
  9. 9. Transfer charac. Bits, pilani
  10. 10. Output charac.—load line Bits, pilani
  11. 11. MOS AMPLIFIER Bits, pilani
  12. 12. DC BIAS Bits, pilani
  13. 13. Understanding MOS Bits, pilani
  14. 14. Bits, pilani
  15. 15. Bits, pilani
  16. 16. Bits, pilani
  17. 17. MODEL Bits, pilani
  18. 18. SECONDARY EFFECTS Bits, pilani
  19. 19. CHANNEL LENGTH MODULATION Bits, pilani
  20. 20. ID increases with VDS
  21. 21. MODIFIED MODEL & equ W I D = K [VGS − VT 0 ] (1 + λVDS ) 2 L Bits, pilani
  22. 22. BODY BIAS EFFECT VT= VTO +γ [(2ΦF + VSB) ½ – (2ΦF)½ ] 2qN Aε s γ = C ox WI D = K [VGS − VT ] (1 + λVDS ) 2 L ID reduces Bits, pilani
  23. 23. Impact of body bias Id Vsb1 Vsb2 Vsb3 Vt1 Vt2 Vt3 Vgs Vsb1< Vsb2 < Vsb3
  24. 24. Temperature effects Vt, K’ , µ are temperature sensitive Vt reduces at a rate of 2mv per degree rise in temp. Breakdown--- Oxide breakdown, punch through Bits, pilani
  25. 25. Techniques to set DC bias--DISCRETE CKT. Using two supply voltages or generate VGS Bits, pilani
  26. 26. STABILITY OF Q POINT– FIX VGS Vt reduces at high temperature Vt
  27. 27. Fix VG, but VS can adjust. ID rolls backUsing degeneration resistance VG = VGS + I D RS
  28. 28. Id Q’Id2 Q Id1 -1/Rs Vt1 Vgs1 Vt2 Vgs
  29. 29. Using single DC supply POTENTIAL DIVIDER BIAS Bits, pilani VG = VGS + I D RS
  30. 30. Q point stability Case-1------Vg increases due to power supply fluctuation Vg↑ Vgs↑ Id↑ (Id Rs) ↑ Vgs↓ Case-2----- VT decreases due to temperature fluctuation VT ↓ ( Vgs – VT )↑ Id↑ (Id Rs) ↑ Vgs↓ ( Vgs – VT ) ↓ Bits, pilani
  31. 31. Setting DC BIAS DRAIN TO GATE FEEDBACK BIAS V DD = VGS + I D RD Bits, pilani
  32. 32. Sensitivity
  33. 33. Sensitivity of Id to Vdd fluctuation [V G − V GS ]= I R1=1M R2=10K D Rs=1k Rs ID=1mAIf Vgs constant Vdd=10v  R2  R + R   ∂I D   1 2 ∂I D 0.1 ≈ Vdd  =S = ID  ∂Vdd  Rs ∂Vdd
  34. 34. If Vgs not constant 2I D VGS = Vt + (W )  Kn   L  ID Substitute Vgs and recalculate SV DD
  35. 35. Sensitivity of Id to Temp. change  ∂VG ∂VGS  ∂I D ∂Rs  ∂T − ∂T  = Rs ∂T + I D ∂T   Bits, pilani
  36. 36. Bits, pilani
  37. 37. Bits, pilani
  38. 38. IC BIASING—current bias Bits, pilani
  39. 39. PMOS Current Mirror Bits, pilani
  40. 40. Matched transistors— keep fab.conditions same Bits, pilani
  41. 41. Bits, pilani
  42. 42. Why current biasing for ICs? To do away with coupling capacitors Bits, pilani
  43. 43. Why do we need coupling capacitors? To isolate the d.c bias voltges of two adjacent amplifiers biased using voltage biasing technique Bits, pilani
  44. 44. GAIN EXPRESSION Bits, pilani
  45. 45. Amplifier equ.y, x voltage or currentFor a narrow range of x Bits, pilani
  46. 46. Current expression in sat. region Bits, pilani
  47. 47. Output voltage/ gain expression Bits, pilani
  48. 48. Distortion Bits, pilani
  49. 49. SMALL SIGNAL APPROX HOW MUCH SMALL? Vgs << 2Vov Bits, pilani
  50. 50. GAIN IN SATURATION REGION, IN LINEAR AV= - RD KN’(W/L) (VOV) (more) AV= - VDD RD KN’(W/L) / [1+ RD KN’(W/L) VOV]2 (less) Bits, pilani
  51. 51. Gain in saturation Av= - gm RD (effect of ro not taken into account) AV= - RD KN’(W/L) (VOV) gm = KN’ (W/L) (VOV)---trans-conductance = 2 ID/ Vov =√ [2 KN’(W/L) ID] Bits, pilani
  52. 52. gm Bits, pilani
  53. 53. SMALL SIGNAL PARAMETERS gm --transconductance ro—drain resistance gmb---body transconductance iD= f (vDS, vGS. VSB) Bits, pilani
  54. 54. iD= f (vDS, vGS, VSB)—Taylor approx. ∂iD ∂iD ∂iD∂iD |Q ≈ ΛvGS + ΛvDS + ΛvSB ∂vGS ∂vDS ∂vSB ∂iD ∂iD ∂iD I D + id ≈ I D + vgs + vds + vsb ∂vGS ∂vDS ∂vSB ∂iD ∂iD ∂iDid = [ vgs + vds + vsb ]Q ∂vGS ∂vDS ∂vSBid = g m vgs + g d vds + g mb vsb
  55. 55. Bits, pilani
  56. 56. Plot the graphs---do yourself gm vs. w/L for Id constant gm vs. w/L for Vov. Constant gm vs. Id for Vov. Constant Bits, pilani
  57. 57. With λCorrection in book is required Bits, pilani
  58. 58. Bits, pilani
  59. 59. Bits, pilani
  60. 60. Model parameters Bits, pilani
  61. 61. Complete AC model Bits, pilani
  62. 62. NMOS Bits, pilani
  63. 63. PMOS Bits, pilani
  64. 64. Converting to T modelFigure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but canbe added between D and S in the T model of (d). Bits, pilani
  65. 65. How to draw AC model of amplifier? For amplification, only AC behaviour needs to be considered Replace MOS by its model in the circuit Bits, pilani
  66. 66. 2 Sources in ckt.—1 ac, 1dc Bits, pilani
  67. 67. Bits, pilani
  68. 68. Using superposition Source Vdd/or Source Ibias voutDC = Vdd − I bias × RD  ro  voutDC = Vdd  RD + ro  Source i voutAC = −i × [ro || RD ] Bits, pilani
  69. 69. Considering only AC voutAC = −i × [ro || RD ] Bits, pilani
  70. 70. Bits, pilani

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