Silicides review

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Review of Silicides in VLSI with focus on Ni for Ni-Cu metalllization for solar cells.

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Silicides review

  1. 1. Mehul C. Raval – Doctorate Student, NCPRE
  2. 2. Outline Importance of silicides in VLSI Properties of important silicides Advantages of NiSi Phase diagram of Ni silicide Properties of different Ni silicides Annealing conditions for NiSi formation Ni silicide in solar cells Fabrication of Ni seed layer for solar cell metallization 2
  3. 3. Silicides in VLSI Almost all metals in periodic table react with Si to silicides with general formula ‘MxSiy’. Silicides have ‘metal-like’ properties. Silicides Refractory Near-Noble Rare Earth Metal Metal Metal Silicides Silicides Silcides TiSi2, WSi PtSi, CoSi ErSi2 2 3
  4. 4.  Early use of silicides to make contact for Schottky diodes*.  Interconnects made from WSi2 silicides had reduced line resistance**.  Gate length, junction depth and contact surface are important parameters for CMOS transistors.  Miniaturization below 0.5 µm would require technological changes in the transistor itself.  Self-Aligned silicides (SALICIDE) play an important role for contact formation.* - Metal Silicides in CMOS Technology: Past, Present, and Future Trends, Shi-Li Zhang & MikaelÖstling, 2003.** - Simply irresistible silicides,Karen Maex, Physics World November 1995. 4
  5. 5. Figure. SALICIDE Formation Process Flow** - Metal Silicides in CMOS Technology: Past, Present, and Future Trends, Shi-Li Zhang & MikaelÖstling, 2003. 5
  6. 6. Figure. Cross-section of a MOSFET** - Simply irresistible silicides,Karen Maex, Physics World November 1995. 6
  7. 7. Properties of important silicides * Silicide Formation ρ(µΩcm) ФB(eV) Dominating Si Temp(°C) Diffusion consumed/nm species of metal(nm) C49 TiSi2 350-700 60-80 - Si - C54TiSi2 750 15-20 0.6 Si 2.3 Co2Si 350 110 - Co 0.9 CoSi 375 147 0.68 Si 1.8 CoSi2 600-700 15-20 0.64 Co 3.6 NiSi 350-750 10.5-15 0.65 Ni 1.8 NiSi2 750-1000 34 0.66 Ni 3.6 Pd2Si 200-500 25-35 - - 0.7• Limitations of CoSi2:** • Limitations of TiSi2:*** - Rise in resistance for narrow lines. - As dimensions reduce, temp for C49 to - Reduction in available Si for reaction. C54 change ↑. - Introduction of Si-Ge substrates. - Max temp to prevent agglomeration ↓. - Junction leakage due to ↑ Si consumption. * - Metal Silicides in CMOS Technology: Past, Present, and Future Trends, Shi-Li Zhang & Mikael Östling, 2003. ** - Chapter 5, Silicide Technology for IC, Lih J. Chen,2004. 7
  8. 8. Advantages of NiSi *  Reduced Thermal Budget - As NiSi forms at low temperatures.  Lower Resistivity.  Reduced Si consumption – Due to reduced resistivity and decreased Si consumption.  Silicide formation controlled by Ni diffusion – Important to avoid bridging at edges of gates.* - Chapter 5, Silicide Technology for Integrated Circuits, Lih J. Chen,2004. 8
  9. 9. Phase Diagram of Ni Silicides Melting Isothermal Line Melting Tie Line point of point of Liquidus Line ‘B’ ‘A’ LiquidRemainsa solid Temperaturesolution α + Liquid β + Liquidhere X α Eutectic Eutectic Line Point β (α + β) - Solid Cα % CO % CL % 100% 100% A Solid Solubility Line B Figure. Illustrative Phase Diagram * * - http://www.southampton.ac.uk/~pasr1/index.htm 9
  10. 10. Ni3Si Ni3Si2 Ni2Si NiSi Ni31Si12/Ni5Si2 NiSi2Figure. Ni-Si Phase Diagram 10
  11. 11. Properties of Ni silcides Figure. Ni silcide phase formation** - Silicides and ohmic contacts, J.P. Gambino & E.G. Colgan, Materials Chemistry and Physics 11
  12. 12. Table. Properties of different Ni silicides* Phase Density(g Silicide t / Si ρ(µΩcm) Melting m/cm^3 Ni t consume Point(°C) d t / Ni t Ni 8.91 1 0 7-10 1455 Ni3Si 7.87 1.31 0.61 80-90 1035/1170 Ni2Si 7.51 1.47 0.91 24-30 1255/1306 Ni3Si2 6.71 1.75 1.22 60-70 830/845 NiSi 5.97 2.2 1.83 10.5-18 992 NiSi2 4.8 3.61 3.66 34-50 981/993 Si 2.33 - - Dopant 1414 dependent • For 15 nm Si on poly-Si, Ni31Si12/ strained Ni2Si was observed for annealing at 200°C and Ni3Si2 observed between 300°C-400°C.** - Chapter 5, Silicide Technology for Integrated Circuits, Lih J. Chen,2004. 12
  13. 13. Annealing Conditions for NiSi Ni Substrate Doping(cm^ Anneal Conditions Silicide Additional RefThickness(nm) -3) °C s Ambient Phase Information 20 350nm poly-Si on P- 8 x 10^20 400 30 N2 NiSi Silicide thickness = 1 p-type (100) 40nm 25 Si(100) - 500 30 Vacuum NiSi Silicide thickness = 2 50nm 12 Si(001) - 400 600 - NiSi, epi Ni2Si is not 3 NiSi2 observed 20 N-type Si(100) 1.6- - 350 1800 Vacuum NiSi Silcide 35nm to 4 2.1 Ω-cm 40nm thick 10 Si(100) - 300 30 He Ni2Si 5 10 Si(100) As & B 300- 30 He NiSi Excessive 5 doped 340 silicidation at edges 10 Si(100) As & B 364 Spike He NiSi 5 doped 10 Si(100) As 270 30 He Ni2Si -> RTP2 – 450°C, 30s. 5 NiSi No excessive silicidation 125 n-type Si(100) As- 2 x 550 30 N2 NiSi Ramp Up – 80°C/s, 6 10^20 cm^-3 Down- 25°C/s. NiSi initiates from 400C 12 -do- -do- 450 30 N2 NiSi -do- 6 50 -do- -do- & P- 500 30 N2 NiSi -do-, Also for p- 6 10^15 cm^-3 type B doped. 13
  14. 14. Table. Contact Resistivity Data for NiSi Ni Substrate Doping Anneal Conditions Contact Comments RefThickness(nm) (cm^- (°C) s Ambient Resistivity,ρ 3) c(Ω-sq.cm) 20 N-type n-type 350 1800 Vacuum 4.2 x 10^-8 4 Si(100) :2x 10^20 cm^-3 20 P-type p-type: 350 1800 Vacuum 7 X 10^-8 4 Si(100) 1x 10^20 cm^-3. 20-40 P+ Poly- B: 2 x 600 30 - 3 x 10^-9 Contact Area = 1 7 Si 10 ^ 20 µ sq.m Assumption – L < 0.5 LT 20-40 N+ Poly As: 2 x 600 30 - 4 x 10^-9 -do- 7 Si 10^20 10 N-type 10 X 300 43 < 10^-8 2-step anneal 8 10^19 470 43 cm^-3 14
  15. 15. Figure. Variation of ρc for NiSi with doping concentration [8]Table. Variation of Annealing Conditions for varying Ni thickness Ni Thickness(nm) Anneal Anneal Time(s) Temperature(°C) 10-12 300-350 30 to 600 20-50 400-500 30 to 1800 > 100 550 30 15
  16. 16. Ni silicide in solar cells Table. Ni seed layer conditions with solar cell metallization properties Ni Bath Anneal FF(%) Rs(Ω- Rsh(Ω- ρc(Ω- Ref Thickness( Conditions sq.cm) sq.cm) sq.cm) nm) (°C,s) 30-40 EN,pH: 9 - 78.2 0.36 15000 - 9 to 11, T < 60 s, 145 ± 20 EN,pH: 8 350°C- - - - 6m 10 to 10, T- 750°C 75°C- 90°C - EN 400°C 79.8 0.64 - 3.5 x 11 10^-5 1000 LIP 300°C 75.6 0.9 - - 12 6000-8000 EN, pH- 8 410°C, 60s 72.4 0.32 9m 13 to 10, T = 95°C 16
  17. 17. Fabrication of Ni seed layer for solar cellsa) b) Figure. Electroless plated Ni from alkaline bath a) 45 and b) 30 s deposition • For 100nm seed layer, annealing to be done at 550°C for 30 s. • For 50nm seed layer, annealing to be done at 500°C for 30s. • TLM samples will be prepared for ρc calculation, target < 2mΩ sq.cm. • Silicide phase to be determined via XPS. 17
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  19. 19. References:1) Analysis of Resistance Behavior in Ti-and Ni-Salicided Polysilicon Films, TatsuyaOhguro, et.al, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 12,1994.2) In situ real-time studies of nickel silicide phase formation, M. Tinani, et.al, J. Vac. Sci.Technol. B 19 „ 2 … March – April 2001. ,3) In situ transmission electron microscopy study of Ni silicide phases formed on „ 001 …Siactive lines, V. Teodorescu, et.al, J. Appl. Phys., Vol. 90, No. 1, 1 July 2001.4) Electrical Properties and Solid-Phase Reactions in Ni/Si(100) Contacts, YoshinoriTSUCHIYA, et. al, Jpn. J. Appl. Phys. Vol. 41 (2002) pp. 2450–2454.5) Low temperature spike anneal for Ni-silicide formation, A. Lauwers, et. al, MicroelectronicEngineering 76 (2004) , 303–310.6) Material aspects of nickel silicide for ULSI applications, D.-X. Xu, et. al, Thin Solid Films 326(1998) 143–150.7) A Self- Aligned Emitter Base Nisi Electrode Technology for Advanced High-speed BipolarLSIs, T. linuma, et. al, IEEE 1992 Bipolar Circuits and Technology Meeting 4.4.8) Systematic TLM Measurements of NiSi and PtSi Specific Contact Resistance to n- and p-Type Si in a Broad Doping Range, N. Stavitski, et. al , IEEE ELECTRON DEVICE LETTERS,VOL. 29, NO. 4, APRIL 2008.9) Alemàn M., N. Bay, D. Barucha, A. Knorz, D. Biro, R. Preu, S.W. Glunz, Advances inElectroless Nickel Plating for the metallization of silicon solar cells using different structuringtechniques for the ARC, Proceedings of 24th PV Solar Energy Conference and Exhibition,Hamburg, September 2009. 19
  20. 20. 10) Nguyen A., M.V. Rane-Fondacaro, H. Efstathiadis, P. Haldar, L. Michealson, C. Wang,K. Munoz, T. Tyson, A. Gallegos, Formation of a Low Ohmic Contact Nickel Silicide Layer onTextured Silicon Wafers Using Electroless Nickel Plating, Conference Proceedings of 25 thEUPVSEC, Valencia, September 2010.11) Jinmo Kang, JaeSung You, ChoonSik Kang, James Jungho Pak, Donghwan Kim,Investigation of Cu metallization for Si solar cells, Solar Energy Materials & Solar Cells 2002;74: 91–96.12) Tous L., R. Russell, J. Das, R. Labie, M. Ngamo, J. Horzel, H. Philipsen,J. Sniekers, K.Vandermissen, L. van den Brekel, T. Janssens, M. Aleman, D.H. van Dorp, J. Poortmans, R.Mertens, Large area copper plated silicon solar cell exceeding 19.5% efficiency, EnergyProcedia, 2012.13) A novel two step metallization of Ni/Cu for low concentrator c-Si solar cells, Vikrant A.Chaudhari, Chetan S. Solanki, Solar Energy Materials & Solar Cells 94 (2010) 2094–2101. 20

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