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Computer Architecture: A quantitative approach - Cap4 - Section 2

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Computer Architecture: A quantitative approach - Cap4 - Section 2

  1. 1. Multiprocessors and Thread-Level Parallelism Symmetric Shared-Memory Architectures “ The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor.” Hennessy and Patterson
  2. 2. Hardware Designers Motivation <ul><li>The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor. </li></ul>
  3. 3. Multiprocessors Cache Coherence
  4. 4. Basic Schemes for Enforcing Coherence <ul><li>Directory Based </li></ul><ul><li>Snooping </li></ul>
  5. 5. The Snooping Protocols <ul><li>Write Invalidate Protocol </li></ul><ul><li>Write Broadcast Protocol </li></ul>
  6. 6. Write Invalidate Protocol
  7. 7. An Example Protocol
  8. 8. An Example Protocol
  9. 9. An Example Protocol
  10. 10. SSM and Snooping Limitations <ul><li>As the number of processors in a multiprocessor grows, or as the memory demands of each processor grow, any centralized resource in the system can become a bottleneck. </li></ul>
  11. 11. SSM and Snooping Limitations
  12. 12. Implementing Snoopy Cache Coherence <ul><li>Race Situation: Have a winner is more important than who wins. </li></ul><ul><li>Broadcast for all misses and some basic properties of the interconnection network. </li></ul><ul><li>Ability to restart the miss handling of the loser in a race. </li></ul>
  13. 13. Thank you! Author: Prof. Sergio Takeo, Marcelo Arbore. Bibliography: Patterson, D. A.; Hennessy, J. L. Computer Architecture: A quantitative Approach, 4 th Ed. Morgan Kaufmann Publishers. “ The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor.” Hennessy and Patterson

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