Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.

Assembly10 interrupts


Published on

Published in: Design
  • Be the first to comment

  • Be the first to like this

Assembly10 interrupts

  1. 1. AVR Interrupts Assembly Language Programming University of Akron Dr. Tim Margush
  2. 2. What is an Interrupt• A condition or event that interrupts the normal flow of control in a program• Interrupt hardware inserts a function call between instructions to service the interrupt condition• When the interrupt handler is finished, the normal program resumes execution11/11/12 Dr. Tim Margush - Assembly 2 Language Programming
  3. 3. Interrupt Sources• Interrupts are generally classified as › internal or external › software or hardware• An external interrupt is triggered by a device originating off-chip• An internal interrupt is triggered by an on- chip component11/11/12 Dr. Tim Margush - Assembly 3 Language Programming
  4. 4. Interrupt Sources• Hardware interrupts occur due to a change in state of some hardware• Software interrupts are triggered by the execution of a machine instruction11/11/12 Dr. Tim Margush - Assembly 4 Language Programming
  5. 5. Interrupt Handler• An interrupt handler (or interrupt service routine) is a function ending with the special return from interrupt instruction (RETI)• Interrupt handlers are not explicitly called; their address is placed into the processors program counter by the interrupt hardware11/11/12 Dr. Tim Margush - Assembly 5 Language Programming
  6. 6. AVR Interrupt System• The ATMega16 can respond to 21 different interrupts• Interrupts are numbered by priority from 1 to 21 › The reset interrupt is interrupt number 1• Each interrupt invokes a handler at a specific address in program memory › The reset handler is located at address $000011/11/12 Dr. Tim Margush - Assembly 6 Language Programming
  7. 7. Interrupt Vectors• The interrupt handler for interrupt k is located at address 2(k-1) in program memory › Address $0000 is the reset interrupt › Address $0002 is external interrupt 0 › Address $0004 is external interrupt 1• Because there is room for only one or two instructions, each interrupt handler begins with a jump to another location in program memory where the rest of the code is found › jmp handler is a 32-bit instruction, hence each handler is afforded 2 words of space in this low memory area11/11/12 Dr. Tim Margush - Assembly 7 Language Programming
  8. 8. Interrupt Vector Table• The 21 instructions at address $0000 through $0029 comprise the interrupt vector table• These jump instructions vector the processor to the actual service routine code › A long JMP is used so the code can be at any address in program memory• An interrupt handler that does nothing could simply have an RETI instruction in the table11/11/12 Dr. Tim Margush - Assembly 8 Language Programming
  9. 9. Use jmp, not rjmp Typical IVT.cseg • If you omit some vectors,.org 0 you must use .org to locate the vectorsjmp reset appropriatelyjmp external_int_0 › The interrupt vectorjmp external_int_1 addresses are defined in the include UDREaddr • The $2A address is justjmp transmitByte beyond the vector table …etc… › A lower address can $2A used if the corresponding interrupts are never enabledreset:11/11/12 Dr. Tim Margush - Assembly 9 Language Programming
  10. 10. Interrupt Enabling• Each potential interrupt source can be individually enabled or disabled › The reset interrupt is the one exception; it cannot be disabled• The global interrupt flag must be set (enabled) in SREG, for interrupts to occur › Again, the reset interrupt will occur regardless11/11/12 Dr. Tim Margush - Assembly 10 Language Programming
  11. 11. Interrupt Actions• If › global interrupts are enabled › AND a specific interrupt is enabled › AND the interrupt condition is present• Then the interrupt will occur• What actually happens? › At the completion of the current instruction, • the current PC is pushed on the stack • global interrupts are disabled • the proper interrupt vector address is placed in PC11/11/12 Dr. Tim Margush - Assembly 11 Language Programming
  12. 12. Return From Interrupt• The RETI instruction will › pop the address from the top of the stack into the PC › set the global interrupt flag, re-enabling interrupts• This causes the next instruction of the previously interrupted program to be executed › At least one instruction will be executed before another interrupt can occur11/11/12 Dr. Tim Margush - Assembly 12 Language Programming
  13. 13. Stack• Since interrupts require stack access, it is essential that the reset routine initialize the stack before enabling interrupts• Interrupt service routines should use the stack for temporary storage so register values can be preserved11/11/12 Dr. Tim Margush - Assembly 13 Language Programming
  14. 14. Status Register• Interrupt routines MUST LEAVE the status register unchanged typical_interrupt_handler: push r0 in r0, SREG … out SREG, r0 pop r0 reti11/11/12 Dr. Tim Margush - Assembly 14 Language Programming
  15. 15. Interrupt Variations• AVR Interrupts fall into two classes › Event based interrupts • Triggered by some event; must be cleared by taking some program action › Condition based interrupts • Asserted while some condition is true; cleared automatically when the condition becomes false11/11/12 Dr. Tim Margush - Assembly 15 Language Programming
  16. 16. Event-based Interrupts• Even if interrupts are disabled, the corresponding interrupt flag may be set by the associated event• Once set, the flag remains set, and will trigger an interrupt as soon as interrupts are enabled › This type of interrupt flag is cleared • by manually by writing a 1 to it • automatically when the interrupt occurs11/11/12 Dr. Tim Margush - Assembly 16 Language Programming
  17. 17. Condition-based Interrupts• Even if interrupts are disabled, the interrupt flag will be set when the associated condition is true• If the condition becomes false before interrupts are enabled, the flag will clear and the interrupt will be missed › These flags are cleared when the condition becomes false › Some program action may be required to accomplish this11/11/12 Dr. Tim Margush - Assembly 17 Language Programming
  18. 18. Sample Interrupts• Event-based • Condition-based › Edge-triggered › Level triggered external interrupts external interrupts › Timer/counter › USART Data Ready, overflows and output Receive Complete compare › EEPROM Ready11/11/12 Dr. Tim Margush - Assembly 18 Language Programming
  19. 19. External Interrupts• The ATMega16 responds to 4 different external int2 interrupts – signals applied to specific pins• RESET (pin 9) reset• INT0 (pin 16 – also PD2)• INT1 (pin 17 – also PD3) int0 int1• INT2 (pin 3 – also PB3)11/11/12 Dr. Tim Margush - Assembly 19 Language Programming
  20. 20. External Interrupt Configuration• Condition-based › while level is low• Event-based triggers › level has changed (toggle) › falling (negative) edge (1 to 0 transition) › rising (positive) edge (0 to 1 transition)11/11/12 Dr. Tim Margush - Assembly 20 Language Programming
  21. 21. MCUCR• MCU Control Register MCUCR – MCU Control Register 7 6 5 4 3 2 1 0 ISC11 ISC10 ISC01 ISC00• ISC – Interrupt Sense Control bits › 00 – low level INT0 › 01 – level change INT1 › 10 – negative edge › 11 – positive edge11/11/12 Dr. Tim Margush - Assembly 21 Language Programming
  22. 22. Level Triggers• The processor samples the levels on pins INT0 and INT1 each clock cycle• Very short pulses (less than one cycle) may go undetected (no change or edge is seen) › The low level interrupt will occur only if the pin is low at the end of the current instruction11/11/12 Dr. Tim Margush - Assembly 22 Language Programming
  23. 23. MCUCSR• MCU Control and Status Register MCUCSR – MCU Control and Status Register 7 6 5 4 3 2 1 0 ISC2 INT2• ISC – Interrupt Sense Control bits › 0 – negative edge › 1 – positive edge • This interrupt does not offer the other triggers11/11/12 Dr. Tim Margush - Assembly 23 Language Programming
  24. 24. GICR• General Interrupt Control Register GICR – General Interrupt Control Register 7 6 5 4 3 2 1 0 INT1 INT0 INT2• Each external interrupt is enabled or disabled here ;Enable int1, disable int0 in R16, GICR sbr R16, 1<<INT1 cbr R16, 1<<INT0 out GICR, R1611/11/12 Dr. Tim Margush - Assembly 24 Language Programming
  25. 25. GIFR• General Interrupt Flag Register GICR – General Interrupt Flag Register 7 6 5 4 3 2 1 0 INTF1 INTF0 INTF2• A set (1) flag indicates a pending interrupt › These flags are used only when edge or change triggers are in use • In level configuration, the flag is always 0 › The specified change event will set the flag; it must be reset manually or by servicing the interrupt11/11/12 Dr. Tim Margush - Assembly 25 Language Programming
  26. 26. Software Interrupt• If the external interrupt pins are configured as outputs, a program may assert 0 or 1 values on the interrupt pins › This action can trigger interrupts according to the external interrupt settings• Since a program instruction causes the interrupt, this is called a software interrupt11/11/12 Dr. Tim Margush - Assembly 26 Language Programming
  27. 27. Timer/Counters• The ATMega16 has three timer/counter devices on-chip• Each timer/counter has a count register• A clock signal can increment or decrement the counter• Interrupts can be triggered by counter events11/11/12 Dr. Tim Margush - Assembly 27 Language Programming
  28. 28. 8-Bit Timer/Counter External Clock Signal11/11/12 Dr. Tim Margush - Assembly 28 Language Programming
  29. 29. Timer Events• Overflow › In normal operation, overflow occurs when the count value passes $FF and becomes $00• Compare Match › Occurs when the count value equals the contents of the output compare register11/11/12 Dr. Tim Margush - Assembly 29 Language Programming
  30. 30. Output Compare Unit External Output11/11/12 Dr. Tim Margush - Assembly 30 Language Programming
  31. 31. Status via Polling• Timer status can be determined through polling › Read the Timer Interrupt Flag Register and check for set bits › The overflow and compare match events set the corresponding bits in TIFR • TOVn and OCFn (n=0, 1, or 2) › Timer 1 has two output compare registers: 1A and 1B • Clear the bits by writing a 111/11/12 Dr. Tim Margush - Assembly 31 Language Programming
  32. 32. Status via Interrupt• Enable the appropriate interrupts in the Timer Interrupt Mask Register• Each event has a corresponding interrupt enable bit in TIMSK › TOIEn and OCIEn (n = 0, 1, 2) • Again, timer 1 has OCIE1A and OCIE1B › The interrupt vectors are located at OVFnaddr and OCnaddr11/11/12 Dr. Tim Margush - Assembly 32 Language Programming
  33. 33. Timer Interrupts• The corresponding interrupt flag is cleared automatically when the interrupt is processed › It may be manually cleared by writing a 1 to the flag bit11/11/12 Dr. Tim Margush - Assembly 33 Language Programming
  34. 34. Automatic Timer Actions• The timers (1 and 2 only) can be configured to automatically clear, set, or toggle related output bits when a compare match occurs › This requires no processing time and no interrupt handler – it is a hardware feature › The related OCnx pin must be set as an output; normal port functionality is suspended for these bits • OC0 (PB3) OC2 (PD7) • OC1A (PD5) OC1B (PD4)11/11/12 Dr. Tim Margush - Assembly 34 Language Programming
  35. 35. Timer Clock Sources• The timer/counters can use the system clock, or an external clock signal• The system clock can be divided (prescaled) to signal the timers less frequently › Prescaling by 8, 64, 256, 1024 is provided • Timer2 has more choices allowing prescaling of an external clock signal as well as the internal clock11/11/12 Dr. Tim Margush - Assembly 35 Language Programming
  36. 36. ATMega16 Prescaler Unit External Clock Signals11/11/12 Dr. Tim Margush - Assembly 36 Language Programming
  37. 37. Clock SelectionTCCR0 and TCCR1B – Timer/Counter TCCR2 – Timer/Counter Control Register Control Register (counters 0 and 1) (counter 2)CSn2, CSn1, CSn0 (Bits 2:0) are the clock CS22, CS21, CS20 (Bits 2:0) are the clock select bits (n = 0 or 1) select bits000 = Clock disabled; timer is stopped 000 = Clock disabled; timer is stopped001 = I/O clock 001 = T2 clock source010 = /8 prescale 010 = /8 prescale011 = /64 prescale 011 = /32 prescale100 = /256 prescale 100 = /64 prescale101 = /1024 prescale 101 = /128 prescale110 = External clock on pin Tn, falling edge 110 = /256 prescale trigger 111 = /1024 prescale111 = External clock on pin Tn, rising edge ASSR (Asynchronous Status Register), bit trigger AS2 sets the clock source to the internal clock (0) or external pin TOSC1)11/11/12 Dr. Tim Margush - Assembly 37 Language Programming
  38. 38. Timer Modes• Normal Mode › Counter counts up, TOV occurs when it reaches 0• Clear Timer on Compare Mode (CTC) › Counter counts up to match the Output Compare Register; On the next count, it resets to 0 and the OC Flag is set• Others…11/11/12 Dr. Tim Margush - Assembly 38 Language Programming
  39. 39. Timer Control (Timer0) TCCRO Timer/Counter 0 Control Register7 6 5 4 3 2 1 0FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00• WGM01:0 Waveform • Compare Match Output Generation Mode Mode › 00 Normal › 00 Nothing › 01 PWM › 01 Toggle › 10 CTC › 10 Clear › 11 Fast PWM › 11 Set• Clock Select • Behavior is slightly › covered previously different in each WG mode11/11/12 Dr. Tim Margush - Assembly 39 Language Programming
  40. 40. Timer Count Value• The timers current value may be read or written at any time › in R16, TCNT0 out TCNT0, R17 • The output compare function is disabled for one cycle after a write • Modification while the timer is running may also cause a missed compare11/11/12 Dr. Tim Margush - Assembly 40 Language Programming
  41. 41. Interrupts• TIMSK - Timer/Counter Interrupt Mask TIMSK Timer/Counter Interrupt Mask Register 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 › Output Compare Interrupt Enable Timer 0 › Timer Overflow Interrupt Enable masks › Input Capture Interrupt Enable11/11/12 Dr. Tim Margush - Assembly 41 Language Programming
  42. 42. Flags• TIFR - Timer/Counter Interrupt Flags TIFR Timer/Counter Interrupt Flag Register 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 › Output Compare Flag Timer 0 › Timer Overflow Flag flags › Input Capture Flag11/11/12 Dr. Tim Margush - Assembly 42 Language Programming
  43. 43. Timer/Counter 1• This is a 16 bit timer › Access to its 16-bit registers requires a special technique• Always read the low byte first › This buffers the high byte for a subsequent read• Always write the high byte first › Writing the low byte causes the buffered byte and the low byte to be stored into the internal register There is only one single byte buffer shared by all of the 16-bit registers in timer 111/11/12 Dr. Tim Margush - Assembly 43 Language Programming
  44. 44. Timer/Counter 1 Control Register• TCCR1A TCCR1A Timer/Counter 1 Control Register A 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10• TCCR1B TCCR1B Timer/Counter 1 Control Register B 7 6 5 4 3 2 1 0 ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS1011/11/12 Dr. Tim Margush - Assembly 44 Language Programming
  45. 45. Timer 1 Data Registers• TCNT1H:TCNT1L › Timer 1 Count• OCR1AH:OCR1AL › Output Compare value – channel A• OCR1BH:OCR1BL › Output Compare value – channel B• ICR1H:ICR1L › Input Capture11/11/12 Dr. Tim Margush - Assembly 45 Language Programming
  46. 46. Switch Bounce Elimination• Pressing/releasing a switch may cause many 0-1 transitions › The bounce effect is usually over within 10 milliseconds• To eliminate the bounce effect, use a timer interrupt to read the switch states only at 10 millisecond intervals › The switch state is stored in a global location to be available to any other part of the program11/11/12 Dr. Tim Margush - Assembly 46 Language Programming
  47. 47. Debounce Interrupt.dseg • Global variable holds the mostswitchstate: .byte 1 recently accessed switch data from the input port › A bit value of 1 will mean.cseg switch is pressed, 0 means it isswitchread: not push r16 • The interrupt is called every 10 in R16, PIND milliseconds com r16 • It simply reads the state of the switches, complements it, and sts switchstate, r16 stores it for global access pop r16 reti11/11/12 Dr. Tim Margush - Assembly 47 Language Programming
  48. 48. Timer Setup• Use timer output compare • The maximum resolutions interrupt (256 counts to overflow)• Timer will use the using these settings are prescaler and the internal › /8: 0.512 millisec 4 MHz clock source › /64: 4.096 millisec › Time between counts › /256: 16.384 millisec • 4Mhz/8 = 2 microsec › /1024: 65.536 millisec • 4MHz/64 = 16 microsec • Using the /256 prescale, • 4MHz/256 = 64 microsec we need 156.25 counts so • 4MHz/1024 = 256 microsec we should load the output compare register with 15611/11/12 Dr. Tim Margush - Assembly 48 Language Programming
  49. 49. Timer Initialization .equ TOP = 256 • A constant is used to ldi temp, BOTTOM specify the counters TOP value out OCR0, temp • The Timer Output ldi temp, 1<<OCIE0 Compare Match interrupt out TIMSK, temp is enabled ldi temp,(1<<WGM01)• The clock source is set to | (0<<WGM00) use the divide by 256 | (4<<CS00) prescaler out TCCR0, temp • Global interrupts are sei enabled11/11/12 Dr. Tim Margush - Assembly 49 Language Programming
  50. 50. Interrupt Task• On each interrupt, the timer automatically resets to 0 and the interrupt flag is reset › the next interrupt will occur in 10 milliseconds• We must preserve the status register and registers used• The interrupt will alter one memory location › .dseg › ;debounced PIND values › switchstate: .byte 111/11/12 Dr. Tim Margush - Assembly 50 Language Programming
  51. 51. Interrupt Routineswitchread: • The counter has just push temp matched the output in temp, SREG compare register and has reset to 0 push temp • Remember to save…switch processing details registers and status pop temp flags as required out SREG, temp pop temp reti11/11/12 Dr. Tim Margush - Assembly 51 Language Programming
  52. 52. Application lds temp, switchstate • The application accesses ;1 in bit n means the switch states from ; switch n is down tst temp SRAM breq no_press › This byte is updated ever 10 milliseconds by the…process the switches timer interruptno_press: .dseg… switchstate: .byte 111/11/12 Dr. Tim Margush - Assembly 52 Language Programming
  53. 53. USART Interrupts• Interrupt driven receive and transmit routines free the application from polling the status of the USART › Bytes to be transmitted are queued by the application; dequeued and transmitted by the UDRE interrupt › Received bytes are enqueued by the RXC interrupt; dequeued by the application11/11/12 Dr. Tim Margush - Assembly 53 Language Programming
  54. 54. Cautions• The queues are implemented in SRAM• They are shared by application and interrupt › It is likely that there will be critical sections where changes should not be interrupted!;A queue storage area.dsegqueuecontents .byte MAX_Q_SIZEfront .byte 1back .byte 1size .byte 111/11/12 Dr. Tim Margush - Assembly 54 Language Programming
  55. 55. USART Configuration• In addition to the normal sbi UCSRB, RXCIE configuration, interrupt vectors must be setup and • The UDRE and TXC the appropriate interrupts interrupts are disabled by enabled default › The transmit interrupt is only enabled when a byte is • Other bits of this register to be sent, so this is initially must not be changed; they disabled hold important USART › The receive interrupt must configuration information be on initially; we are always waiting for an • The transmit complete incoming byte interrupt is not needed11/11/12 Dr. Tim Margush - Assembly 55 Language Programming
  56. 56. USART Interrupt UDREaddr • The interrupt vectorsjmp transmit_byte must be located at URXCaddr correct addresses injmp byte_received the UTXCaddr › The include file hasreti already defined labels for the addresses › The TXC interrupt is shown for completeness; it is not used in this example11/11/12 Dr. Tim Margush - Assembly 56 Language Programming
  57. 57. Byte Received• This interrupt occurs when byte_received: the USART receives a in R16, UDR byte and makes it rcall r_enqueue available in its internal receive queue reti• To prevent overflow of • If another byte arrives this 2 byte queue, the during this routine, it will interrupt immediately be caught on the next removes it and places it in interrupt the larger RAM-based › Receive errors? queue › Queue full? › Registers saved?11/11/12 Dr. Tim Margush - Assembly 57 Language Programming
  58. 58. Transmit Byte• This occurs when UDRE transmit_byte: is ready to accept a byte rcall t_dequeue• If the transmit queue is brcc t_sendit empty, disable the cbi UCSRB, UDRIE interrupt• Otherwise place the byte rjmp t_exit into UDR t_sendit:• The t_dequeue function out UDR, R16 returns a byte in R16 t_exit: › If no byte is available, it reti returns with the carry flag set • Remember to save registers and status!11/11/12 Dr. Tim Margush - Assembly 58 Language Programming
  59. 59. UDRIE?• The UDRE Interrupt is enabled by the t_enqueue function › When a byte is placed into the queue, there is data to be transmitted › This is the logical place to enable the UDRE interrupt (if not already enabled) • Enable it after the item is enqueued, or it might occur immediately and find nothing to transmit!11/11/12 Dr. Tim Margush - Assembly 59 Language Programming
  60. 60. EEPROM Writes• Writing to EEPROM takes quite a bit of time – An interrupt can be used to efficiently store multiple bytes• The EEPROM Ready interrupt will fire when a store operation can be initiated › This eliminates polling the EEWE bit• This approach assumes a queue of bytes and addresses › When something is enqueued, the interrupt is enabled to begin the storage operations11/11/12 Dr. Tim Margush - Assembly 60 Language Programming
  61. 61. EEPROM Ready• The interrupt vector .org ERDYaddr must be setup properly jmp eestore• This interrupt must be initially disabled, as › The Ready Interrupt the ERDY condition will initially be (EEWE=0) will disabled, so no normally be true additional causing a continuing configuration is needed interrupt11/11/12 Dr. Tim Margush - Assembly 61 Language Programming
  62. 62. EESTORE• If the queue is empty, the eestore: interrupt is disabled rcall e_dequeue• Otherwise, the byte and brcc ee_store address which are returned cbi EECR, EERIE in R16-R18 are placed in rjmp ee_exit the EEPROM registers ee_store: and the write operation is out EEARH, R18 initiated out EEARL, R17 › When complete, the out EEDR, R16 interrupt will occur again to sbi EECR, EEMWE allow the next byte to be sbi EECR, EEWE stored › In none are in the queue, ee_exit: the interrupt will be reti disabled11/11/12 Dr. Tim Margush - Assembly 62 Language Programming
  63. 63. Queue Manipulation• Interrupt routines can • What if we increase the enqueue and dequeue queue size during an without fear of enqueue, but are interruption interrupted before the new• Applications must ensure item is stored into that critical sections are memory? not interrupted • What happens if we are in the process of a dequeue, and an interrupt routine enqueues a new item?11/11/12 Dr. Tim Margush - Assembly 63 Language Programming