Computer Archeticture

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  • Design state of art organization in 1990
  • Let me summarize what I have said so far. The most important thing I want you to remember is that: all computers, no matter how complicated or expensive, can be divided into five components: (1) The datapath and (2) control that make up the processor. (3) The memory system that supplies data to the processor. And last but not least, the (4) input and (5) output devices that get data in and out of the computer. One thing about memory is that Not all “memory” are created equally. Some memory are faster but more expensive and we place them closer to the processor and call them “cache.” The main memory can be slower than the cache so we usually use less expensive parts so we can have more of them. Finally as you can see from the last few slides, the input and output devices usually has the messiest organization. There are several reasons for it: (1) First of all, I/O devices can have a wide range of speed. (2) Then I/O devices also have a wide range of requirements. (s) Finally to make matters worse, historically I/O has attracted the least amount of research interest. But hopefully this is changing. In this class, you will learn about all these five components and we will try to make this as enjoyable as possible. So have fun.
  • Computer Archeticture

    1. 1. Computer Architecture
    2. 2. Important Policies <ul><li>No make-up quizzes and all exams are close-book unless specified otherwise. </li></ul><ul><li>Make-up exam is given only when special extenuating situation happens and under the discretion of the instructor </li></ul><ul><li>You are required to attend every class. Exception is given only if you notify the instructor with a legitimate reason in advance. </li></ul>
    3. 3. Other Important Policies <ul><li>Don’t arrive late to the class. </li></ul><ul><li>All handouts are available on the instructor's website. </li></ul><ul><li>You are required to check the instructor's website periodically (at least once a day before the class time) for important announcement. </li></ul>
    4. 4. Other Important Policies <ul><li>All assignments are due at the beginning of the class time on the due day unless specified otherwise. No late turn-in will be accepted – no exceptions!! </li></ul><ul><li>No copying is allowed on any assignment. No credit will be given to both copier's and copiee's work. </li></ul><ul><li>All assignments should include your work, or else no credit will be given. </li></ul>
    5. 5. The Big Picture <ul><li>What is inside a computer? </li></ul><ul><li>How does it execute my program? </li></ul>?
    6. 6. The Big Picture <ul><li>The Five Classic Components of a Computer </li></ul>Control Datapath Memory Processor/CPU Input Output
    7. 7. System Organization I/O Bus Memory Bus Processor Cache Main Memory Disk Controller Disk Disk Graphics Controller Network Interface Graphics Network interrupts I/O Bridge Core Chip Set
    8. 12. What is Computer Architecture? <ul><li>Coordination of levels of abstraction </li></ul>I/O system CPU Compiler Operating System Application Digital Design Circuit Design <ul><li>Under a set of rapidly changing Forces </li></ul>Instruction Set Architecture, Memory, I/O Firmware Memory Software Hardware Interface Between HW and SW
    9. 13. Computer Architecture <ul><li>Architecture: System attributes that have a direct impact on the logical execution of a program </li></ul><ul><li>Architecture is visible to a programmer: </li></ul><ul><ul><li>Instruction set </li></ul></ul><ul><ul><li>Data representation </li></ul></ul><ul><ul><li>I/O mechanisms </li></ul></ul><ul><ul><li>Memory addressing </li></ul></ul>
    10. 14. Levels of Representation <ul><li>lw $15, 0($2) </li></ul><ul><li>lw $16, 4($2) </li></ul><ul><li>sw $16, 0($2) </li></ul><ul><li>sw $15, 4($2) </li></ul>High Level Language Program Assembly Language Program Machine Language Program Control Signal Specification Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
    11. 15. Instruction Set Interface instruction set software hardware Interface imp 1 imp 2 imp 3 use use use time
    12. 16. MIPS I Instruction Set Architecture <ul><li>Instruction Categories </li></ul><ul><ul><li>Load/Store </li></ul></ul><ul><ul><li>Computational </li></ul></ul><ul><ul><li>Jump and Branch </li></ul></ul><ul><ul><li>Floating Point </li></ul></ul><ul><ul><li>Memory Management </li></ul></ul><ul><ul><li>Special </li></ul></ul>R0 - R31 PC HI LO OP OP OP rs rt rd sa funct rs rt immediate jump target 3 Instruction Formats: all 32 bits wide
    13. 17. Organization <ul><li>-- Capabilities & Performance Characteristics of Principal Functional Units </li></ul><ul><ul><li>(e.g., Registers, ALU, Shifters, Logic Units, ...) </li></ul></ul><ul><li>-- Ways in which these components are interconnected </li></ul><ul><li>-- nature of information flows between components </li></ul><ul><li>-- logic and means by which </li></ul><ul><li>such information flow is controlled. </li></ul><ul><li>Choreography of FUs to realize the ISA </li></ul><ul><li>Register Transfer Level Description </li></ul>Logic Designer's View ISA Level FUs & Interconnect
    14. 18. Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction
    15. 19. Processor Performance 1 0 0 0 1 2 0 0 1 9 9 7 1 9 9 6 1 9 9 5 1 9 9 4 1 9 9 3 1 9 9 2 1 9 9 1 1 9 9 0 1 9 8 9 1 9 8 8 1 9 8 7 Copyright 1998 Morgan Kaufmann Publishers, Inc. All Rights Reserved H P 9 0 0 0 / 7 5 0 S U N - 4 / 2 6 0 M I P S M 2 0 0 0 M I P S M / 1 2 0 I B M R S 6 0 0 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 1 0 0 D E C A l p h a 5 / 5 0 0 D E C A l p h a 2 1 2 6 4 / 6 0 0 D E C A l p h a 5 / 3 0 0 D E C A l p h a 4 / 2 6 6 D E C A X P / 5 0 0 I B M P O W E R 1 0 0 Y e a r P e r f o r m a n c e 0
    16. 20. Performance Trends Year Performance 0.1 1 10 100 1000 1965 1970 1975 1980 1985 1990 1995 2000 Microprocessors Minicomputers Mainframes Supercomputers
    17. 21. Processor and Caches To main memory Processor Module External Cache Datapath Registers Internal Cache Control Processor
    18. 22. Memory Memory Controller Memory Bus DRAM SIMM SIMM Slot 0 SIMM Slot 1 SIMM Slot 2 SIMM Slot 3 SIMM Slot 4 SIMM Slot 5 SIMM Slot 6 SIMM Slot 7 DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM
    19. 23. Summary <ul><li>Goal </li></ul><ul><li>Understand basic operation of a computer </li></ul><ul><li>Why? </li></ul><ul><li>Software performance is affected/determined by HW capabilities </li></ul><ul><li>Future Computer Architects (Processor or System) </li></ul>
    20. 24. Summary (Continued) <ul><li>Agenda </li></ul><ul><li>Map “high-level” software to instructions </li></ul><ul><li>Instructions are composed of hardware primitives </li></ul><ul><ul><li>how to use them </li></ul></ul><ul><ul><li>how to implement them </li></ul></ul><ul><ul><li>why a particular primitive </li></ul></ul><ul><li>Memory for storing instructions and data </li></ul><ul><ul><li>Main memory </li></ul></ul><ul><ul><li>Caches </li></ul></ul><ul><ul><li>interaction with operating system </li></ul></ul><ul><li>Input/Output </li></ul>
    21. 25. Summary (Continued) <ul><li>All computers consist of five components </li></ul><ul><ul><li>Processor: (1) datapath and (2) control </li></ul></ul><ul><ul><li>(3) Memory </li></ul></ul><ul><ul><li>(4) Input devices and (5) Output devices </li></ul></ul><ul><li>Not all “memory” created equally </li></ul><ul><ul><li>Cache: fast (expensive, small) memory close to the processor </li></ul></ul><ul><ul><li>Main memory: slower, cheaper, larger memory farther from processor </li></ul></ul><ul><li>Input and output (I/O) devices has the messiest organization </li></ul><ul><ul><li>Wide range of speed: graphics vs. keyboard </li></ul></ul><ul><ul><li>Wide range of requirements: speed, standard, cost ... etc. </li></ul></ul>

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