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Batch no.2

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Batch no.2

  1. 1. A FAST CRYPTOGRAPHY PIPELINED HARDWARE DEVELOPED IN FPGA WITH VHDLPRESENTED BYK.KALPANA (093J1A0407)B.DURGA PRASAD (093J1A0418)L.SHIVA KRISHNA (093J1A0440)B.HARI KRISHNA (093J1A0419) GUIDE: P.VANNUR(M.tech), KOTTAM KRUNAKARA REDDY INSTITUTE OF TECHNOLOGY CHINNA TEKURU, KURNOOL-518 218
  2. 2. CONTENTS• ABSTRACT• INTRODUCTION• ADVANCED ENCRYPTION STANDARD• ENCRYPTION BLOCK DIAGRAM• ARCHITECTURE OF AES• ADVANTAGES• DISADVANTAGES• APPLICATIONS• CONCLUSION• FUTURE SCOPE
  3. 3. Key words• Cryptography• Pipeline• FPGA• AES
  4. 4. ABSTRACTMain objective :• The main objective of the project is to increase the speed of encryption and decryption by using pipelined hardware.• Pipelined hardware cryptography was used to improve performance in order to achieve higher throughput and greater parallelism.
  5. 5. What is FPGA ????• FPGA stands for field programmable gate array. Why FPGA ????
  6. 6. What is pipeline? 5IF ID EX M W 1 IF ID EX M W 1 IF ID EX M W 1 IF ID EX M W Four Pipelined Instructions
  7. 7. What is parallelism?????
  8. 8. INTRODUCTION• Cryptography - secret writing DES-Data Encryption Standard AES-Advanced Encryption Standard
  9. 9. Which is better (software or hardware based cryptograph)??????
  10. 10. AES-Advanced Encryption Standard What is AES???? and why AES????
  11. 11. Encryption phases 1.Subbytes 2.Shift rows 3.Mix columns 4.Addround key• For decryption algorithm will use respective inverse operations.
  12. 12. SubBytes – A non-linear substitution step where each byte isreplaced with another according to a lookup table (known as SBox).
  13. 13. ShiftRows – A transposition step where each row of the state isshifted cyclically a certain number of steps.
  14. 14. MixColumns – A mixing operation which operates on the columns of the state, combining the four bytes in each column using a linear transformation.
  15. 15. AddRoundKey – It is an XOR operation between the state and the round key.
  16. 16. Key Expansion - Three operations. 1.RotWord 2.SubWord 3.XOR operations
  17. 17. Block diagram of I/O of encryption
  18. 18. Block Diagram Of Encryption B U F Add F round E R key Sub Shift Add roundRound bytes rows keyskey Sub Shift Mix Add round bytes rows columns keysselector
  19. 19. AES architecture and its blocks 1.Key expansion 2.Encryption 3.Decryption
  20. 20. Architecture diagram of AES
  21. 21. Advantages• High Performance• Time to market• Reprogrammable• Reconfigurable• Long term maintenance Disadvantages• More expensive.• Power consumption is more.
  22. 22. FUTURE SCOPE• Micro electronics intends to use this work as part of larger projects such as smart metering in power systems and cryptography interface in data communication.
  23. 23. Conclusion
  24. 24. ThankQ
  25. 25. Queries….???

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