Vlsi cadence tutorial_ahmet_ilker_şin

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A CMOS inverter design in AMS 0.35 um in cadence for basic users

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Vlsi cadence tutorial_ahmet_ilker_şin

  1. 1. OKAN UNIVERSITYELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT EEE 459 Very Large Scale Integrated Circuits Cadence Tutorials AHMET İLKER ŞİN
  2. 2. Outlines Open PuTTy and VNC Viewer connection Running cadence Introduction to design flow Schematic entry of a CMOS inverter Create a new library Schematic of a CMOS inverter Generating symbol from schematics Transient simulation of Schematics Layout drawing Layout versus schematic check (LVS) Simulation of layout Simple design flow 2
  3. 3. Open Putty and VNC connectionOpen putty by click its icon in the quick launch menu 3
  4. 4. Double click on vlsi-1 to log on 4
  5. 5. Enter user name and passwordAnd finally ready to using vncviewer 5
  6. 6. Open VNC by click its icon in the quick launch menu Click OKEnter your password 6
  7. 7. So , you are connected to the server andready to run cadence 7
  8. 8. RUNNING CADENCE Cadence is one of the most widely used IC design software all overr the world. It contains many subprograms each of which is responsible from one step in IC design flow. In the content of this tutorial you will learn lowlevel(transistor level)design tools of the cadence 8
  9. 9. Right click on the desktop and click to‘’Konsole’’ 9
  10. 10. This will make a directory named tutorial Enter newly created tutorial directoryChoose c35b3 as the technology file and This command generates a link to the script file requiredWrite ams_cds –tech c35b3 –mode msfb to run cadence 10
  11. 11. Now , cadence is opening… 11
  12. 12. So you have running cadence now 12
  13. 13. Then , select process option as ‘’c35b3c0’’, click apply and OK 13
  14. 14. Introduction to design flow LayoutDesign Specification DRC – Design RuleSchematic Capture Check ExtractionCreate Symbol LVS – Layout versusSimulation Schematic check Post Layout Simulation Sign Off 14
  15. 15. SCHEMATIC ENTRY OF A CMOS INVERTER Create a new library  In this tutorial , we will start using cadence and design our first CMOS inverter. Do not forget that , you have to learn every step in this tutorial.  Initially starting to design, we have to create a library, that will contain all the circuits that you will implement during this laboratory. 15
  16. 16. Open library manager window by tools -->library manager on msfb-log window 16
  17. 17. Choose ,File  New  Library 17
  18. 18. On the newly appeared window , click ‘’Write ‘’EEE 459’’ to the name of the Attach to an existing techfile’’ button andlibrary as seen on the window then press click OKOK 18
  19. 19. Again new window will appear to choosethe technology library.Choose‘’TECH_C35B3’’ from the menu . This isthe technology library for 0.35 u fabricationprocess then click OK 19
  20. 20. We got new library , now we will continuemaking a new cell.Click on library ‘’eee459’’ which you have added previously.There is not cellview in the ‘’eee459’’library yet.Click on FileNewCell view 20
  21. 21. Write ‘’inverter’’ to the cell name.Be surethat view name is ‘’schematic’’.Altough theothers are default,click OK 21
  22. 22. Now , Virtuoso schematic editing windows is opened.As you see, you will work with a black background.There is a toolbox on left.Most of thecommands in the menus have short-keysand some of required short keysmentioned in the tutorial 22
  23. 23. Then ‘’Add instance’’ window is opened,then click BrowseNow , we will add a transistor.Click on Addİnstance from the menu. The shortcutkey for this command is ‘’i’’. 23
  24. 24. Click on the browse and find ‘’PRIMLIB’’ inLibrary then select ‘’Mosfets’’ in Categoryand ‘’nmos4’’ to cell.View will be ‘’ Symbol’’by default,check it. 24
  25. 25. Then insert NMOS transistor to schematicWidth,length and other properties of the editor, in the same way for ‘’pmos4’’ cell andtransistor can be changed in this window or insert one PMOS transistor. Due to we areyou can change them later making an inverter that PMOS transistor should be to top. 25
  26. 26. Now,we will draw the connections.Click toAddwire(narrow) or press ‘’w’’.Click atthe start and end points of the wires.Don’tforget to connect bulk connections both oftwo transistor as seen in the figure 26
  27. 27. When place to VDD and GND , directionhave to be selected ‘’inputoutput’’ ,check it Then , we will add pins of the circuit. Click on Pin or press ‘’p’’ in order to add pins of the circuit,Firstly we will add VDD and GND 27
  28. 28. When you insert the ‘’in’’, direction have tobe selected ‘’input’’ and insert the ‘’output’’,direction have to be selected ‘’output’’ 28
  29. 29. HİNT : you can zoom İN or OUT by using the buttons on the toolbar or using window  , ‘’f’’ auto-zooms the current design.Either you can click-and drag using 3rd button(right button) of the mouse,that zooms the drawn box.when you have zoomed to a wrong place,press ‘’f’’ in order to fit the circuitİf you get some warning messages , check theyellow markers,if there is no problem, you willget any warning or error 29
  30. 30. Click ‘’Check and Save’’ As you see , when connected to pins, yellow markers and net names are disappear 30
  31. 31. Generating symbol from schematic Click on DesignCreate Cell ViewFrom Cell View . Every cell should have a symbol view in order to be used in other circuits. 31
  32. 32. Be sure that ‘’To view Name’’ is ‘’symbol’’ and ‘’Tool/Data Type’’ is ‘’Composer-Symbol’’ as the following figureYou will get ‘’ Symbol Generation Options’’.Write ‘’gnd’’ to the ’’Bottom Pins’’and clickOK with default settings 32
  33. 33. A new window is appear showing your new box-shaped symbol view You have finished to design of schematics and copied the symbol of the inverter.You are ready to start simulations of this schematics. Before this , I will give a few notes here 33
  34. 34. NOTES You can see the properties of transistor or any other components by pressing ’’q’’ or clicking on EditPropertiesObjects,after choosing the object (by clicking on it). When an object is selected, its borders become visible. For the transistor, it is possible change the aspect ratios by changing "Width" and "Length’’ which are "10u" and "0.35u" by default. u is used micro and "m" is used for "mili"here. You can move objects by ‘’m’’ or ‘’EditMove’’. Copy and deleting objects are similar also.See the menus and shortcuts. 34
  35. 35. TRANSİENT SIMULATION OFSCHEMATİCS In order to simulate a circuit , you need to define the input- output and vdd-gnd , for this purpose we will generate another cell Make a new cell ‘’inverter’’ in ‘’EEE459’’ library with ‘’schematic’’ view , using FileNewCellview on the library manager window 35
  36. 36. Write ‘’ inverter_tb’’ to the ‘’Cell Name’’ and clickOK 36
  37. 37. ‘’ Virtuoso schematic editing’’ window isopened then click ‘’Add Instance’’(or press ‘i’)and click ‘’Browse’’ 37
  38. 38. Library Cell nameEEE459 inverter Now ,lets add the following components as seen on the table and draw the ciruitanalogLib vpulseanalogLib vdcanalogLib capanalogLib gnd 38
  39. 39. We have added inverter symbol from EEE459Library 39
  40. 40. analogLİbvdcsymbol Now, we will add ‘’vdc’’ from ‘’AnalogLİb’’ 40
  41. 41. When insert the ‘’vdc’’ , ‘’Add ınstance’’ menu willopen .Here ‘’vdc’’ will be used to apply VDDvoltage Write ‘’3.3 v’’ to ‘’DC voltage’’ , if you want change properties of the component later, press ‘’q’’ and change it 41
  42. 42. analogLibSourcesIndependentvpulsesymbol Now,we will add ‘’vpulse’’ from ‘’analogLib’’ 42
  43. 43. When insert the ‘’vpulse’’ , ‘’Addınstance’’ menu will open .Vpulse isgenerate pulse signals with‘’Voltage1’’ and ‘’Voltage2’’ levels.Thedelay time at the beginning of thesimulation is determined by DelayTime. Also rise time, Fall time,Pulsewidth,and period are determined bythese properties Change the properties of ‘’vpulse’’ as shown in figure.Remember that ‘’n’’ stands for ‘’nano’’ and ‘’u’’ stands for ‘’micro’’ 43
  44. 44. analogLibPassivescapsymbol Now,we will add ‘’cap’’ from ‘’analogLib’’ 44
  45. 45. İnsert the ‘’cap’’Change the capacitance of ‘’cap’’ to ‘’100.0f F’’ 45
  46. 46. analogLibSourcesGlobalsgndSymbolNow,we will add ‘’gnd’’ from ‘’analogLib’’ 46
  47. 47. Place ‘’gnd’’ components in determined location 47
  48. 48. Now,we will draw the connections.Click toAddwire(narrow) or press ‘’w’’.Click at the startand end points of the wires 48
  49. 49. Then, we use ‘’Wire Name’’ in order to namedwires 49
  50. 50. When you click on ‘’Wire Name’’ button , ‘’AddWire Name’’ window will be opened. Write ‘’in’’to ‘’Names’’ and place to related point and dothe same things to other wire connection 50
  51. 51. This is the last view of the circuit.Press ‘’checkand save’’ 51
  52. 52. Now, click on ‘’Tools’’’’Analog Environment’’ inorder to run analog simulator 52
  53. 53. Click on AnalysesChoose ( you can select ‘’choose Analyses’’ to do the same thing) 53
  54. 54. ‘’tran’’ is chosen as the default analysis time.Write 4u to the ‘’Stop Time’’.You haveprogrammed the simulator to simulate thetransient response of the circuit for 4usecond.Select ‘’Enabled’’ and click OK 54
  55. 55. After selected the properties of AnalogEnvironment Click on SessionSave State.Then ‘’Saving State’’ window will be opened. 55
  56. 56. On this window, select ‘’Cellview’’ in ‘’ SaveState Option’’ skip then press OK 56
  57. 57. When you apply thiss process ‘’spectre_statel’’ will be appear on ‘’Library Manager’’.Whenyou click on ‘’spectre_statel’’, ‘’Virtuoso Analog environment’’ window will appear on thescreen that you have selected and saved analyses properties. Thus you can make analysisquickly 57
  58. 58. Come to ‘’Simulaton’’ skip and click ‘’Netlist andRun’’ 58
  59. 59. When you click on ‘’Netlist and Run’’ simulationfile will be ready and log file window will beappear in screenWhen you go down on log window that you will see ‘’spectre completes with 0 error, 0 warning and 2 notices. This note is announce to simulation succesful , then‘’check and save’’ on the Schematics 59
  60. 60. In order to take out waveform window ,click onResultsDirect PlotTransient Signal.After thisprocess waveform window will be opened 60
  61. 61. Waveform window is opened but there isnot any wave as you see.So we have todetermine the nodes in order to find outgraphics. 61
  62. 62. According to we want to see output , we have toselect wire of out labelled as you see After selected to out wire that you will be notice that change of the wire colour from blue to green. Then press ‘’ESC’’ 62
  63. 63. And Finally waveform of output is come out If you want to see two or more waveform on the screen 63
  64. 64. In ‘’ Virtuoso Analog Design Environment’’window taht select in turn in order OutputsToBe PlottedSelect On Schematic This will let youchoose the nodes to be observed 64
  65. 65. There are 2 type of signal to be observed after the simulation :Voltage and Current.If you click on the wire, you select thatwire’s voltage as the observed signal (white circled).If youclick on the node like the input of the inverter, you select thecurrent of that node as the observed signal. You see circle onthat node. Focus on the schematics editor and click on vpulse node (circled),the wires at the input and output of the inverter Then,Check and Save schematics 65
  66. 66. After you have selected ‘’vpulse ‘’ node , input and output wirethat you will notice that selected wires and nodes will appear in‘’Virtuoso Analog Design Environment’’ on Outputs heading 66
  67. 67. When you have click on turn in order ‘’in’’ ,‘’out’’,’’V1/PLUS’’ , ‘’Setting Outputs’’ window will beopened. Select ‘’Saved’’ and click OK 67
  68. 68. Click on ‘’SimulationNetlist and Run’’ to startthe simulation.After the simulation is completed,a waveform window will be opened.Do notforget to ‘’Check and Save’’ the schematicsbefore running the simulation 68
  69. 69. In order to see these signals seperately.click on‘’AxesTo strip’’ at waveform window. You should see a waveform similar to the figure.Three different colours represent the vpulse as current waveform,input and output of inverter.As seen the input signal is inverted,so the operation of the circuit is correct 69
  70. 70. Just like that… Would you want to learn which one is input and which one is output?Well,if you click on the wires on the schematics and press ‘’q’’. You will see the properties of them.You can see the names of the wires there 70
  71. 71. As you see on the waveform window these graphs arecalled ‘’ Square Waveforms’’. I will inform about squarewave forms in proceeded slides 71
  72. 72. SQUARE WAVE WAVEFORMS Square-wave Waveforms are used extensively in electronic and micro electronic circuits for clock and timing control signals as they are symmetrical waveforms of equal and square duration representing each half of a cycle and nearly all digital logic circuits use square wave waveforms on their input and output gates. Unlike sine waves which have a smooth rise and fall waveform with rounded corners at their positive and negative peaks, square waves on the other hand have very steep almost vertical up and down sides with a flat top and bottom producing a waveform which matches its description 72
  73. 73. A Square Wave Waveform Pulse Rising or Width Leading+A edge Falling or Trailing Edge Amplitude Positive Negative Half Half0 One Cycle or Period T 2T 73
  74. 74. We know that square wave waveforms are symmetrical in shape as each halfof the cycle is identical, so the time that the pulse width is positive must beequal to the time that the pulse width is negative or zero. When square wavewaveforms are used as "clock" signals in digital circuits the time of thepositive pulse width is known as the "Duty Cycle" of the period. Then we cansay that for a square wave waveform the positive or "ON" time is equal to thenegative or "OFF" time so the duty cycle must be 50%, (half of its period). Asfrequency is equal to the reciprocal of the period, ( 1/T ) we can define thefrequency of a square wave waveform as : 74
  75. 75. ExampleA Square Wave waveform has a pulse width of 10ms,calculate its frequency.For a Square wave waveform, the duty cycle is givenas 50%, therefore the period of the waveform must beequal to: 10ms + 10ms or 20ms 75
  76. 76. So to summarise, Square wave Waveforms aresymmetrical in shape and have a positive pulse widthequal to the negative pulse width resulting in a 50%duty cycle. Square wave waveforms are used in digitalsystems to represent a logic level "1", high amplitudeand logic level "0", low amplitude 76
  77. 77. LAYOUT DRAWİNG Basics of layout drawingUntil now , you designed your circuit and simulated it in the virtual environment.To convert your design to real world , you need to draw te layout of it. Layout drawing is not as easy as drawing wires in the schematics because you need considering the real(physical) structure of the circuit. Do not forget that , layout drawing is important and it is a job title in the VLSI desihn centers.This section is very important. Although all the steps here will be explanied in this tutorial , try to understand by yourself first in order to gain time. 77
  78. 78. What is LAYOUT ?Layout is the drawings of masks used during the fabrication of the CMOS chips. Masks are kinds of filters used to shape various layers. Each layer in CMOS fabrication, like Polysilicon layer or metal layer, are shaped with a different mask. Considering our purpose as the designer, we have the ability to change very restricted number of variables during design. For instance we cannot change the thickness of the oxide layer in the gate, but we can change the width of the gate. During layout drawing, we will consider only the width and length of a metal layer, not the thickness. 78
  79. 79. LAYOUT DRAWING USING CADENCE In the previous part, layout drawing basics are given. In this tutorial, the layout will be drawn using Cadence. At the end of the tutorial the design will be checked in order to verify the physical structure of the drawn layout. 79
  80. 80. Now we can start drawing the layout of theinverter. Open Library Manager byTools>Library Manager on icfb window. 80
  81. 81. And Library Manager has opened İn Libary Manager window , Schematic have to be selected under to view skip as seen on the figure First create a new cell view for the inverter. Select File> New >Cell View 81
  82. 82. On ‘’Create New File’’ window that select "Virtuoso" as the tool, also make sure that library name is "EE459" and cell name is "inverter". Click OKAfter selected ‘’Virtuoso’’ as the tool,wiewname will be changed as layout 82
  83. 83. Two new windows wiil appear. One is named as ‘’LSW’’and the other one is the layout window.LSW is a palette from which you can select the masklayer you want draw with.At the moment it list thelayers defined in TECH_C35B3 process. Although thereare lots of layers listed, only some of themWill be used. Some of the layers have two differentversions like ‘’POLY1 drw’’ and ‘’POLY1 pin’’. ‘’drw’’stands for drawing and ‘’pin’’ stands for pin .Whiledrawing the layout only ‘’ drw’’ layers should beused. 83
  84. 84. The Layer Selection Window (LSW) Active layerInstances /Pins selectable Visibility & selection control for all layers AV : All layers visible & selectable NV : All layers invisible & unselectable AS : All visible layers selectable NS : All visible layers unselectable Layer List Click with LEFT mouse button to select the layer as the ACTİVE layer Click with MIDDLE mouse button to switch VISIBILITY of the layer Click with RIGHT mouse button to switch SELECTABILITY of the layer 84
  85. 85. Layer Available Process CornersNTUB N well for pmos devicesDIFF Used for drawing any diffusion (n or p type) for transistor as well as for substrate and well contactsNPLUS Designates any diffusion within the box to be n-type diffusion(used for the DIFF layer)PPLUS designates any diffusion within the box to be p-type diffusion(used for the DIFF layer)POLY1 1st layer poly-silicon,used for transistor gatesPOLY2 2nd layer poly-silicon (used for capacitors)CONT Designates contact from diffusion to MET1MET1-4 Four metal layers; ‘’drw’’ and ‘’pin’’ are the same but appear different on the screen (‘’drw’’ is used for standard drawing and ‘’pin’’ for pins)VIA1 Metal via between MET1 and MET2 (similar for VIA2-3)PAD Designates area for bonding pads where the protective silicon-dioxide layer will be etched away (used only at the end of the project) The LSW and some commonly used layers 85
  86. 86. Note: Most layers are available in three different types: drawing layer (drw),pin layer(pin) and net layer (net). The circuit elements are laid out using thedrawing layers. The pin layers are used only for pins and are logical layers.The net layers are generated automatically during extraction. Aside: Due to a bug in Cadence, you cannot actually close the LSW window once it opens unless you exit Cadence. 86
  87. 87. Layout Editor MenusOn ‘’ Virtuoso Layout Editing ‘’ window ,there are some essantial tools to drawlayout. Commonly used tools have circled 87
  88. 88. On ‘’ Virtuoso Layout Editing ‘’ window selectOptions  Layout Editor and when ‘’LayoutEditor Options ‘’ window opened , you noticethat diselect of the ‘’Gravity on’’ tabs Don’tchange this option 88
  89. 89. On ‘’ Virtuoso Layout Editing ‘’ window selectOptions  Display and ‘’Display Options’’window will be opened Notice that ‘’ X Snap Spacing ‘’ and ‘’ Y Snap Spacing ‘’ values equal to 0.05 Don’t change this values 89
  90. 90. On ‘’msfb’’ window click Options  UserPrefences 90
  91. 91. Click ‘’Options Displayed When Commands Start‘’ option and enabled it .Due to this option ,when you selected any tools (move ,ruler,pathetc… ) a window will be opened interested tool 91
  92. 92. Create ruler Window  Create Ruler Hotkey : k 92
  93. 93. Rectangle Create  Rectangle Hotkey : r 93
  94. 94. Clear All Rulers Window  Clear All Rulers Hot key : shift + k 94
  95. 95. Stretch Edit  Stretch Hot Key : s When applied this command , your drawing can be adjustable as extend or shorten 95
  96. 96. Move Edit  Move Hot Key : m Due to this Option you can carry your drawings , or various parts to any point in your layout screen 96
  97. 97. Copy Edit  Copy Hot Key : c Through using this command you are able to copy any items and changed by ‘’Rows‘’ and ‘’Columns’’ values on copy window that copied intended nummer 97
  98. 98. Path Getting started to draw path , when click to right mouse button once , rotate of the drawing path will be changed and in order to finish drawing path againly click to right mouse button twice as Create Path Hot Key : p If you want to change width of the path , you can adjust from this tap 98
  99. 99. Merge Edit  Merge Hot Key : shift +m Merge command is integrate two or more ıtems. Select related drawings and make shift + m 99
  100. 100. Chop Chop command is cut certain region in selected part . Firstly click on the part that want to chop and you will see that appear the white line outside of the related part finally select want to cut with right mouse button Edit  Other Chop Hot Key : shift + c 100
  101. 101. We are going to use the analog synthesiscapability of the tool to generate anapproximate layout in order to minimize theeffort as much as possible. Open theschematic view of the “inverter” cell in the“eee459” library that you created in SchematicEntry. This should be similar to on Figure The schematic view of the inverter cell 101
  102. 102. Then ‘’Add instance’’ window is opened,then click BrowseNow , we will add a layout oftransistor.Click on Add İnstance from themenu on Virtuoso Layout Editing window.The shortcut key for this command is ‘’i’’. 102
  103. 103. Click on the browse and find ‘’PRIMLIB’’ inLibrary then select ‘’Mosfets’’ in Categoryand ‘’pmos4’’ to cell.View will be ‘’ layout’’by default,check it 103
  104. 104. When we select Pmos as layout form , createinstance menus will be appear.To start off, it isbest to utilize the capability of the tool Selectthe “Parameter” tab and scroll down to see theproperties you can configure. ( or Select thePMOS and press“q” to bring up its properties) Check the“Substrate Contact” button as shown in figure 104
  105. 105. After select this option and as you bring the cursor onthe layout window , Pmos layout symbol come out onwindow as yellow grid. İf one clicked on symbol , Pmossymbol will be appear currently on window 105
  106. 106. Finally our Pmos layout came out completely Note that you can also add or remove the top and bottom contacts if necessary. Press “OK”, and the layout window will update to include a substrate contact for the PMOSIMPORTANT Place the PMOS above it, flipping itupside down, so that the substrate contactsare at the top of the block. You can rotate anobject while moving it by rightclicking 106
  107. 107. Metal 1 substrate contacts for the PMOS consistsof an NPLUS area along with DIFF, and theactual contact with CONT and MET1 107
  108. 108. Now , we will add a layout of Nmos. Click on Add İnstance from the menu on Virtuoso Layout Editing windowClick on the browse and find ‘’PRIMLIB’’ inLibrary then select ‘’Mosfets’’ in Categoryand ‘’nmos4’’ to cell.View will be ‘’ layout’’by default,check it 108
  109. 109. Check the “Substrate Contact” button and place Nmos transistor layout to Virtuoso Layout Editing Window 109
  110. 110. 110
  111. 111. On LSW window that select ‘’NV’’ tabs select ‘’POLY1 (drw)’’ and ‘’MET1 (drw)’’ after that press ‘’f’’ on Virtuoso Layout Editing window 111
  112. 112. PMOS Through this operation that you can see only ’’POLY1 (drw)’’ and ’’MET1 (drw)’’ of layout of transistors. To see the previous one , click ‘’AV’’ on LSW and press ‘’f’’ on Virtuoso Layout Editing windowNMOS 112
  113. 113. Now we place contacts over here Press ‘’o’’ to create a contact automatically by choosing between pre-defined contacts 113
  114. 114. These contacts are described in Table ContactTypes Available in the HitKit Process Layer DescriptionVIA1_C Contact between MET1 and MET2VIA2_C Contact between MET2 and MET3VIA3_C Contact between MET3 and MET4P1_C Contact between MET1 and POLY1P2_C Contact between MET1 and POLY2ND_C Contact between MET1 and NTUBPD_C Contact between MET1 and Psubstrate 114
  115. 115. Since you want to contact POLY1 and MET1,choose ‘’P1_C’’. Lay the contact sothat the mid points of the “POLY1” and thecontact coincide. You can zoom in onthe pin to make sure you place it exactly. 115
  116. 116. When you use ruler(k),you will see width andlength of POLY is 0.3500.To place P1_C contactcompletely , change width and length values to0.35 116
  117. 117. Connect the metal via using ‘’MET1’’ dgfrom ‘’LSW’’ as shown in Figure.Connectionscan be drawn using the create path <p>commands. Through this connection,‘’MET1’’ and ‘’POLY1’’ will be connected. 117
  118. 118. To start path , click on the middle of the‘’P1.C’’ poly extension on NMOS , youwill see a ghost yellow line appear.Move this ghost line to the other ‘’P1.C’’poly extension belong to PMOS 118
  119. 119. Finally, The gates of PMOS and CMOS are connected as in the figureA single click will finish a line segmentand let you continue drawing , adouble click will finish the path 119
  120. 120. Now , we will connect drain of NMOS tosource of PMOS to appear output. Tostart path click on the middle of theNMOS drain (MET1)rail and you will seea ghost yellow line appear again.Movethis ghost line to PMOS of the source(MET1) rail 120
  121. 121. and the output connection hasconnected between PMOS and NMOS 121
  122. 122. Creating PinsYou will need to create 4 pins (vdd,gnd,output,in) todefine your terminal names , to pass DRC for theinverter cell.From your layout window ; choose‘’Create’’  ‘’pin’’ from the menu . The CreateSymbolic Pin window will appear 122
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