9.sequential+circuits part+1


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9.sequential+circuits part+1

  1. 1. Sequential Circuit Design: Part 1• Design of memory elements – Static latches – Pseudo-static latches – Dynamic latches• Timing parameters• Two-phase clocking• Clocked inverters James Morizio 1
  2. 2. Sequential Logic Φ FFs LOGIC tp,combOut In 2 s to rag e mechanis ms • po s itive feedback • charg e-bas ed James Morizio 2
  3. 3. Sequencing• Combinational logic – output depends on current inputs• Sequential logic – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline clk clk clk clk in out CL CL CL Finite State Machine Pipeline James Morizio 3
  4. 4. Sequencing Cont.• If tokens moved through pipeline at constant speed, no sequencing elements would be necessary• Ex: fiber-optic cable – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But dispersion sets min time between pulses• This is called wave pipelining in circuits• In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones. James Morizio 4
  5. 5. Sequencing Overhead• Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.• Inevitably adds some delay to the slow tokens• Makes circuit slower than just the logic delay – Called sequencing overhead• Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence James Morizio 5
  6. 6. Sequencing Elements• Latch: Level sensitive – a.k.a. transparent latch, D latch• Flip-flop: edge triggered – A.k.a. master-slave flip-flop, D flip-flop, D register• Timing Diagrams clk clk Latch Flop D Q D Q – Transparent – Opaque clk D – Edge-trigger Q (latch) Q (flop) James Morizio 6
  7. 7. Flip-Flop: Timing Definitions Φ t tse tup tholdIn DATA STABLE t tpFFOut DATA STABLE t James Morizio 7
  8. 8. Maximum Clock Frequency Φ FFs LOGIC tp,comb James Morizio 8
  9. 9. Latch Design• Pass Transistor Latch φ• Pros + Tiny D Q + Low clock load• Cons Used in 1970’s – Vt drop – nonrestoring – backdriving – output noise sensitivity – dynamic – diffusion input James Morizio 9
  10. 10. Latch Design φ• Transmission gate + No Vt drop D Q - Requires inverted clock φ James Morizio 10
  11. 11. Latch Design φ• Inverting buffer D X Q + Restoring φ + No backdriving φ + Fixes either D Q • Output noise sensitivity φ • Or diffusion input – Inverted output James Morizio 11
  12. 12. Latch Design φ• Buffered input X D Q + Fixes diffusion input φ φ + Noninverting φ James Morizio 12
  13. 13. Latch Design φ Q• Buffered output D X + No backdriving φ φ φ• Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 – 2 FO4 delays) - High clock loading James Morizio 13
  14. 14. Latch Design φ• Tristate feedback X D Q + Static φ φ – Backdriving risk φ• Static latches are now essential James Morizio 14
  15. 15. Latch Design φ Q• Datapath latch D X + Smaller, faster φ φ - unbuffered input φ James Morizio 15
  16. 16. Design of Memory Elements D C C Φ C Φ C Φ Φ Q Q Positive edge-triggered D flip-flop Why use inverters on outputs?Skew Problem : Φ may be delayed with respect to Φ (both may be 1 at the same time)This is what happens- Q D Eliminating/Reducing skew: Q Φin Φ 1 Transmission gate acts a buffer, should have same C Φ delay as inverter James Morizio 16
  17. 17. Latch design C Q D C QD Φ C Φ Φ Φ Static D latch “Jamb” latch Weak inverter James Morizio 17
  18. 18. Latch Design Variant of D latch C C D Φ Q Φ Φ ΦD Q Φ Φ James Morizio 18
  19. 19. Flip-Flop Design• Flip-flop is built as pair of back-to-back latches φ φ X D Q φ φ φ φ Q X D Q φ φ φ φ φ φ James Morizio 19
  20. 20. Enable• Enable: ignore clock when en = 0 – Mux: increase latch D-Q delay – Clock Gating: increase en setup time, skew Symbol Multiplexer Design Clock Gating Design φ en φ φ D 1 Latch Latch Latch D Q Q D Q 0 en en φ en φ φ D 1 Flop Q 0 Flop Flop D Q D Q en en James Morizio 20
  21. 21. Reset• Force output low when reset asserted• Synchronous vs. asynchronous φ φ Symbol Latch Flop D Q D Q reset reset Synchronous Reset φ Q φ φ Q reset reset Q D D φ φ φ φ φ φ φ φ φ Q Q φ Asynchronous Reset φ φ reset reset D D φ φ φ φ φ φ reset reset φ φ φ James Morizio 21
  22. 22. Set / Reset• Set forces output high when enabled• Flip-flop with asynchronous set and reset φ φ reset set QD φ φ φ φ set reset φ φ James Morizio 22
  23. 23. Dynamic Latches• So far, all latches have been static-store state when clock is stopped but power is maintained• Dynamic latches reduce transistor count• Eliminate feedback inverter and transmission gate• Latch value stored on the capacitance of the input (gate capacitance) James Morizio 23
  24. 24. Dynamic Latch and Flip-Flop D C Q CDynamic D latch Data stored as Φ Charge on gate capacitance D C C QDynamic negativeedge-triggered D Φ Φflip-flop• Difficult to ensure reliable operation• Similar to DRAM• Refresh cycles are required James Morizio 24
  25. 25. Charge-Based Storage Q ΦD Q Φ Non-overlapping clocks Schematic diagram P s e u d o -s ta tic La tc h James Morizio 25
  26. 26. Master-Slave Flip-Flop Φ Φ Q AD B Φ Φ To reduce skew: generate complement of clock within the cell Extra inverter per cell Overlapping Cloc ks Can Caus e • Race Conditions • Undefined Signals James Morizio 26
  27. 27. Two-Phase Clocking• Inverting a single clock can lead to skew problems• Employ two non-overlapping clocks for master and slave sections of a flip-flop• Also, use two phases for alternating pipeline stages James Morizio 27
  28. 28. Two-Phase ClockingΦ D C C Q 1Φ 2 Φ1 Φ 2 Φ1(t) . Φ2(t) = 0 Φ1=1, Φ2 = 0 D Q Φ1=0, Φ2 = 1 D Q James Morizio 28
  29. 29. 2-phase non-overlapping clocks Φ2Pseudo-static Φ1 QD flip-flop D Φ2 Φ1 Φ1 Important: Φ2 Non-overlap time t must be kept small t James Morizio 29
  30. 30. 2-phase dynamic flip-flop φ1 φ2 D Q Input Sampledφ1φ2 Output Enable James Morizio 30
  31. 31. Use of “p” Leakers Φ1 Φ2 No need to routeFlip-flop D Q Φ signalsbased on nMOSpass gates Degraded voltage VDD-Vt Φ1 Φ2 D Q pMOS leaker transistors provide full-restored logic Problem: Increased delay levels (extra inverter) James Morizio 31
  32. 32. Clocked Inverters Φ Similar to tristate buffer Φ = 1, acts as inverter Φ = 0, output = Z Φ Φ Q D i1 i2 i3 ΦD Q Φ D Latch James Morizio 32
  33. 33. Flip-flop insensitive to clock overlap VDD VDD M2 M6 φ M4 φ M8 X In D CL1 CL2 φ M3 φ M7 M1 M5 φ−section φ−section C2MOS flip-flop James Morizio 33
  34. 34. C2MOS avoids Race Conditions VDD VD D VDD VDD M2 M6 M2 M6 0 M4 0 M8 X XIn D In D 1 M3 1 M7 M1 M5 M1 M5 (a) (1-1) overlap (b) (0-0) overlap James Morizio 34