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Juniper Networks Router Architecture

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Juniper Networks Router Architecture
[Scholarly Paper Presentation]

Juniper Networks Router Architecture

  1. 1. Juniper Networks Router Architecture<br />[NGN Router OS]<br />Scholarly Paper Presentation<br />(In partial fulfillment for MS Degree in Computer Engineering)<br />Advisor: Dr. Jeremy Allnutt<br />Co-advisor: Dr BijanJabbari<br />George Mason University, Fairfax, Virginia<br />Lawrence Awuah<br />lawuah@gmu.edu<br />ljawuah@ieee.org<br />Fall 2007<br />
  2. 2. Summary<br /><ul><li>Design Objectives
  3. 3. Architecture Overview
  4. 4. Specific TX Matrix & T640 Routing node Implementation
  5. 5. Packet Forwarding and ASIC Design
  6. 6. Switch Fabric Implementation</li></li></ul><li>Router Description<br /><ul><li>A router is simply a computer networking device that interconnects separate logical subnets and forwards data packets along networks.
  7. 7. Routers operate in two different planes:</li></ul>Control Plane<br /> The control plane defines the part of the router architecture that is concerned with generating the networkrouting table. Control Plane processing leads to the construction of RIB and FIB in memory.<br />Forwarding Plane<br /> The forwarding plane is responsible for packet forwarding. <br /> This planeis responsible for processing packets in hardware before forwarding them across the switch fabric from the ingress interface to the appropriate egress interface - HS packet processing.<br />
  8. 8. RouterDesign Objectives<br /> The TX Matrix platform [max four T640 routing nodes] was designed with these predefined objectives:<br /><ul><li>Packet forwarding performance
  9. 9. Bandwidth density
  10. 10. Security
  11. 11. Single software image
  12. 12. Multi-chassis capability
  13. 13. IP service delivery
  14. 14. High availability
  15. 15. Expandable average lifetime</li></ul>Leading to CAPEX & OPEX savings - replacing old equipment vs. installing new equipment every few years + operational cost.<br />
  16. 16. ArchitectureOverview<br />The Juniper router architectural design isolates control plane functions from that of data plane, incorporate modular and microkernel approach in its OS structure.<br /> Separation of Control plane and Forwarding planefunctions<br />The router architecture separates routing and control functions from packet forwarding operations.<br /><ul><li>separate specialized forwarding processor from the main processor.
  17. 17. forwarding no longer had to compete with control functions in a single processor.</li></li></ul><li>SeparationOf The Two Processing Functions [RE & PFE]<br />
  18. 18. ModularOperating Systems<br /><ul><li>With a modular design, network functions are broken up into distinct processes with standard interfaces with each process operating independently.
  19. 19. A set of dynamically loadable applications with their own separate and protected memory spaces – security, flexibility, speed.
  20. 20. All processes (RPD, Device control process, SMNP daemon, PFE daemon, etc) communicate via IPC. </li></li></ul><li>Themicrokernel approach<br /><ul><li>The only part of the system executing in kernel-mode.
  21. 21. Minimal operating system kernel.
  22. 22. Most operating-system services are provided in user-mode - functions such as the host stack, device drivers, or file system run in user mode.
  23. 23. The modularity and microkernel approach share almost the same design objectives.</li></li></ul><li>Benefits of modular OS design<br /><ul><li>Loading of new application modules during run-time operation without affecting device uptime.
  24. 24. Minimal system downtime.
  25. 25. Graceful restart and gracefuldegradation capabilities.
  26. 26. Dynamic loading and start/stop capability allows frequent system refresh cycles.
  27. 27. Kernel-loadable modules.
  28. 28. Kernel protection and security.
  29. 29. Onlineoperating system adjustments (OIR).</li></li></ul><li>TX Matrix Architecture(Maximum of 4 T640 Routing Nodes)<br />TX Routing Matrix: T640 Routing Nodes:<br />-Performs Routing Functions -Distributed Packet Forwarding<br />-Stage 2 of CLOS Switch Fabric (F2-stage) -Stages 1 & 3 of CLOS Fabric (F1&F3-stage)<br />-Single Management Interface -REs: local chassis management<br />-64 PFEs in TX routing matrix -16 PFEs in T640 routing node<br />=> 64x64 Fabric ASICs [multi-chassis] => 16x16 Fabric ASICs [single-chassis]<br />
  30. 30. The TX Matrix Platform<br />A Juniper Networks Routing Matrix <br />(distributed design)<br /><ul><li>Three main components:
  31. 31. T640 Routing Nodes (4 maximum)
  32. 32. maintains distributed packet forwarding decisions
  33. 33. also known as line-card chassis (LCCs) providing network interfaces for the routing matrix
  34. 34. A TX Matrix platform
  35. 35. executes the routing protocols for the routing matrix and maintains system state
  36. 36. provides services to switch fabric that interconnects the individual T640 routing nodes also know as the switch-card chassis (SCC)
  37. 37. A set of cables
  38. 38. Fiberoptic array cables (VCSEL) and high speed Ethernet cables that interconnect the respective data and the control planes of each individual chassis into the routing matrix </li></li></ul><li>Packet Forwarding Architecture<br />T640 Routing NodePacket Forwarding Architecture<br /><ul><li>The packet forwarding architecture of a routing matrix is a straightforward extension of that of a stand-alone T640 routing node.
  39. 39. Understanding the architecture of the T640 routing node is necessary.</li></li></ul><li>ASIC-Based Design[PIC, FPC, PFE]<br />
  40. 40. Routing Engine [RE]<br /><ul><li>The RE consists of;</li></ul>- an Intel-based PCI platform (CPU ) running the JUNOS software. <br />- SDRAM for storage of the routing and forwarding tables and other processes.<br />- a compact flash disk for primary storage of software images, configuration files, and microcode.<br />- a hard disk for secondary storage. <br /><ul><li>The RE maintains the routing tables used by the router.
  41. 41. The RE has a direct 100-Mbps connection to the PFE.</li></li></ul><li>Routing Engine Architecture<br />
  42. 42. Switch Fabric Implementations<br /><ul><li>Maintains data plane connectivity among all of the PFEs.
  43. 43. Four operationally independent, identical and active switch planes.
  44. 44. The fifth plane that acting as a hot spare to provide redundancy. </li></li></ul><li>PFE & Switch Fabric Cell Distribution<br /><ul><li>Cell/Packet distribution similar to TCP/IP SAR of IP datagram packet.
  45. 45. Egress PFE drops packets if cells missing (assigned sequence #s).
  46. 46. Ingress PFE distribute packets on cell-by-cell basis - load balancing.</li></li></ul><li>Future work<br />Extensive research in RE and its inherent router OSdesign is needed.<br />Modern research work in the following areas:<br /><ul><li>Multi-threaded& multi-processor architecture for efficiency, reliability and user convenience.
  47. 47. Real-time CPU scheduling such as preemptive priority-based, preemptive kernel (for sensitive applications such as voice and video).
  48. 48. Virtual machines- can be incorporated into the design for efficient utilization of hardware (CPU, memory, I/O devices) and other computer resources.</li></li></ul><li>*Computers & Human*<br />"Computers are incredibly fast, accurate and stupid. Human beings are incredibly slow, inaccurate and brilliant. Together they are powerful beyond imagination" <br />Einstein<br />Q & A !!!<br />Thank you<br />

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