http://krimo666.mylivepage.com/L64105 MPEG-2Audio/Video DecoderTechnical ManualPreliminary              ®
http://krimo666.mylivepage.com/     This document contains proprietary information of LSI Logic Corporation. The     infor...
http://krimo666.mylivepage.com/            Contents            PrefaceChapter 1   Introduction            1.1   An L64105 ...
http://krimo666.mylivepage.com/            4.5    Video Interface Registers                       4-58            4.6    A...
http://krimo666.mylivepage.com/                  6.4.2  Detecting Potential Underflow Conditions                         in...
http://krimo666.mylivepage.com/            8.3   Video Decoder Pacing                             8-24                  8....
http://krimo666.mylivepage.com/             9.10   Pan and Scan Operation                           9-32                  ...
http://krimo666.mylivepage.com/             10.9  S/P DIF Interface                              10-29                   1...
http://krimo666.mylivepage.com/4.5    Register 4 (0x004)                                      4-84.6    Register 5 (0x005)...
http://krimo666.mylivepage.com/    4.32   Registers 99–101 (0x063–0x065) Audio           ES Channel Buffer Write Address [...
http://krimo666.mylivepage.com/4.56   Register 195 (0x0C3) Host SDRAM Write Data [7:0]   4-414.57   Registers 196–198 (0x0...
http://krimo666.mylivepage.com/      4.83    Register 243 and 244 (0x0F3 and 0x0F4)              Microcontroller PC [11:0]...
http://krimo666.mylivepage.com/4.111 Register 309 (0x135)                                   4-724.112 Register 336 (0x150)...
http://krimo666.mylivepage.com/      5.10   Block Move Flowchart                               5-19      6.1    Channel In...
http://krimo666.mylivepage.com/9.6     Horizontal Input Timing                                      9-119.7     Horizontal...
http://krimo666.mylivepage.com/         11.9    Asynchronous Channel Write Timing                     11-14         11.10 ...
http://krimo666.mylivepage.com/6.5    System Header Enable Bits                            6-116.6    Video PES Header Ena...
http://krimo666.mylivepage.com/        9.3     Force Video Background Selections                     9-12        9.4     O...
http://krimo666.mylivepage.com/               Preface               This book is the primary reference and Technical Manua...
http://krimo666.mylivepage.com/                  ♦ Chapter 5, Host Interface describes the host interface to the L64105   ...
http://krimo666.mylivepage.com/                 1.5 Mbit/s (MPEG-1), International Standard. ISO/IEC Copyright Office,     ...
http://krimo666.mylivepage.com/            Chapter 1            Introduction            This chapter provides general over...
http://krimo666.mylivepage.com/Figure 1.1     A Typical L64105 Application                                                ...
http://krimo666.mylivepage.com/Figure 1.2    L64105 Decoder Block Diagram             L64105 Decoder                      ...
http://krimo666.mylivepage.com/      the L64105 address SDRAM as if it were 8-byte wide RAM. The address      converter ch...
http://krimo666.mylivepage.com/               The L64105 is an MPEG-2 Main Level, Main Profile decoder. It handles         ...
http://krimo666.mylivepage.com/1.3 Features               Video Decoder –               ♦ Fully compliant to Main Profile a...
http://krimo666.mylivepage.com/Audio Decoder –♦ Processes MPEG audio with support for Linear PCM data.♦ Decodes dual-chann...
http://krimo666.mylivepage.com/            Chapter 2            I/O Signal Descriptions            This chapter describes ...
http://krimo666.mylivepage.com/Figure 2.1   L64105 I/O Signals                BUSMODE                             PD[7:0] ...
http://krimo666.mylivepage.com/2.2 Host Interface             BUSMODE          Host Controller Select Pin                 ...
http://krimo666.mylivepage.com/                       WRITEn - Intel Mode                       The external host asserts ...
http://krimo666.mylivepage.com/                            unmasked interrupt condition has occurred in the chip.         ...
http://krimo666.mylivepage.com/      CH_DATA[7:0] Channel Data Bus                                    Input               ...
http://krimo666.mylivepage.com/2.4 Memory Interface            Important:   The length of all connections between the L641...
http://krimo666.mylivepage.com/             SWEn             SDRAM Write Enable                             Output        ...
http://krimo666.mylivepage.com/            HS                Horizontal Sync                                    Input     ...
http://krimo666.mylivepage.com/       BCLK             DAC Bit Clock                                    Output            ...
http://krimo666.mylivepage.com/            SPDIF_IN           External S/P DIF                                 Input      ...
http://krimo666.mylivepage.com/       SYSCLK           Device Clock                                       Input           ...
http://krimo666.mylivepage.com/           Chapter 3           Register Summary           Communication with the L64105 Dec...
http://krimo666.mylivepage.com/Table 3.2       Host Interface Registers                                   Default Addr    ...
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Manual L64105 Mpeg2 Av Decoder

  1. 1. http://krimo666.mylivepage.com/L64105 MPEG-2Audio/Video DecoderTechnical ManualPreliminary ®
  2. 2. http://krimo666.mylivepage.com/ This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. Document DB14-000041-00, First Edition (July 1998) This document describes revision A of LSI Logic Corporation’s L64105 MPEG-2 Audio/Video Decoder and will remain the official reference source for all revisions/releases of this product until rescinded by an update. To receive product literature, call us at 1.800.574.4286 (U.S. and Canada); +32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe) and ask for Department JDS; or visit us at http://www.lsilogic.com. LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. In particular, supply of the LSI Logic IC L64105 does not convey a license or imply a right under certain patents and/or other industrial or intellectual property rights claimed by IRT, CCETT and Philips, to use this IC in any ready-to-use electronic product. The purchaser is hereby notified that Philips, CCETT and IRT are of the opinion that a generally available patent license for such use is required from them. No warranty or indemnity of any sort is provided by LSI Logic regarding patent infringement. Copyright © 1997, 1998 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT The LSI Logic logo design and G10 are registered trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies.ii
  3. 3. http://krimo666.mylivepage.com/ Contents PrefaceChapter 1 Introduction 1.1 An L64105 Application 1-1 1.2 L64105 Overview 1-2 1.2.1 Memory Utilization 1-5 1.2.2 Error Concealment 1-5 1.3 Features 1-6Chapter 2 I/O Signal Descriptions 2.1 Signals Organization 2-1 2.2 Host Interface 2-3 2.3 Channel Interface 2-5 2.4 Memory Interface 2-7 2.5 Video Interface 2-8 2.6 Audio Interface 2-9 2.7 Miscellaneous and Test Interfaces 2-11Chapter 3 Register Summary 3.1 Summary by Register 3-1 3.2 Alphabetical Listing 3-30Chapter 4 Register Descriptions 4.1 Host Interface Registers 4-2 4.2 Video Decoder Registers 4-17 4.3 Memory Interface Registers 4-38 4.4 Microcontroller Registers 4-48 Contents iii
  4. 4. http://krimo666.mylivepage.com/ 4.5 Video Interface Registers 4-58 4.6 Audio Decoder Registers 4-72 4.7 RAM Test Registers 4-91Chapter 5 Host Interface 5.1 Overview 5-1 5.2 Interface Signals 5-2 5.3 Register Access and Functions 5-5 5.3.1 General Functions 5-5 5.3.2 SCR Registers 5-6 5.3.3 Interrupt Registers 5-9 5.4 SDRAM Access 5-10 5.4.1 Host Reads/Writes 5-10 5.4.2 Host DMA SDRAM Transfers 5-14 5.4.3 SDRAM Block Move 5-18Chapter 6 Channel Interface 6.1 Overview 6-1 6.2 Interface Signals Operation 6-3 6.2.1 Asynchronous Mode 6-4 6.2.2 Synchronous VALIDn Inputs 6-5 6.2.3 Synchronous A/VREQn Outputs 6-7 6.2.4 Channel Bypass Mode 6-8 6.2.5 Channel Pause 6-8 6.3 Preparser 6-9 6.3.1 Host Selection of Streams and Headers 6-9 6.3.2 Elementary Streams 6-12 6.3.3 PES Packet Structure 6-14 6.3.4 Preparsing an MPEG-1 System Stream 6-16 6.3.5 Preparsing a Program Stream 6-18 6.3.6 Error Handling in Program Streams 6-21 6.3.7 Preparsing A/V PES Packets from a Transport Stream 6-24 6.3.8 Error Handling in A/V PES Mode 6-25 6.4 Channel Buffer Controller 6-27 6.4.1 Buffer Reset 6-28iv Contents
  5. 5. http://krimo666.mylivepage.com/ 6.4.2 Detecting Potential Underflow Conditions in the Video Channel 6-29 6.5 Summary 6-30Chapter 7 Memory Interface 7.1 Overview 7-1 7.2 SDRAM Configurations 7-2 7.3 SDRAM Timing and Modes 7-3 7.4 SDRAM Refresh and Arbitration 7-5 7.5 Memory Channel Buffer Allocation 7-6 7.6 Memory Frame Store Allocation 7-9 7.6.1 Luma Store 7-9 7.6.2 Chroma Store 7-9 7.6.3 Normal Mode 7-10 7.6.4 Reduced Memory Mode (RMM) 7-11 7.7 Summary 7-12Chapter 8 Video Decoder Module 8.1 Overview 8-1 8.2 Postparser Operation 8-4 8.2.1 Sequence Header 8-4 8.2.2 Sequence Extension 8-6 8.2.3 Sequence Display Extension 8-7 8.2.4 Group of Pictures Header 8-8 8.2.5 Picture Header 8-9 8.2.6 Picture Coding Extension 8-11 8.2.7 Quant Matrix Extension 8-13 8.2.8 Host Access of Q Table Entries 8-14 8.2.9 Picture Display Extension 8-15 8.2.10 Copyright Extension 8-17 8.2.11 User Data 8-18 8.2.12 Picture Data 8-18 8.2.13 Unsupported Syntax 8-18 8.2.14 Auxiliary Data FIFO Operation 8-19 8.2.15 User Data FIFO Operation 8-21 Contents v
  6. 6. http://krimo666.mylivepage.com/ 8.3 Video Decoder Pacing 8-24 8.3.1 Channel Start/Reset and Status Bits 8-25 8.3.2 Video Decoder Start/Stop 8-26 8.4 Frame Store Modes 8-30 8.4.1 Normal (3-Frame Store) Mode 8-30 8.4.2 Reduced Memory Mode 8-32 8.4.3 Two-Frame Store Mode 8-34 8.4.4 Decode and Display Frame Store Status Indicators 8-34 8.5 Trick Modes 8-35 8.5.1 Skip Frame 8-35 8.5.2 Repeat Frame 8-38 8.5.3 Channel Buffer Underflow Panic Repeat 8-40 8.5.4 Rip Forward Mode 8-40 8.5.5 Force Broken Link 8-43 8.5.6 Search for Next GOP/Seq Command 8-43 8.5.7 Reconstruction Force Rate Control 8-43 8.5.8 Sequence End Processing 8-46 8.6 Error Handling and Concealment 8-48 8.6.1 Error Conditions Detected 8-49 8.6.2 Recovery Mechanisms 8-49Chapter 9 Video Interface 9.1 Overview 9-2 9.2 Television Standard Select 9-4 9.3 Display Areas 9-5 9.3.1 Vertical Timing 9-7 9.3.2 Horizontal Timing 9-10 9.4 Video Background Modes 9-12 9.5 Still Image Display 9-13 9.6 Display Modes and Vertical Filtering 9-16 9.7 Reduced Memory Mode 9-19 9.8 Horizontal Postprocessing Filters 9-20 9.9 On-Screen Display 9-23 9.9.1 OSD Modes 9-24 9.9.2 Internal OSD 9-24 9.9.3 External OSD 9-31vi Contents
  7. 7. http://krimo666.mylivepage.com/ 9.10 Pan and Scan Operation 9-32 9.10.1 Host Controlled Pan and Scan 9-33 9.10.2 Bitstream Controlled Pan and Scan 9-35 9.10.3 Vertical Pan and Scan 9-35 9.11 Display Freeze 9-36 9.12 Pulldown Operation 9-38 9.13 Video Output Format and Timing 9-39 9.14 Display Controller Interrupts 9-40Chapter 10 Audio Decoder Module 10.1 Features 10-1 10.2 Audio Decoder Overview 10-2 10.3 Decoding Flow Control 10-6 10.3.1 Audio Decoder Play Mode 10-6 10.3.2 Audio Decoder Start/Stop 10-7 10.3.3 Audio Formatter Play Mode 10-8 10.3.4 Audio Formatter Start/Stop 10-8 10.3.5 Autostart 10-9 10.4 MPEG Audio Decoder 10-10 10.4.1 MPEG Audio Syntax 10-10 10.4.2 MPEG Audio Decoding 10-12 10.5 Linear PCM Audio Decoder 10-14 10.5.1 Packet Header Syntax 10-14 10.5.2 Synchronization 10-16 10.5.3 Other Host Controls and Status 10-18 10.5.4 Sample Decimation for S/P DIF 10-18 10.6 MPEG Formatter 10-19 10.6.1 Number of IEC958 Frames when Formatting MPEG Data 10-21 10.6.2 Pd Field 10-21 10.6.3 Pause Burst 10-22 10.6.4 Synchronization 10-24 10.6.5 Error Conditions 10-24 10.7 PCM FIFO Mode 10-26 10.8 DAC Interface 10-27 Contents vii
  8. 8. http://krimo666.mylivepage.com/ 10.9 S/P DIF Interface 10-29 10.9.1 Biphase Mark Coding 10-30 10.9.2 IEC958 Syntax 10-30 10.9.3 IEC958 Channel Status 10-32 10.10 Clock Divider 10-32Chapter 11 Specifications 11.1 Electrical Requirements 11-1 11.2 AC Timing 11-4 11.3 Pinouts and Packaging 11-18Appendix A Video/Audio Compression and Decompression Concepts A.1 Video Compression and Decompression Concepts A-1 A.1.1 Video Encoding A-2 A.1.2 Bitstream Syntax A-5 A.1.3 Video Decoding A-7 A.2 Audio Compression and Decompression Concepts A-7 A.2.1 MPEG Audio Encoding A-8 A.2.2 Audio Decoding A-11Appendix B Glossary of Terms and Abbreviations Index Customer FeedbackFigures 1.1 A Typical L64105 Application 1-2 1.2 L64105 Decoder Block Diagram 1-3 2.1 L64105 I/O Signals 2-2 2.2 PLLVDD Decoupling Circuit 2-11 4.1 Register 0 (0x000) 4-2 4.2 Register 1 (0x001) 4-3 4.3 Register 2 (0x002) 4-5 4.4 Register 3 (0x003) 4-7viii Contents
  9. 9. http://krimo666.mylivepage.com/4.5 Register 4 (0x004) 4-84.6 Register 5 (0x005) 4-94.7 Register 6 (0x006) 4-104.8 Register 7 (0x007) 4-114.9 Registers 9–12 (0x009–0x00C) SCR Value [31:0] 4-134.10 Registers 13–16 (0x00D–0x010) SCR Compare/Capture [31:0] 4-134.11 Register 17 (0x011) 4-144.12 Register 18 (0x012) 4-154.13 Register 19 (0x013) 4-154.14 Registers 20–23 (0x014–0x017) SCR Compare Audio [31:0] 4-164.15 Register 28 (0x01C) Video Channel Bypass Data [7:0] 4-164.16 Register 29 (0x01D) Audio Channel Bypass Data [7:0] 4-174.17 Register 64 (0x040) 4-174.18 Register 65 (0x41) 4-184.19 Register 66 (0x042) User Data FIFO Output [7:0] 4-194.20 Register 67 (0x043) Aux Data FIFO Output [7:0] 4-194.21 Register 68 (0x044) 4-204.22 Register 69 (0x045) 4-214.23 Registers 72 and 73 (0x048 and 0x049) Video ES Channel Buffer Start Address [13:0] 4-224.24 Registers 74 and 75 (0x04A and 0x04B) Video ES Channel Buffer End Address [13:0] 4-234.25 Registers 76 and 77 (0x04C and 0x04D) Audio ES Channel Buffer Start Address [13:0] 4-234.26 Registers 78 and 79 (0x04E and 0x04F) Audio ES Channel Buffer End Address [13:0] 4-244.27 Registers 80 and 81 (0x050 and 0x051) Video PES Header Channel Buffer Start Address [13:0] 4-244.28 Registers 82 and 83 (0x052 and 0x053) Video PES Header Channel Buffer End Address [13:0] 4-244.29 Registers 88 and 89 (0x058 and 0x059) Audio PES Header/System Channel Buffer Start Address [13:0] 4-254.30 Registers 90 and 91 (0x05A and 0x05B) Audio PES Header/System Channel Buffer End Address [13:0] 4-254.31 Registers 96–98 (0x060–0x062) Video ES Channel Buffer Write Address [19:0] 4-26Contents ix
  10. 10. http://krimo666.mylivepage.com/ 4.32 Registers 99–101 (0x063–0x065) Audio ES Channel Buffer Write Address [19:0] 4-26 4.33 Registers 102–104 (0x066–0x068) Video PES Header Channel Buffer Write Address [19:0] 4-27 4.34 Registers 108–110 (0x06C–0x06E) Video ES Channel Buffer Read Address [19:0] 4-27 4.35 Registers 108–110 (0x06C–0x06E) Video ES Channel Buffer Compare DTS Address [18:0] 4-28 4.36 Registers 111–113 (0x06F–0x071) Audio ES Channel Buffer Read Address [19:0] 4-28 4.37 Registers 111–113 (0x06F–0x071) Audio ES Channel Buffer Compare DTS Address [18:0] 4-29 4.38 Registers 114–116 (0x072–0x074) Audio PES Header/System Channel Buffer Write Address [19:0] 4-29 4.39 Registers 120–122 (0x078–0x07A) S/P DIF Channel Buffer Read Address [19:0] 4-30 4.40 Register 124 (0x07C) 4-30 4.41 Registers 128–130 (0x080–0x082) Picture Start Code Read Address [19:0] 4-31 4.42 Registers 131–133 (0x083–0x085) Audio Sync Code Read Address [19:0] 4-31 4.43 Registers 134–136 (0x086–0x088) Video ES Channel Buffer Numitems [18:0] 4-32 4.44 Registers 134–136 (0x086–0x088) Video Numitems/Pics in Channel Compare Panic [18:0] 4-32 4.45 Registers 137–139 (0x089–0x08B) Audio ES Channel Buffer Numitems [18:0] 4-33 4.46 Registers 140–142 (0x08C–0x08E) S/P DIF Channel Buffer Numitems [18:0] 4-33 4.47 Register 143 (0x08F) 4-34 4.48 Register 144 (0x090) 4-35 4.49 Register 145 (0x091) 4-35 4.50 Register 147 (0x093) 4-36 4.51 Register 149 (0x094) 4-37 4.52 Registers 150 and 151 (0x096 and 0x097) Pictures in Video ES Channel Buffer Counter [15:0] 4-38 4.53 Register 192 (0x0C0) 4-38 4.54 Register 193 (0x0C1) 4-39 4.55 Register 194 (0x0C2) Host SDRAM Read Data [7:0] 4-41x Contents
  11. 11. http://krimo666.mylivepage.com/4.56 Register 195 (0x0C3) Host SDRAM Write Data [7:0] 4-414.57 Registers 196–198 (0x0C4–0x0C6) Host SDRAM Target Address [18:0] 4-424.58 Registers 199–201 (0x0C7–0x0C9) Host SDRAM Source Address [18:0] 4-424.59 Registers 202 and 203 (0x0CA and 0x0CB) Block Transfer Count [15:0] 4-434.60 Register 204 (0x0CC) 4-434.61 Register 205 (0x0CD) 4-444.62 Register 206 (0x0CE) 4-454.63 Registers 207–212 (0x0CF–0x0D4) 4-454.64 Registers 213–215 (0xD5–0x0D7) DMA SDRAM Target Address [18:0] 4-464.65 Registers 216–218 (0xD8–0x0DA) DMA SDRAM Source Address [18:0] 4-464.66 Register 219 (0x0DB) DMA SDRAM Read Data [7:0] 4-474.67 Register 220 (0x0DC) DMA SDRAM Write Data [7:0] 4-474.68 Register 221 (0x0DD) 4-474.69 Registers 222 and 223 (0x0DE and 0x0DF) VCO Test Low Freq [15:8] 4-474.70 Registers 224 and 225 (0x0E0 and 0x0E1) Anchor Luma Frame Store 1 Base Address [15:0] 4-484.71 Registers 226 and 227 (0x0E2 and 0x0E3) Anchor Chroma Frame Store 1 Base Address [15:0] 4-484.72 Registers 228 and 229 (0x0E4 and 0x0E5) Anchor Luma Frame Store 2 Base Address [15:0] 4-484.73 Registers 230 and 231 (0x0E6 and 0x0E7) Anchor Chroma Frame Store 2 Base Address [15:0] 4-494.74 Registers 232 and 233 (0x0E8 and 0x0E9) B Luma Frame Store Base Address [15:0] 4-494.75 Registers 234 and 235 (0x0EA and 0x0EB) B Chroma Frame Store Base Address [15:0] 4-494.76 Register 236 (0x0EC) 4-504.77 Register 237 (0x0ED) 4-514.78 Register 238 (0x0EE) 4-524.79 Register 239 (0x0EF) 4-544.80 Register 240 (0x0F0) 4-564.81 Register 241 (0x0F1) 4-564.82 Register 242 (0x0F2) Q Table Entry [7:0] 4-57Contents xi
  12. 12. http://krimo666.mylivepage.com/ 4.83 Register 243 and 244 (0x0F3 and 0x0F4) Microcontroller PC [11:0] 4-57 4.84 Register 245 (0x0F5) Revision Number [7:0] 4-57 4.85 Register 246 (0x0F6) 4-57 4.86 Register 248 (0x0F8) Reduced Memory Mode (RMM) Bit 4-58 4.87 Register 265 (0x109) 4-58 4.88 Registers 266–268 (0x10A and 0x10C) Programmable Background Y/Cb/Cr [7:0] 4-60 4.89 Register 269 (0x10D) OSD Palette Write [7:0] 4-60 4.90 Registers 270–273 (0x10E–0x111) OSD Odd/Even Field Pointers [15:0] 4-61 4.91 Register 274 (0x112) 4-61 4.92 Register 275 (0x113) 4-62 4.93 Register 276 (0x114) 4-63 4.94 Register 277 (0x115) Horizontal Filter Scale [7:0] 4-64 4.95 Register 278 (0x116) 4-65 4.96 Register 279 (0x117) 4-65 4.97 Register 280 (0x118) Horizontal Pan and Scan Luma/Chroma Word Offset [7:0] 4-66 4.98 Register 281 (0x119) Vertical Pan and Scan Line Offset [7:0] 4-66 4.99 Register 282 (0x11A) 4-66 4.100 Register 283 (0x11B) 4-67 4.101 Register 284 (0x11C) 4-67 4.102 Registers 285–288 (0x11D–0x120) Display Override Luma/Chroma Frame Store Start Addresses [15:0] 4-68 4.103 Register 289 (0x121) 4-68 4.104 Register 290 (0x122) 4-69 4.105 Registers 297–299 (0x129–0x12B) Main Start/End Rows [10:0] 4-70 4.106 Registers 300–302 (0x12C–0x12E) Main Start/End Columns [10:0] 4-70 4.107 Register 303 (0x12F) 4-70 4.108 Register 304 (0x130) Vcode Even [7:0] 4-71 4.109 Register 305 (0x131) Fcode [7:0] 4-71 4.110 Registers 306–308 (0x132–0x134) SAV/EAV Start Columns [10:0] 4-72xii Contents
  13. 13. http://krimo666.mylivepage.com/4.111 Register 309 (0x135) 4-724.112 Register 336 (0x150) 4-724.113 Register 337 (0x151) 4-744.114 Register 338 (0x152) 4-764.115 Register 351 (0x15F) 4-774.116 Register 352 (0x160) 4-774.117 Register 353 (0x161) 4-774.118 Register 354 (0x162) 4-784.119 Register 355 (0x163) 4-794.120 Register 356 (0x164) 4-804.121 Register 357 (0x165) 4-814.122 Register 358 (0x166) 4-824.123 Register 359 (0x167) PCM FIFO Data In [7:0] 4-834.124 Register 360 (0x168) Linear PCM - dynscalehigh [7:0] 4-834.125 Register 361 (0x169) Linear PCM - dynscalelow [7:0] 4-834.126 Register 362 (0x16A) PCM Scale [7:0] 4-844.127 Register 363 (0x16B) 4-844.128 Register 364 (0x16C) 4-854.129 Register 365 (0x16D) 4-874.130 Register 366 (0x16E) 4-884.131 Register 367 (0x16F) Host Category [7:0] 4-894.132 Register 368 (0x170) 4-904.133 Registers 369 and 370 (0x171 and 0x172) Host Pd Value [15:0] 4-914.134 Registers 384 and 385 (0x180 and 0x181) Memory Test Address [11:0] 4-914.135 Register 386 (0x182) 4-914.136 Registers 387–392 (0x183–0x188) Memory Test Pass/Fail Status Bits 4-935.1 Host Interface Block Diagram 5-25.2 Motorola Mode Write Timing 5-35.3 Motorola Mode Read Timing 5-45.4 Intel Mode Write Timing 5-55.5 Intel Mode Read Timing 5-55.6 Operation of the SCR Counter 5-75.7 Interrupt Structure 5-95.8 Host Read/Write Flowchart 5-135.9 DMA SDRAM Read/Write Flowchart 5-17Contents xiii
  14. 14. http://krimo666.mylivepage.com/ 5.10 Block Move Flowchart 5-19 6.1 Channel Interface Block Diagram 6-3 6.2 Asynchronous Channel Interface Timing 6-4 6.3 xVALIDn Input Synchronization Circuits 6-6 6.4 Synchronous Valid Signals Timing 6-6 6.5 L64105 A/VREQn Circuits 6-7 6.6 Elementary Stream Buffering 6-13 6.7 PES Packet Structure 6-15 6.8 Preparsing an MPEG-1 System Stream 6-16 6.9 System PES Channel Buffer Map for MPEG-1 Streams 6-17 6.10 System Channel Buffer Map for Program Streams 6-19 6.11 Audio ES Channel Buffer Map for Linear PCM Audio 6-20 6.12 Audio ES Channel Buffer Map for MPEG Audio 6-21 6.13 Video ES Channel Buffer Map 6-21 6.14 Parsing an Audio/Video PES Transport Stream 6-24 6.15 MPEG-1/MPEG-2 Channel Interface Operation 6-30 6.16 A/V PES Mode Channel Interface Operation 6-31 7.1 Memory Interface Block Diagram 7-2 7.2 SDRAM Timing Requirements for Reads 7-4 7.3 SDRAM Timing Requirements for Writes 7-5 7.4 SDRAM Timing Requirements for Refresh 7-5 7.5 Luma Frame Store Organization 7-9 7.6 Chroma Frame Store Organization 7-10 8.1 Video Decoder Block Diagram 8-3 8.2 Time Line for Frame Picture 8-28 8.3 Time Line for Field Picture 8-29 8.4 Frame Store Organization in Normal Mode 8-31 8.5 Single Skip with and without Display Freeze 8-37 8.6 Frame Repeat Modes 8-39 8.7 Setting Up Rip Forward/Display Override Command 8-42 8.8 Automatic Rate Control 8-45 8.9 Using Force Rate Control in Rip Forward Mode 8-46 8.10 Example of Sequence End Processing 8-47 9.1 Video Interface Block Diagram 9-3 9.2 Display Areas Example 9-6 9.3 Vertical Timing Vcodes and Fcodes for NTSC 9-8 9.4 Vertical Timing Vcodes and Fcodes for PAL 9-9 9.5 Sync Input Timing 9-10xiv Contents
  15. 15. http://krimo666.mylivepage.com/9.6 Horizontal Input Timing 9-119.7 Horizontal Timing for 8-Bit Digital Transmission for NTSC 9-129.8 Luma and Chroma Frame Store Format 9-149.9 Frequency Response A 9-219.10 Impulse Response A 9-219.11 Frequency Response B 9-229.12 Impulse Response B 9-229.13 OSD Area Data Organization 9-259.14 OSD Header Control Fields 9-269.15 OSD Header Color Fields 9-279.16 OSD Storage Formats 9-299.17 Horizontal Pan and Scan Calculation 9-359.18 Freeze Operation Timing 9-379.19 Pulldown Operation Timing 9-399.20 Video and Control Output Timing 9-4010.1 L64105 Audio Decoder Block Diagram 10-410.2 MPEG Audio Bitstream Syntax 10-1110.3 MPEG Audio Decoding Flow 10-1310.4 Linear PCM Packet Syntax 10-1410.5 Linear PCM Audio Sample Syntax 10-1610.6 Linear PCM Output Ports 10-1910.7 Syntax of the MPEG Data in IEC958 Format 10-2010.8 Length of Burst Payload 10-2110.9 Inserting Pause Bursts in the MPEG Formatter Output 10-2310.10 DAC Output Mode: PCM Sample Precision = 16 Bit 10-2710.11 DAC Output Mode: PCM Sample Precision = 20 Bit 10-2810.12 DAC Output Mode: PCM Sample Precision = 24 Bit 10-2810.13 IEC958 Biphase Mark Representation 10-3010.14 IEC958 Syntax 10-3110.15 IEC958 Channel Status 10-3211.1 AC Test Load and Waveform for Standard Outputs 11-411.2 AC Test Load and Waveform for 3-State Outputs 11-511.3 SDRAM Read Cycle 11-711.4 SDRAM Write Cycle 11-811.5 Host Write Timing (Motorola Mode) 11-1011.6 Host Read Timing (Motorola Mode) 11-1111.7 Host Write Timing (Intel Mode) 11-1311.8 Host Read Timing (Intel Mode) 11-13Contents xv
  16. 16. http://krimo666.mylivepage.com/ 11.9 Asynchronous Channel Write Timing 11-14 11.10 Synchronous AVALIDn/VVALIDn Signals Timing 11-15 11.11 Reset Timing 11-15 11.12 Video Interface Timing 11-16 11.13 Serial PCM Data Out Timing 11-17 11.14 A_ACLK Timing 11-17 11.15 PREQn Timing 11-18 11.16 160-Pin Package Pinout 11-25 11.17 160-Pin PQFP (PZ) Mechanical Drawing (Sheet 1 of 2) 11-26 A.1 MPEG Macroblock Structure A-3 A.2 Typical Sequence of Pictures in Display Order A-6 A.3 Typical Sequence of Pictures in Bitstream Order A-6 A.4 Audio Encoding Process (Simplified) A-8 A.5 ISO System Stream A-9 A.6 MPEG Audio Packet Structure A-9Tables 3.1 L64105 Register Groupings 3-1 3.2 Host Interface Registers 3-2 3.3 Video Decoder Registers 3-7 3.4 Memory Interface Registers 3-14 3.5 Microcontroller Registers 3-17 3.6 Video Interface Registers 3-20 3.7 Audio Decoder Registers 3-24 3.8 RAM Test Registers 3-27 4.1 Display Mode Selection Table 4-64 4.2 MPEG Bitrate Index Table 4-73 4.3 Audio Decoder Modes 4-81 4.4 ACLK Divider Select [3:0] Code Definitions 4-86 5.1 Host Interface Signals 5-2 5.2 SCR Compare/Capture Mode Bits 5-6 5.3 DMA Mode Bits 5-14 6.1 Levels of Hierarchy in MPEG-1 and MPEG-2 System Syntax 6-2 6.2 Video Stream Select Enable Bits 6-9 6.3 Audio Stream Select Enable Bits 6-10 6.4 Pack Header Enable Bits 6-11xvi Contents
  17. 17. http://krimo666.mylivepage.com/6.5 System Header Enable Bits 6-116.6 Video PES Header Enable Bits 6-126.7 Audio PES Header Enable Bits 6-126.8 Buffer Start and End Address Registers for ES Mode 6-136.9 Buffer Write and Read Pointer Registers in ES Mode 6-146.10 Number of Items in Buffers in ES Mode 6-146.11 SDRAM Addresses - Audio PES Header/System Channel Buffer 6-186.12 Video PES Header Channel Buffer Registers 6-256.13 Compare DTS Register Bits and Fields 6-286.14 Video Channel Underflow Control Registers 6-297.1 NEC’s 16 Mbit Synchronous DRAM (Burst Length = 2) 7-47.2 Example NTSC SDRAM Allocation 7-67.3 Channel Buffer Architectures 7-87.4 Example NTSC SDRAM Allocation with Frame Store (720 x 480) 7-128.1 Sequence Header Processing 8-48.2 Sequence Extension Processing 8-68.3 Sequence Display Extension Processing 8-78.4 Group Of Pictures Header Processing 8-88.5 Picture Header Processing 8-98.6 Picture Coding Extension Processing 8-118.7 Quant Matrix Extension Processing 8-138.8 Picture Display Extension Processing 8-158.9 Number of Frame Center Offsets 8-168.10 Copyright Extension Processing 8-178.11 All User Data Processing 8-188.12 Aux Data FIFO Registers 8-198.13 Aux Data FIFO Status 8-208.14 Auxiliary Data Layer ID Assignments 8-218.15 User Data FIFO Registers 8-228.16 User Data FIFO Status 8-228.17 User Data Layer ID Assignments 8-248.18 Frame Store Base Address Registers 8-328.19 Current Decode/Display Frame Bits Coding 8-348.20 Video Skip Frame Modes 8-359.1 Television Standard Select Field 9-49.2 Television Standard Select Default Values 9-5Contents xvii
  18. 18. http://krimo666.mylivepage.com/ 9.3 Force Video Background Selections 9-12 9.4 Override Display Registers 9-14 9.5 Display Mode Selection Table 9-17 9.6 Raster Mapper Increment Value by Source Resolution 9-23 9.7 OSD Modes 9-24 9.8 High Color Modes 9-26 9.9 Host Controlled Pan and Scan Registers 9-33 9.10 Freeze Modes 9-36 10.1 Audio Decoder Modes 10-3 10.2 Audio Autostart Registers 10-9 10.3 Valid Linear PCM Stream Permutations 10-15 10.4 MPEG Formatter Data Burst Preamble Syntax 10-20 10.5 IEC958 Frame Sizes Supported in MPEG Audio Formatter 10-21 10.6 Pd Selection 10-22 10.7 MPEG Formatter Pause Burst Syntax 10-23 10.8 MPEG Audio Formatter Error Handling 10-25 10.9 PCM FIFO Mode Registers 10-26 10.10 IEC958 Subframe Preambles 10-31 10.11 ACLK Divider Select [3:0] Code Definitions 10-34 11.1 Absolute Maximum Ratings 11-2 11.2 Recommended Operating Conditions 11-2 11.3 Capacitance 11-2 11.4 DC Characteristics 11-3 11.5 SDRAM Interface AC Timing 11-6 11.6 Host Interface AC Timing (Motorola Mode) 11-9 11.7 Host Interface AC Timing (Intel Mode) 11-12 11.8 Asynchronous Channel Write AC Timing 11-14 11.9 Synchronous AVALIDn/VVALIDn Signals AC Timing 11-14 11.10 Video Interface AC Timing 11-16 11.11 Audio Interface AC Timing 11-17 11.12 Alphabetical Pin Summary 11-18 A.1 MPEG Compressed Bitstream Syntax A-5xviii Contents
  19. 19. http://krimo666.mylivepage.com/ Preface This book is the primary reference and Technical Manual for the L64105 MPEG-2 Audio/Video Decoder. It contains functional descriptions, I/O signal and register descriptions, and includes complete physical and electrical specifications for the L64105.Audience This document assumes that you have some familiarity with ISO/IEC 13818, Generic Coding of Moving Pictures and Associated Audio (MPEG-2), microprocessors, and related support devices. The people who benefit from this book are: ♦ Engineers and managers who are evaluating the L64105 for possible use in a system ♦ Engineers who are designing the L64105 into a systemOrganization This document has the following chapters and appendixes: ♦ Chapter 1, Introduction includes an overview of the L64105 Decoder and lists its features. ♦ Chapter 2, I/O Signal Descriptions describes the input/output signals of the L64105. ♦ Chapter 3, Register Summary summarizes all of the registers of the L64105 in tabular form with page references to their descriptions in Chapter 4. ♦ Chapter 4, Register Descriptions identifies and describes all of the register bits and fields of the L64105 accessible from the host processor. Preface xix
  20. 20. http://krimo666.mylivepage.com/ ♦ Chapter 5, Host Interface describes the host interface to the L64105 and to external SDRAM connected to the L64105. ♦ Chapter 6, Channel Interface describes the processing of the audio/video bitstream as it comes into the L64105 and the various methods which the L64105 uses to handle and recover from input stream errors. ♦ Chapter 7, Memory Interface describes the SDRAM configurations required by the L64105 and its interface to those memories. ♦ Chapter 8, Video Decoder Module describes how the video decoder portion of the L64105 supports MPEG-2 Main Profile and Main Level decoding and MPEG-1 Simple Profile and Main Level decoding. ♦ Chapter 9, Video Interface describes how video is displayed from decoded frame stores. Also describes the features and operation of the Display Controller and how to program it for proper operation. Includes an overview of the vertical and horizontal post-processing filters. ♦ Chapter 10, Audio Decoder Module describes how the L64105 processes Linear PCM and MPEG (MUSICAM) input audio streams. ♦ Chapter 11, Specifications includes the electrical requirements for, AC timing characteristics of, and a pin summary for the L64105. Also contains the pin listing and package outline drawing for the 160-pin PQFP. ♦ Appendix A, Video/Audio Compression and Decompression Concepts ♦ Appendix B, Glossary of Terms and AbbreviationsRelated Publications L64108 MPEG-2 Transport with Embedded MIPS CPU (CW4001) and Control Chip Technical Manual, LSI Logic Corporation, DB14-000039-00. ISO/IEC 13818, Generic Coding of Moving Pictures and Associated Audio (MPEG-2), International Standard. ISO/IEC Copyright Office, Case Postal 56, CH1211 Genève 20, Switzerland. ISO/IEC 11172 (1993), Information Technology—Coding of Moving Picture and Associated Audio for Digital Storage Media at up to aboutxx Preface
  21. 21. http://krimo666.mylivepage.com/ 1.5 Mbit/s (MPEG-1), International Standard. ISO/IEC Copyright Office, Case Postal 56, CH1211 Genève 20, Switzerland. ITU-R BT.601-5 (10/95), Studio Encoding Parameters of Digital Television for Standard 4:3 and Wide-screen 16:9 Aspect Ratios, http://www.itu.ch/publications/itu-r/iturbt.htm. ITU-R BT.656-3 (10/95), Interface for Digital Component Video Signals in 525-line and 625-line Television Systems Operating at the 4:2:2 Level of Recommendation ITU-R BT.601 (Part A), http://www.itu.ch/publications/itu-r/iturbt.htm.Conventions Used in This Manual Unless otherwise specified, MPEG refers to the MPEG-2 standard. MSB indicates the most-significant bit or byte. LSB indicates the least- significant bit or byte. If bit or byte is not obvious in the context, the term is spelled out. The first time a word or phrase is defined in this manual, it is italicized. The word set means to change a bit to the logic 1 state. The word clear means to change a bit to the logic 0 state. The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Signals that are active LOW end in an “n.” Hexadecimal numbers are indicated by the prefix “0x” before the number—for example, 0x32CF. Binary numbers are indicated by the prefix “0b” before the number—for example, 0b0011.0010.1100.1111. Preface xxi
  22. 22. http://krimo666.mylivepage.com/ Chapter 1 Introduction This chapter provides general overview information on the L64105 MPEG-2 Audio/Video Decoder chip. The chapter contains the following sections: ♦ Section 1.1, “An L64105 Application,” page 1-1 ♦ Section 1.2, “L64105 Overview,” page 1-2 ♦ Section 1.3, “Features,” page 1-61.1 An L64105 Application Figure 1.1 illustrates the L64105 in a typical set top box application. The L64105 is specifically designed for use in digital audio and video MPEG-2 decoding systems based on the MPEG-2 algorithm. The device may be considered a “black box” that receives coded audio and video data and produces decoded audio and video data streams. LSI Logic has optimized the L64105 input/output interfaces for low-cost integration into embedded applications. The L64105 is a member of a family of pin and software compatible, advanced, MPEG-2 A/V decoders. The L64020 DVD Audio/Video Decoder adds DVD and Dolby Digital audio decoding features. 1-1
  23. 23. http://krimo666.mylivepage.com/Figure 1.1 A Typical L64105 Application L64X08 EBUS L64X08 L64105 NTSC/PALSatellite in L647X4 Baseband Integrated MPEG-2 Encoder QPSK Video X-PORT A/V Demod CPU Decoder Audio Stereo DACs Audio OrCable in L64768 S/P DIF QAM 4 Mbit 16 Mbit Optional Demod DRAM SDRAM 16 Mbit SDRAM The L64105 accepts an 8-bit, parallel channel input from a transport demultiplexer and, with interaction of a host microcontroller, decompresses and decodes the channel information into separate, serial video and audio streams. The L64105 handles NTSC and PAL formats and provides a Sony/Philips Digital Interface (S/P DIF) formatted output stream.1.2 L64105 Overview Figure 1.2 shows a block diagram of the L64105. Its major blocks include the: ♦ Host Interface ♦ Channel Interface ♦ Memory Interface ♦ Video Decoder ♦ Video Interface ♦ Audio Decoder The Host Interface includes 512, 8-bit registers (some not used), read and write FIFOs, and byte enable logic. The host and L64105 communicate with each other exclusively through the registers. An external interrupt signal from the L64105 alerts the host about internal events, such as picture start code detection. Separate I/O signals are used for handshaking. The L64105 can interface with either an Intel or Motorola type processor by tying an external pin high or low.1-2 Introduction
  24. 24. http://krimo666.mylivepage.com/Figure 1.2 L64105 Decoder Block Diagram L64105 Decoder Video to CH_DATA[7:0] NTSC/PAL Encoder Channel Video Video Interface Microcontroller Decoder Interface DCK (£ 9 MHz) I/O Control Data andAddress Buses Host 64-bit Data Bus Interface Status and Audio Control Address Bus and Clocks Memory to DACSYSCLK Interface Audio Oversampling(27 MHz) Decoder Clock In S/P DIF Out SDRAM Buffers and Frame Stores The read and write FIFOs are used to give the host access to the external SDRAM. The read/write paths are still through registers. The interface supports direct read/write, DMA transfers using an external DMA controller, and block moves within SDRAM. The byte enable logic converts host byte writes to 8-byte words for the write FIFO and 64-bit internal bus and vice versa. The byte enable logic also performs byte switching for little endian hosts. The Channel Interface accepts byte-wide MPEG streams and a clock. The interface synchronizes to and preparses the incoming stream by stripping system headers and storing them in a dedicated buffer area in SDRAM. The interface also separates the audio and video streams and stores them in dedicated buffer areas in SDRAM. A buffer controller maintains the read and write pointers for the dedicated buffers. The Memory Interface includes byte enable logic and an address converter. The recommended SDRAM is 16 bits wide, so the byte enable logic performs the conversion between the SDRAM bus and the 8-byte wide internal bus of the L64105. The host and internal microcontroller of L64105 Overview 1-3
  25. 25. http://krimo666.mylivepage.com/ the L64105 address SDRAM as if it were 8-byte wide RAM. The address converter changes these addresses to chip selects, bank selects, and column and row addresses for the SDRAM. The Video Decoder reads the MPEG video elementary stream from the SDRAM buffer, performs postparsing on it, decompresses it, decodes it, and stores it back in SDRAM. The postparser strips off all header information and stores it in internal memory for use in the decoding process. The postparser also strips auxiliary and user data from the stream and stores it in FIFOs that can be read through registers by the host. The decompressed and decoded video is stored back in SDRAM in frame form. The Video Interface reads the video frames from frame stores in SDRAM, synchronizes them to the vertical and horizontal sync signals from the NTSC/PAL Encoder, and mixes in On-Screen Display (OSD) information. The interface performs letterboxing, 3:2 pulldown, and pan and scan. It also handles trick modes such as pause, slow play, fast forward, etc. The Audio Decoder contains an MPEG (Musicam) Decoder, Linear PCM Decoder, MPEG Formatter, Audio DAC Interface, and an S/P DIF (IEC958) Interface. The decoders decompress and decode the audio stream. The decoder outputs can be steered to the DAC or S/P DIF Interface. The formatter converts the encoded and compressed streams to S/P DIF format for the S/P DIF Interface. The host controls the mode of the Audio Decoder; that is, it determines which decoder runs and where its output goes, and which formatter runs. The host can also place the Audio Decoder in the bypass mode and connect inputs from another device directly to the L64105 audio outputs. The microcontroller is shown on the block diagram since it controls most of the processes of the L64105.1-4 Introduction
  26. 26. http://krimo666.mylivepage.com/ The L64105 is an MPEG-2 Main Level, Main Profile decoder. It handles image sizes up to 720 x 480 pixels with a frame rate of 30 fps for NTSC and up to 720 x 576 pixels at 25 fps for PAL. It can also decode MPEG-1 sequences. The coded data channel may have a sustained bit rate of up to 20 Mbits/second. As the resolution decreases, the amount and bandwidth of SDRAM memory required for frame stores also decreases.1.2.1 Memory Utilization The L64105 supports direct connection to commercial SDRAM for use as frame stores, channel buffers, and overlay memory. The L64105 uses frame stores for frame reconstruction and display, separate video and audio channel buffers for rate matching, and zero or more regions for graphical overlay. This storage is combined into a single contiguous memory space accessed over a 16-bit wide bus. In most cases this will be one 1 M x 16-bit SDRAM, for a total memory space of 2 Mbytes. The interface between the L64105 and SDRAM requires no external components. The L64105 pinout allows the connection to SDRAM to be made on a single PCB layer. During normal operation, the L64105 exclusively controls the SDRAM frame stores. However, it is possible to access the SDRAM through the host port on the L64105 for test verification and for access to the overlay stores and channel information.1.2.2 Error Concealment The L64105 detects data in the bitstream that does not meet MPEG-2 syntax or grammar rules and can flag the data for exception processing. Hardware error handling is limited to error masking and the application of concealment vectors in video. Audio error concealment is limited to muting on errors and searching for error-free frames. The L64105 flags gross errors in the bitstream due to channel buffer overrun or underrun or to nonconformance in the bitstream. The L64105 flags the errors so that they may be masked in the video or the audio output. The host microcontroller may be programmed to execute mechanisms to recover from gross errors. L64105 Overview 1-5
  27. 27. http://krimo666.mylivepage.com/1.3 Features Video Decoder – ♦ Fully compliant to Main Profile at Main Level of the MPEG-2 video standard, ISO 13818-2. ♦ Decodes an MPEG-2 bitstream, including MPEG-2 Program stream, with private stream support. ♦ Decodes an MPEG-1 bitstream as defined in ISO IS 11172, including the MPEG-1 system layer. ♦ Operates at image sizes up to ITU-R BT.601 resolution (720 x 480 pixels @ 30 fps for NTSC and 720 x 576 @ 25 fps for PAL). ♦ Up to 20 Mbps sustained input channel data rate for program streams and A/V PES streams from a transport demultiplexer. ♦ 8-bit parallel dedicated input channel interface. ♦ 8-bit luma/chroma output. ♦ Complete on-chip channel buffer controller and display buffer controls. ♦ Error concealment maintains display of images during channel errors. Video Interface – ♦ Integrates a flexible 256-color, On-Screen Display (OSD) controller. ♦ Allows connection to an external OSD generator. ♦ Programmable display management. ♦ Slave video timing operation. ♦ Integrates postprocessing filters for image resizing (horizontal and vertical). ♦ Integrates vertical filter for letterbox format display. ♦ Implements 3:2 pulldown. ♦ Supports pan and scan with 1/8-pixel accuracy. ♦ Supports 4:2:0 to 4:2:2 sampling filters.1-6 Introduction
  28. 28. http://krimo666.mylivepage.com/Audio Decoder –♦ Processes MPEG audio with support for Linear PCM data.♦ Decodes dual-channel MPEG audio, Layer I and II ISO 13818-2, supporting bit rates of 8 Kbps to 448 Kbps and sampling rates of 16, 22.05, 24, 32, 44.1, and 48 kHz.♦ Supports Linear PCM streams with sample rates of 48 kHz and 96 kHz at 24-bit resolution.♦ IEC958 output interface for audio data bitstreams.♦ Mute on error for concealment.♦ Provides an audio “Bypass” mode for interface to a CD audio decoder.System –♦ Programmable preparser accepts PES, ES, and PS streams.♦ Direct connection to commodity SDRAM.♦ Input/output interfaces are optimized for glueless integration into consumer video systems.♦ Operates from a single 27-MHz clock with an additional audio sample clock input.♦ Total external memory required for audio and video decoding is 16-Mbit SDRAM for ITU-R BT.601-5 resolution.♦ Interfaces to Intel and Motorola (and compatible) 8-bit microcontrollers for initialization, testing, and status monitoring.♦ Direct interface to off-the-shelf NTSC/PAL video encoders.♦ Direct interface to off-the-shelf audio stereo DACs.♦ Available in a 160-pin, PQFP pack.♦ Low power 3.3-Volt process.♦ TTL-compatible I/O pins.Features 1-7
  29. 29. http://krimo666.mylivepage.com/ Chapter 2 I/O Signal Descriptions This chapter describes the input/output signals of the L64105. The chapter contains the following sections: ♦ Section 2.1, “Signals Organization,” page 2-1 ♦ Section 2.2, “Host Interface,” page 2-3 ♦ Section 2.3, “Channel Interface,” page 2-5 ♦ Section 2.4, “Memory Interface,” page 2-7 ♦ Section 2.5, “Video Interface,” page 2-8 ♦ Section 2.6, “Audio Interface,” page 2-9 ♦ Section 2.7, “Miscellaneous and Test Interfaces,” page 2-112.1 Signals Organization The L64105 has six major interfaces: ♦ Host (8-bit microcontroller interface) ♦ Channel (8-bit synchronous or asynchronous bitstream data channel) ♦ Memory (16-bit synchronous SDRAM interface) ♦ Video (8-bit multiplexed digital video output) ♦ Audio (serial digital audio output) ♦ Test Figure 2.1 shows the signals, their grouping, and their I/O direction. A lower case “n” at the end of a signal name indicates that it is an active LOW signal. 2-1
  30. 30. http://krimo666.mylivepage.com/Figure 2.1 L64105 I/O Signals BUSMODE PD[7:0] CSn CREF A[8:0] BLANK ASn OSD_ACTIVE Video D[7:0] Interface EXT_OSD[3:0] DSn/WRITEn HS HostInterface READ/READn VS DTACKn/RDYn WAITn CD_ASDATA INTRn CD_BCLK DREQn CD_LRCLK PREQn CD_ACLK ASDATA AREQn BCLK VREQ LRCLK Audio CH_DATA[7:0] A_ACLK InterfaceChannel AVALIDn L64105 AUDIO_SYNCnInterface VVALIDn ACLK_32 ERRORn ACLK_441 DCK ACLK_48 SPDIF_IN SPDIF_OUT SCSn SCS1n PLLVDD SDQM PLLVSS SBA[11:0] RESETn Memory SCASnInterface SYSCLK Miscellaneous and SRASn Test Interface TM[1:0] SBD[15:0] SWEn ZTEST SCLK SCAN_TE2-2 I/O Signal Descriptions
  31. 31. http://krimo666.mylivepage.com/2.2 Host Interface BUSMODE Host Controller Select Pin Input This pin must be tied to VSS if the host CPU is an Intel processor or to VDD if it is a Motorola processor. The Intel processor uses two separate pins, READn and WRITEn, for read and write transfers. The Motorola processor uses a single read/write signal, READ. CSn Chip Select Input This active-LOW signal indicates an attempt by an external host CPU to access the L64105 either for a read or a write bus cycle. CSn must be asserted for the entire read/write cycle and may held LOW for more than one bus transaction. A[8:0] Address Input Nine-bit address input selects one of 512 internal registers. The address value on these lines is latched on the falling edge of READn in a read cycle and on the falling edge of WRITEn in a write cycle in Intel mode. Motorola mode uses a separate address strobe, ASn. ASn Address Strobe Input Active-LOW address strobe input. This signal is used in Motorola mode to latch the address. D[7:0] Host Data Bus Bidirectional The host uses the D[7:0] bidirectional data bus to program the L64105 and access status and bitstream information during operation. During a read bus cycle, D[7:0] carries valid information from an internal L64105 register. DTACKn/RDYn or WAITn indicate when the data on the bus is valid. In write cycles, the data is latched by the L64105 on the rising edge of DSn/WRITEn. DSn/WRITEn Data Strobe/Write Indicator Input DSn - Motorola Mode DSn indicates when the host strobes the data in or out of the L64105. Read transactions start when DSn, CSn, and ASn are all LOW. During a write cycle, the L64105 latches the data on the bus on the rising edge of DSn. Host Interface 2-3
  32. 32. http://krimo666.mylivepage.com/ WRITEn - Intel Mode The external host asserts WRITEn to start a write cycle. READn must be HIGH during a write cycle, and CSn must be LOW during a write cycle. The address is registered on the falling edge of WRITEn. The data is latched by the L64105 on the rising edge of WRITEn. READ/READn Read/Write Strobe - Read Indicator Input READ - Motorola Mode The Motorola host asserts READ HIGH for a read cycle and deasserts it for a write cycle. CSn must be asserted to select the L64105. READn - Intel Mode The Intel host asserts READn and holds WRITEn deasserted to perform a read cycle. The address is registered on the falling edge of READn. CSn must be asserted to select the L64105. DTACKn/RDYn Data Acknowledge/Data Ready 3-State Output DTACKn - Motorola Mode The L64105 asserts this signal to indicate to the external host that the current bus transaction (read or write) can be completed. DTACKn is 3-stated if CSn is not asserted. The bus cycle is terminated if the L64105 deasserts DTACKn before the cycle is completed. RDYn - Intel Mode The L64105 asserts this signal to indicate to the external host that the current bus transaction (read or write) can be completed. RDYn is 3-stated if CSn is not asserted. The bus cycle is terminated if the L64105 deasserts RDYn before the cycle is completed. WAITn Wait 3-State Output This signal may be used instead of DTACKn/RDYn by hosts that require an inverted sense. The L64105 asserts WAITn to indicate that its Host Interface is busy with a read or write bus cycle and it deasserts it when the current cycle is completed. WAITn is 3-stated when CSn is not active. INTRn Interrupt OD Output INTRn is an active-LOW, open-drain, output signal. The L64105 asserts this signal to alert the host that an2-4 I/O Signal Descriptions
  33. 33. http://krimo666.mylivepage.com/ unmasked interrupt condition has occurred in the chip. The host must read registers 0 through 4 to determine the cause of the interrupt, take the appropriate action, and set the Clear Interrupt Pin bit in Register 6 (page 4-10) to deassert INTRn. DREQn DMA Transfer Request Output The L64105 asserts this signal when it is ready to receive a new byte of data from or transmit a new byte of data to an external DMA controller. The state of DREQn reflects the condition of internal read and write FIFOs. For DMA write cycles, DREQn is deasserted when the write FIFO is not near full (more than one space left) and deasserted when the FIFO is near full (one space left). For read cycles, DREQn is asserted when the read FIFO is not near empty (more than one space filled) and deasserted when the FIFO is near empty (one space filled). The maximum transfer rate over this interface is 20 Mbps in worst case conditions. The peak data rate may increase above this depending on system SDRAM usage. PREQn PCM FIFO Request Output The L64105 asserts this signal when it is ready to receive a new byte of data in the PCM FIFO, i.e., when the FIFO is not near full (less than 25 bytes unread). The PCM FIFO allows the host to send Linear PCM audio samples to the Audio Decoder in the L64105. PREQn can be used as a request signal to an external DMA controller.2.3 Channel Interface AREQn Audio Transfer Request Output The L64105 asserts AREQn when it is ready to receive a new byte of coded audio data in A/V PES stream mode (from a transport stream demultiplexer) or a new byte of any data in program stream modes. The decoder is ready when the channel input FIFO is not near full. VREQn Video Transfer Request Output The L64105 asserts VREQn when it is ready to receive a new byte of coded audio data in A/V PES stream mode (from a transport stream demultiplexer). The decoder is ready when the channel input FIFO is not near full. VREQn is not used in program stream modes. Channel Interface 2-5
  34. 34. http://krimo666.mylivepage.com/ CH_DATA[7:0] Channel Data Bus Input The CH_DATA bus is used to transfer 8-bit, parallel bitstreams into the L64105. The maximum transfer rate over this interface is 20 Mbps in worst case conditions. The peak data rate may increase above this rate depending on system SDRAM usage. AVALIDn Audio Data Valid Input The channel device asserts this signal in response to AREQn when the data byte it placed on the CH_DATA bus is valid. The L64105 transfers the byte in when AVALIDn is deasserted. This signal can be used with the DCK input for synchronous transfers. VVALIDn Video Data Valid Input The channel device asserts this signal in response to VREQn when the data byte it placed on the CH_DATA bus is valid. The L64105 transfers the byte in when VREQn is deasserted. This signal can be used with the DCK input for synchronous transfers. This signal is used only in the A/V PES stream mode when the channel input is a program from a transport stream demultiplexer. Use the AVALIDn signal for all data bytes in program stream modes. ERRORn Bitstream Error Input ERRORn is asserted by the channel device to signal uncorrectable errors in the bitstream and is used by the L64105 to invoke error handling routines. It is latched by the L64105 on the rising edge of AVALIDn or VVALIDn. DCK Channel Clock Input The DCK is a free-running clock from the external channel device. It must have a period ≥ 3 x that of SYSCLK (27 MHz). DCK, together with the AVALIDn and VVALIDn signals, is used to write data synchronously to the L64105 channel input.2-6 I/O Signal Descriptions
  35. 35. http://krimo666.mylivepage.com/2.4 Memory Interface Important: The length of all connections between the L64105 and SDRAM on a PCB layout must be kept as short as possible, must be matched in length and pin load, and the pin load should be less than 50 pF. SCSn SDRAM Chip Select Output The host asserts this signal to select the low address SDRAM chip, the first 2 Mbytes of memory. The recommended SDRAM size for the L64105 is: 2048 × 512 × 16 bits SCS1n Second SDRAM Chip Select Output The host asserts this signal to select the high address SDRAM chip in systems that have more than 2 Mbytes of memory. The high address SDRAM chip must have the same page size as the low address SDRAM chip but does not have to have the same number of pages. SDQM SDRAM Control Pin Output SDQM is an active HIGH output signal for the SDRAM data control mask. SBA[11:0] SDRAM Address Bus Output The row/column multiplexed address bus for SDRAM memory. The L64105’s microcontroller and the host address SDRAM as if it were RAM. The Memory Interface converts these addresses to SDRAM format. SCASn SDRAM Column Address Select Output The Memory Interface asserts this signal when the SDRAM column address is on SBA[11:0]. SRASn SDRAM Row Address Select Output The Memory Interface asserts this signal when the SDRAM row address is on SBA[11:0]. SBD[15:0] SDRAM Data Bus Bidirectional This 16-bit bidirectional data bus is directly connected to 1M x 16 SDRAM(s) for buffering channel data and reconstructed pictures. Memory Interface 2-7
  36. 36. http://krimo666.mylivepage.com/ SWEn SDRAM Write Enable Output The Memory Interface asserts SWEn for SDRAM write cycles and holds it deasserted for SDRAM read cycles. SCLK SDRAM 81-MHz Clock Output The 27-MHz SYSCLK input is multiplied by three using the on-chip PLL to generate the 81-MHz SCLK. Important: SCLK should be connected through a 33-Ω terminating resistor mounted as close as possible to the SCLK pin of the L64105.2.5 Video Interface PD[7:0] Pixel Data Output Bus Output The PD[7:0] bus carries the pixel data for the reconstructed pictures. The pixel data is formatted in ITU_R BT.601 Y, Cb, Cr chromaticity. CREF Chroma Reference Output The Video Interface asserts CREF when the Cb component of Chroma is on PD[7:0] and deasserts it at all other times. BLANK Blank Output BLANK is a composite blank output from the L64105 display controller. Its polarity is user-defined. OSD_ACTIVE On-Screen Display Output The Memory Interface asserts this signal to indicate that the on-chip OSD pixel on PD[7:0] is nontransparent. This signal indicates which pixels have mixed OSD. EXT_OSD[3:0] Palette Selection Bus Input The host controls an external device (such as a character generator) to write half-bytes across this bus to select colors from a 16-color look-up table in the L64105 to be used for external OSD.2-8 I/O Signal Descriptions
  37. 37. http://krimo666.mylivepage.com/ HS Horizontal Sync Input HS is the horizontal sync signal from the PAL/NTSC Encoder. HS is used to reset the horizontal counters in the display controller. HS should be synchronous to SYSCLK. VS Vertical Sync/Odd-Even Field Indicator Input VS is the vertical sync signal from the PAL/NTSC Encoder. It can be programmed to be either a conventional vertical sync input or an even/odd field indicator. In the even/odd field indicator mode, the internal display controller counters reset each time VS changes state (at the beginning of each field). The polarity of the field is controlled by the timing of VS relative to HS. VS should be synchronous to SYSCLK.2.6 Audio Interface CD_ASDATA CD Mode Audio Data Input Unencoded serial audio data from a CD or other storage device. Connected directly to the ASDATA output when the host selects the CD Bypass mode. CD_BCLK CD Mode DAC Bit Clock Input Bit clock from CD player. Connected directly to the BCLK output when the host selects the CD Bypass mode. CD_LRCLK CD Mode DAC Left/Right Clock Input Left/right sample clock from CD player. Connected directly to the LRCLK output when the host selects the CD Bypass mode. CD_ACLK CD Mode DAC Clock Input DAC clock from CD player. Connected directly to the A_ACLK output when the host selects the CD Bypass mode. ASDATA Audio Serial Data Output Serial audio data from the L64105’s Audio Decoder in nonbypass modes. The data can be MPEG or Linear PCM audio. Serial audio data from the CD_ASDATA input in CD Bypass mode. Audio Interface 2-9
  38. 38. http://krimo666.mylivepage.com/ BCLK DAC Bit Clock Output Serial data bit clock used by the L64105’s DAC Interface to serialize the decoded audio data and by the external DAC to clock it in on the rising edge. BCLK is derived from one of the ACLK_ inputs under host control in normal modes and is the CD_BCLK input in CD Bypass mode. LRCLK DAC Left/Right Sample Clock Output Used to indicate which samples belong to the left and right stereo channels. In default mode, LRCLK is asserted when the right channel sample is on the ASDATA pin and deasserted when the left channel sample is on the ASDATA pin. The host can set the Invert LRCLK bit in Register 363 (page 4-84) to invert the sense of the clock (HIGH for left channel, LOW for right). A_ACLK DAC Clock Output This clock is buffered from the selected input ACLK_ (see the following ACLK_ description). In CD-bypass mode, this clock comes directly from the CD_ACLK input pin. AUDIO_SYNCn Audio Sync Strobe Output Provides an indication of Audio Decoder synchronization to the bitstream. Used in transport systems requiring hardware sync controls. This is an active LOW pulse at the time of the audio frame decode start. ACLK_32, ACLK_441, ACLK_48 Audio Reference Clocks Input Host selectable audio reference clocks from which clocks for the external DAC, internal DAC Interface, and internal S/P DIF Interface are derived. ACLK_32 = 32 kHz * N, ACLK_441 = 44.1 kHz * N, and ACLK_48 = 48 kHz * N where N = 768, 512, 384, or 256. At least one of the three ACLK_ inputs must be supplied and it must be integrally divisible into the required sample rate clocks. See the ACLK Select bits in Register 363 (page 4-84) and the ACLK Divider Select bits in Register 364 (page 4-85).2-10 I/O Signal Descriptions
  39. 39. http://krimo666.mylivepage.com/ SPDIF_IN External S/P DIF Input This input is directly connected to the SPDIF_OUT pin when the host selects the S/P DIF Bypass mode. SPDIF_OUT S/P DIF Output Output IEC958 formatted output of the L64105’s S/P DIF Interface in normal modes and SPDIF_IN in S/P DIF Bypass mode.2.7 Miscellaneous and Test Interfaces PLLVDD PLL Power Supply Input This pin provides power (3.3 V) to the on-chip PLL for deriving the 81-MHz SDRAM clock. This power supply pin must be isolated from the digital power plane with the filter shown in Figure 2.2 and only connected at the voltage regulator. Figure 2.2 PLLVDD Decoupling Circuit Ferrite Bead VDD PLLVDD 1 µF 10 µF PLLVSS PLLVSS PLLVSS PLL Ground Input This pin provides ground to the on-chip PLL for deriving the 81-MHz SDRAM clock. This supply pin must be isolated from the digital ground plane, and only connected at the voltage regulator. It should be decoupled from the PLLVDD pin. RESETn Reset Input When RESETn is asserted, the L64105 resets its internal microcontroller, FIFO controllers, state machines, and registers. The minimum RESETn pulse width is 8 cycles of SYSCLK (8/27 MHz = 300 ns). SYSCLK and the selected ACLK (ACLK_32, ACLK_441, or ACLK_48) must be running during reset. Miscellaneous and Test Interfaces 2-11
  40. 40. http://krimo666.mylivepage.com/ SYSCLK Device Clock Input Device clock has a nominal frequency of 27 MHz. Picture reconstruction and video timing are referenced with respect to this clock. SYSCLK also drives the PLL to generate the 81-MHz clock for the SDRAM interface. TM[1:0] Test Mode Input These inputs are used by LSI Logic during manufacturing test. They are not exercised in a customer system. They should both be tied to VSS in the system. ZTEST Test Mode Input Test mode pin. This should be tied to VDD in the system for normal operation. Forcing this signal LOW 3-states all outputs allowing for simple PCB bed-of-nails testing. SCAN_TE Test Mode Input Test mode pin. This should be tied to VSS in the system for normal operation.2-12 I/O Signal Descriptions
  41. 41. http://krimo666.mylivepage.com/ Chapter 3 Register Summary Communication with the L64105 Decoder is through 512, 8-bit registers. The registers are named by their decimal address, 0 to 511. They are organized into the eight groups listed in Table 3.1. The registers, fields, and bits in each group are further detailed in Table 3.2 through Table 3.8. To find a register, field, or bit, use Table 3.1 to find the starting page of the summary table for the group. Then use the summary table to find the page in Chapter 4 on which the register is described. If you know the name of a field or bit, use the alphabetic index starting on page 3-31 to find the page number on which it is described.3.1 Summary by Register Table 3.1 L64105 Register Groupings Register Table Page Number Register Group Number Reference 0–63 Host Interface Registers 3.2 3-2 64–191 Video Decoder Registers 3.3 3-7 192–223 Memory Interface Registers 3.4 3-14 224–255 Microcontroller Registers 3.5 3-17 256–335 Video Interface Registers 3.6 3-20 336–383 Audio Decoder Registers 3.7 3-24 384–415 RAM Test Registers 3.8 3-27 3-1
  42. 42. http://krimo666.mylivepage.com/Table 3.2 Host Interface Registers Default Addr Addr Value Page (Dec) (Hex) Bit(s) R/W (Hex) Status/Command/Data Ref. 0 0 0 R1 0 Decode Status Interrupt 4-2 W 0 Decode Status Mask 1 R1 0 Aux/User Data FIFO Ready Interrupt 4-2 W 0 Aux/User Data FIFO Ready Mask 2 R1 0 First Slice Start Code Detect Interrupt 4-3 W 0 First Slice Start Code Detect Mask 3 R1 0 Sequence End Code Detect Interrupt 4-3 W 0 Sequence End Code Detect Mask 4 R1 0 SDRAM Transfer Done Interrupt 4-3 W 0 SDRAM Transfer Done Mask 5 1 Reserved 6 R 0 Audio Sync Recovery Interrupt 4-3 W 0 Audio Sync Recovery Mask 7 R 0 New Field Interrupt 4-3 W 0 New Field Mask 1 1 0 R1 0 Audio Sync Code Detect Interrupt 4-3 W 0 Audio Sync Code Detect Mask 1 R1 0 Picture Start Code Detect Interrupt 4-4 W 0 Picture Start Code Detect Mask 2 R1 0 SCR Compare Audio Interrupt 4-4 W 0 SCR Compare Audio Mask 3 1 Reserved 4 R1 0 Begin Active Video Interrupt 4-4 W 0 Begin Active Video Mask(Sheet 1 of 5)3-2 Register Summary

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