Terahertz trigate transistor


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Terahertz trigate transistor

  1. 1. High Performance Non-Planar Tri-gate Transistor Architecture Dr. Gerald Marcyk Director Components Research Logic Technology Development Intel Intel 1
  2. 2. What Are We Announcing? • Invention of a novel tri-gate fully depleted transistor with industry leading performance − • A three dimensional extension of the TeraHertz architecture − − • Highest reported drive current for non-planar devices Depleted substrate improves Ioff leakage Improved manufacturability over proposed double gate structures − Intel Intel Research targeted for 2nd half of the decade Uses 300mm equipment and existing lithography capabilities 2
  3. 3. Why is this Important? • Transistor research breakthroughs will allow us to continue Moore’s Law through end of decade • IC Industry is making transition from Planar to Non-Planar Transistors • This development has potential to enable products with higher performance that use less power • Intel transistors lead industry performance in both research and manufacturing • Intel’s $4B investment in R&D continues on track: delivering a new process technology every 2 years Intel Intel 3
  4. 4. Moore’s Law A new technology every 2 years Process Name P856 P858 Px60 P1262 P1264 P1266 P1268 1st Production 1997 1999 2001 2003 2005 2007 2009 Lithography .25µm .18µm .13µm 90nm 65nm 45nm 32nm Gate Length .20µm .13µm <70nm <50nm 200 200 Wafer Size (mm) 200/300 <35nm <25nm <18nm 300 300 300 300 Manufacturing Development Research Copy Exactly! Intel Intel Pathfinding 4
  5. 5. Accelerated Scaling of 130nm Node Planar Transistors 90nm Node 70nm Length (Production2001) 65nm Node 50nm Length (Production in 2003) 45nm Node 30nm Prototype (Production in 2005) 32nm Node 25 nm 20nm Prototype (Production in 2007) Intel Intel 15nm 15nm Prototype (Production in 2009) 5
  6. 6. Silicon devices are Nanotechnology 50nm 100nm Influenza virus Transistor for 90nm process Source: CDC Source: Intel 25 nm 15nm Intel Intel 15nm Research Transistor 6
  7. 7. Transistor Gate Length Scaling 10 1 10 3.0um 2.0um 1.5um 1.0um .8um 1 .5um .35um .25um .18um .13um 90nm Micron 0.1 Gate Length 0.01 1970 Typical Feature Size 1980 1990 0.1 50nm 2000 2010 0.01 2020 Transistor Gate Length is Smallest Feature on the Device Intel Intel 7
  8. 8. Planar Transistor Problem: Smaller Devices have Higher Leakage Research data in literature Ioff (A/um) 1.E-04 () 1.E-06 1.E-08 Production data Intel’s 15nm transistor (2001) 1.E-10 1.E-12 () Intel’s 30nm transistor ( 2000) 1.E-14 10 100 1000 Transistor Physical Lg (nm) We need novel device structures to meet this challenge Intel Intel 8
  9. 9. Intel’s TeraHertz Transistor: Lower Ioff Leakage Raised Source/ Drain Gate < 30nm Silicon Oxide High-k Gate Dielectric Fully Depleted Substrate: Subthreshold Leakage is Approaching Theoretical Minimum Intel Intel 9
  10. 10. A Switch to Non-Planar CMOS Transistors • Planar TeraHertz Transistor Improves Leakage − Control of Nano-thick Silicon Layer becomes the Manufacturing Issue • Three Dimensional Devices ( Non-Planar) have been Proposed by Researchers − − − Intel Intel Dual Gate, FinFET, etc. Complex Fabrication processes Measured Device Performance has been Disappointing 10
  11. 11. New Tri-Gate Transistor Structure Gate Source Drain Gate Oxide Oxide Substrate Intel Intel 11
  12. 12. Tri-gate Transistor works in Three Dimensions Tri-Gate Planar CMOS Gate 1 Gate Gate 2 Gate 3 SiO2 Buried Oxide Intel Intel SiO2 Silicon Substrate 12
  13. 13. Silicon Body Thickness (nm) Tri-Gate’s Geometry Advantage 60 Tri-Gate 50 Double- Gate Double- 40 ( 30 Single- Gate Single-Gate 20 10 0 0 20 40 60 80 Device Gate Length, Lg (nm) Tri-gate is Fully Depleted Without Unusual Lithography Patterning or SOI Thickness Control Issues. Intel Intel 13
  14. 14. Multi-Channel Tri-gate Devices: Even More Drive Current Gate Multiple Drains Gate Drains Sources Multiple Sources Intel Intel 14
  15. 15. Conclusions • High-Performance Tri-Gate Fully-Depleted CMOS with 60nm physical gate length has been Demonstrated • Tri-gate Fully-Depleted CMOS exhibits lower leakage than standard planar CMOS − Similar to Planar TeraHertz Transistor • Unique Tri-Gate Geometry is more Manufacturable than Fully-Depleted Planar and Double Gate structures. • Tri-gate with Spacer-Defined Fins has Potential to deliver 20% Higher Total Current per unit Layout Area than Standard CMOS Intel Intel 15
  16. 16. Additional details of this Tri-gate transistor technology will be presented at the International Solid State Device and Materials Conference in Nagoya Japan on Sept 17, 2002 For further information on Intel's silicon technology, please visit the Silicon Showcase at www.intel.com/research/silicon Intel Intel 16
  17. 17. BACK – UP MATERIAL Intel Intel 17
  18. 18. New Tri-gate Transistor Structure Current Lg WSi Gate Oxide HSi Improved Manufacturability Width = Height = Gate Length Intel Intel 18
  19. 19. Double Gate FinFET Transistor Current HSi Gate Oxides Lg WSi Major Problem: Fin Width must be Narrower than Gate Length Lithography becomes the Key Limiter Intel Intel 19
  20. 20. New materials Extend Performance of 90nm Planar Transistors Changes made Future options Gate High-k gate dielectric Silicide added New transistor structure Channel Strained silicon Transistor Intel Intel 20
  21. 21. 90 nm Generation Transistor Silicide Layer Silicon Gate Electrode 50nm 1.2 nm SiO2 Gate Oxide Strained Silicon Intel Intel 21
  22. 22. Strained Silicon Transistors Current Flow Normal electron flow Normal Silicon Lattice Intel Intel Faster electron flow Strained Silicon Lattice 22