Personal Information
Organization / Workplace
Hyderabad Area, India India
Occupation
Senior Design Engineer
Industry
Telecom / Mobile
About
• Designed and implemented support for dynamic power and frequency variation support in the Crest Factor Reduction (PC-CFR) Radio core.
• Productization work involving release formalities, C model development and test framework development for multiple PC-CFR releases
• Developed FPGA IP for the I.4 OTN encoder. Designed, synthesized and timing optimized the RS and BCH encoders for the 10Gbps standard. A novel architecture was used for the RS encoder so that it could meet the design requirements. A patent has been applied for the same. The design is now being used successfully by multiple customers. This, along with the decoder counterpart was also productized in Vivado 2013.1 re...
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