DATA MANIPULATION1
2.1 COMPUTER ARCHITECTUREData Manipulation2
COMPUTER ARCHITECTURE Central Processing Unit (CPU) Arithmetic Logic Unit (ALU) Registers General-purpose Special-pur...
MODERN INTEL AND AMD CPUSIntel Core i7 AMD Phenom II X44
45NM PROCESSOR WAFER2-5
Data BusAddress BusControl Bus1230 45679AB8EFCDCONSTITUENT COMPONENTS OF A CPUI/O UnitControl UnitProgram Counter (PC)Inst...
A BUS2-7
COMPUTER BUSES Collection of wires that connect the components ofa computer to one another Address Data Control Power...
CPU AND MEMORYCONNECTED VIA A BUSSystemMemoryCPUBus2-9
ADDING TWO VALUES STORED IN SYSTEM MEMORYIS A FIVE-STEP PROCESSStep 1 Get the first value to be added from memory and stor...
STORED PROGRAMS Programs can be encoded as a sequence of bitsand stored in system memory Obvious today Not always so E...
ENIAC BEING PROGRAMMEDBY EARLY COMPUTERS2-12
VON NEUMANN ARCHITECTURESystemMemoryI/ODevicesALUControlUnitCPU2-13
TYPES OF MEMORYRegistersCacheSystem MemoryMass StoragePriceQuantitySpeed2-14
2.2 MACHINE LANGUAGEData Manipulation15
MACHINE LANGUAGE Machine instruction: a command recognized by theCPU and encoded as a bit pattern Machine language: the ...
EXAMPLE: DIVIDING VALUES STORED IN MEMORYStep 1 LOAD a register with value from memory.Step 2 LOAD another register with a...
AN ILLUSTRATIVE MACHINE LANGUAGE We will be using the hypothetical machinedescribed in Appendix C of the book: 16 one-by...
ARCHITECTURE OF THE MACHINE INAPPENDIX CRegistersALUControl UnitPCIR0123456789ABCDEF2-19
INSTRUCTION AND DATA TEMPLATES0 0 1 1 0 1 0 1 1 0 1 0 0 1 1 11 1 0 0 1 0 0 00 1 0 1 0 1 1 1opcode operand operand operandI...
EXAMPLE: ADDING VALUES STORED IN MEMORYEncodedInstructionTranslation156C LOAD register 5 with the bit pattern found at add...
2.3 PROGRAM EXECUTIONData Manipulation22
THE MACHINE CYCLEFetch• [PC] → IR• Increment PCDecode• Interpret IR• Fetch operand(s)Execute• Carry outinstruction2-23
PROGRAMS VS DATA Everything in memory is encoded in strings of 1’sand 0’s There is no differentiation between data and c...
EXAMPLE PROGRAM WALK-THROUGH (PG. 98)RegistersALUControl UnitPCIR0123456789ABCDEF2-25
2.4 ARITHMETIC/LOGIC INSTRUCTIONSData Manipulation26
LOGICAL OPERATIONS1 0 0 1 1 0 1 0AND 1 1 0 0 1 0 0 11 0 0 0 1 0 0 01 0 0 1 1 0 1 0XOR 1 1 0 0 1 0 0 10 1 0 1 0 0 1 11 0 0 ...
BIT MAPS A bit map is a way of using a value in the computerby assigning each bit in the value some meaning We could sto...
MASKS Using a mask we can extract the status of anygiven bit(s) in a string of bits The following example tests to see i...
BIT SHIFTING Circular Shifts Also called rotations Logical Shifts Left or right Also called arithmetic shifts2-30
2.5 COMMUNICATING WITHOTHER DEVICESData Manipulation31
CONTROLLERS ATTACHED TO AMACHINE’S BUS2-32
MOTHERBOARDBLOCK DIAGRAM2-33
X58 CHIPSET ARCHITECTURE2-34
MEMORY-MAPPED I/O In many computers I/O devices are read from andwritten just as memory is A certain amount of address s...
MISSING RAM2-36
DIRECT MEMORY ACCESS (DMA) Allows certain hardware subsystems to accesssystem memory independently of the CPU Historical...
HANDSHAKING Two-way communication between the processorand a peripheral device Status word: a bit map used to communicat...
PARALLEL VS SERIAL COMMUNICATION 1-bit at a time Simple to implement Lower bandwidth thanparallel Able to transmit ove...
2.6 OTHER ARCHITECTURESData Manipulation41
PIPELINING Technique for speeding up execution of a program Each stage of the machine cycle can run in parallelon differ...
PIPELININGt0 t1 t2 t3 t4 t5 t6 t7 t8FetchDecodeExecuteWriteCompletedFetchDecodeExecuteWriteCompletedWithoutPipeliningWithP...
PARALLEL PROCESSING ANDMULTIPROCESSOR MACHINES Parallel processing means to execute multiplethreads or processes simultan...
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Cs160 chapter 2

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Cs160 chapter 2

  1. 1. DATA MANIPULATION1
  2. 2. 2.1 COMPUTER ARCHITECTUREData Manipulation2
  3. 3. COMPUTER ARCHITECTURE Central Processing Unit (CPU) Arithmetic Logic Unit (ALU) Registers General-purpose Special-purpose Control Unit Input/output (I/O) Unit2-3
  4. 4. MODERN INTEL AND AMD CPUSIntel Core i7 AMD Phenom II X44
  5. 5. 45NM PROCESSOR WAFER2-5
  6. 6. Data BusAddress BusControl Bus1230 45679AB8EFCDCONSTITUENT COMPONENTS OF A CPUI/O UnitControl UnitProgram Counter (PC)Instruction Register (IR)Other OtherOther OtherOther OtherRegistersALU2-6
  7. 7. A BUS2-7
  8. 8. COMPUTER BUSES Collection of wires that connect the components ofa computer to one another Address Data Control Power (usually ignored)2-8
  9. 9. CPU AND MEMORYCONNECTED VIA A BUSSystemMemoryCPUBus2-9
  10. 10. ADDING TWO VALUES STORED IN SYSTEM MEMORYIS A FIVE-STEP PROCESSStep 1 Get the first value to be added from memory and storeit in a register.Step 2 Get the second value to be added from memory andstore it in another register.Step 3 Activate the circuitry in the ALU responsible foraddition. Add the values from Steps 1 & 2 and storethe sum in a third register.Step 4 Write the contents of register holding the result back tosome address in memory.Step 5 Halt.2-10
  11. 11. STORED PROGRAMS Programs can be encoded as a sequence of bitsand stored in system memory Obvious today Not always so Early computers were hard-wired Difficult to re-program von Neumann architecture Memory is an array of individually-addressable cells thatstore both instructions and data Control unit interprets and executes instructions2-11
  12. 12. ENIAC BEING PROGRAMMEDBY EARLY COMPUTERS2-12
  13. 13. VON NEUMANN ARCHITECTURESystemMemoryI/ODevicesALUControlUnitCPU2-13
  14. 14. TYPES OF MEMORYRegistersCacheSystem MemoryMass StoragePriceQuantitySpeed2-14
  15. 15. 2.2 MACHINE LANGUAGEData Manipulation15
  16. 16. MACHINE LANGUAGE Machine instruction: a command recognized by theCPU and encoded as a bit pattern Machine language: the set of machine instructionsa particular CPU recognizes Flavors: Reduced Instruction Set Computer (RISC) Complex Instruction Set Computer (CISC) Instruction categories: Data transfer Arithmetic/logic Control 2-16
  17. 17. EXAMPLE: DIVIDING VALUES STORED IN MEMORYStep 1 LOAD a register with value from memory.Step 2 LOAD another register with another value frommemory.Step 3 If this second value equals zero, JUMP to Step 6.Step 4 Divide the contents of the first register by the contentsof the second register putting the quotient in a thirdregister.Step 5 Store the contents of the third register in memory.Step 6 HALT.2-17
  18. 18. AN ILLUSTRATIVE MACHINE LANGUAGE We will be using the hypothetical machinedescribed in Appendix C of the book: 16 one-byte, general-purpose registers 256 one-byte memory cells Two-byte instructions2-18
  19. 19. ARCHITECTURE OF THE MACHINE INAPPENDIX CRegistersALUControl UnitPCIR0123456789ABCDEF2-19
  20. 20. INSTRUCTION AND DATA TEMPLATES0 0 1 1 0 1 0 1 1 0 1 0 0 1 1 11 1 0 0 1 0 0 00 1 0 1 0 1 1 1opcode operand operand operandInstruction TemplatemantissaexponentexponentInteger Template Floating-Point Template2-20
  21. 21. EXAMPLE: ADDING VALUES STORED IN MEMORYEncodedInstructionTranslation156C LOAD register 5 with the bit pattern found at address6C.166D LOAD register 6 with the bit pattern found at address6D.5056 ADD contents of registers 5 and 6 and put the sum inregister 0.306E STORE the contents of register 0 in address 6E.C000 HALT.2-21
  22. 22. 2.3 PROGRAM EXECUTIONData Manipulation22
  23. 23. THE MACHINE CYCLEFetch• [PC] → IR• Increment PCDecode• Interpret IR• Fetch operand(s)Execute• Carry outinstruction2-23
  24. 24. PROGRAMS VS DATA Everything in memory is encoded in strings of 1’sand 0’s There is no differentiation between data and code The control unit interprets the contents of certaincells as instructions and other cells as data Programs can even modify themselves during execution2-24
  25. 25. EXAMPLE PROGRAM WALK-THROUGH (PG. 98)RegistersALUControl UnitPCIR0123456789ABCDEF2-25
  26. 26. 2.4 ARITHMETIC/LOGIC INSTRUCTIONSData Manipulation26
  27. 27. LOGICAL OPERATIONS1 0 0 1 1 0 1 0AND 1 1 0 0 1 0 0 11 0 0 0 1 0 0 01 0 0 1 1 0 1 0XOR 1 1 0 0 1 0 0 10 1 0 1 0 0 1 11 0 0 1 1 0 1 0OR 1 1 0 0 1 0 0 11 1 0 1 1 0 1 12-27
  28. 28. BIT MAPS A bit map is a way of using a value in the computerby assigning each bit in the value some meaning We could store the day of the week in a byte7 6 5 4 3 2 1 0NotUsedSaturdayFridayThursdayWednesdayTuesdayMondaySunday2-28
  29. 29. MASKS Using a mask we can extract the status of anygiven bit(s) in a string of bits The following example tests to see if it’s Friday yet:Bit Map 0 0 0 0 0 0 1 0Mask (AND) 0 0 1 0 0 0 0 0Result 0 0 0 0 0 0 0 02-29
  30. 30. BIT SHIFTING Circular Shifts Also called rotations Logical Shifts Left or right Also called arithmetic shifts2-30
  31. 31. 2.5 COMMUNICATING WITHOTHER DEVICESData Manipulation31
  32. 32. CONTROLLERS ATTACHED TO AMACHINE’S BUS2-32
  33. 33. MOTHERBOARDBLOCK DIAGRAM2-33
  34. 34. X58 CHIPSET ARCHITECTURE2-34
  35. 35. MEMORY-MAPPED I/O In many computers I/O devices are read from andwritten just as memory is A certain amount of address space is set aside forcommunicating with memory-mapped devices These addresses reside at the top of the addressablememory range 232 = 4,294,967,296 or 4,096 MB 264 = 18,446,744,073,709,551,616 18 quintillion bytes 18 petabytes PB 17,592,186,044,416 MB2-35
  36. 36. MISSING RAM2-36
  37. 37. DIRECT MEMORY ACCESS (DMA) Allows certain hardware subsystems to accesssystem memory independently of the CPU Historically the CPU would have been responsiblefor every bit transferred in the computer DMA allows peripherals to transfer blocks of data toand form memory without CPU intervention2-37
  38. 38. HANDSHAKING Two-way communication between the processorand a peripheral device Status word: a bit map used to communicatebetween the system and the external device One bit may indicate an out-of-paper error Another signals the printer is ready for more data The controller monitors the status and passesimportant messages along to the CPU2-38
  39. 39. PARALLEL VS SERIAL COMMUNICATION 1-bit at a time Simple to implement Lower bandwidth thanparallel Able to transmit overlonger distances thanparallel Multiple bits at a time Higher bandwidth thanserial Trickier to implement Limited distance Propagation delay “Noisy” Mutual inductance CapacitanceSerial Parallel39
  40. 40. 2.6 OTHER ARCHITECTURESData Manipulation41
  41. 41. PIPELINING Technique for speeding up execution of a program Each stage of the machine cycle can run in parallelon different instructions Bubbles Stalls Bad prediction2-42
  42. 42. PIPELININGt0 t1 t2 t3 t4 t5 t6 t7 t8FetchDecodeExecuteWriteCompletedFetchDecodeExecuteWriteCompletedWithoutPipeliningWithPipelining2-43
  43. 43. PARALLEL PROCESSING ANDMULTIPROCESSOR MACHINES Parallel processing means to execute multiplethreads or processes simultaneously Pipelining is a step in this direction True parallel processing require more than oneCPU Several strategies Multiple, independent processors sharing memory whileexecuting separate processes Multiple cores operating on the same data at the sametime executing the same set of instructions A single core operating on multiple data sets at thesame time 2-44

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