S emb t6-arch_mem

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S emb t6-arch_mem

  1. 1. Maths is not everything Embedded Systems 4 - Hardware Architecture CPU Input/Output mechanisms Memory Buses and Aux Input/Output interfaces RMR©2012 Power Management
  2. 2. Maths is not everything Memory Organization Caches RMR©2012
  3. 3. Caches and CPUs address cache controller CPU RMR©2012 © 2008 Wayne Wolf data Maths is not everything data cache address data main memory
  4. 4. Cache operation Many main memory locations are mapped onto one cache entry. May have caches for: instructions; data; Maths is not everything RMR©2012 © 2008 Wayne Wolf data + instructions (unified). Memory access time is no longer deterministic.
  5. 5. Terms Cache hit: required location is in cache. Cache miss: required location is not in cache. Compulsory (cold): location has never been accessed. Capacity: working set is too large. Maths is not everything RMR©2012 © 2008 Wayne Wolf Conflict: multiple locations in working set map to same cache entry. Working set: set of locations used by program in a time interval.
  6. 6. Memory system performance h = cache hit rate. tcache = cache access time, tmain = main memory access time. Maths is not everything RMR©2012 © 2008 Wayne Wolf Average memory access time: tav = htcache + (1-h)tmain
  7. 7. Multiple levels of cache Maths is not everything RMR©2012 © 2008 Wayne Wolf CPU L1 cache L2 cache
  8. 8. Multi-level cache access time h1 = cache hit rate. h2 = rate for miss on L1, hit on L2. Average memory access time: Maths is not everything RMR©2012 © 2008 Wayne Wolf tav = h1tL1 + (h2-h1)tL2 + (1- h2-h1)tmain
  9. 9. Replacement policies Replacement policy: strategy for choosing which cache entry to throw out to make room for a new memory location. Two popular strategies: Maths is not everything RMR©2012 © 2008 Wayne Wolf Random. Least-recently used (LRU).
  10. 10. Cache organizations Fully-associative: any memory location can be stored anywhere in the cache (almost never implemented). Maths is not everything RMR©2012 © 2008 Wayne Wolf Direct-mapped: each memory location maps onto exactly one cache entry. N-way set-associative: each memory location can go into one of n sets.
  11. 11. Cache performance benefits Keep frequently-accessed locations in fast cache. Cache retrieves more than one word at a time. Maths is not everything RMR©2012 © 2008 Wayne Wolf Sequential accesses are faster after first access.
  12. 12. Direct-mapped cache 1 0xabcd byte byte byte ... valid tag data cache block address tag index offset Maths is not everything RMR©2012 © 2008 Wayne Wolf = hit value byte
  13. 13. Write operations Write-through: immediately copy write to main memory. Maths is not everything RMR©2012 © 2008 Wayne Wolf Write-back: write to main memory only when location is removed from cache.
  14. 14. Direct-mapped cache locations Many locations map onto the same cache block. Conflict misses are easy to generate: Array a[ ] uses locations 0, 1, 2, … Maths is not everything RMR©2012 © 2008 Wayne Wolf Array b[ ] uses locations 1024, 1025, 1026, … Operation a[i] + b[i] generates conflict misses.
  15. 15. Set-associative cache A set of direct-mapped caches: Maths is not everything RMR©2012 © 2008 Wayne Wolf Set 1 Set 2 hit ... data Set n
  16. 16. Maths is not everything RMR©2012 © 2008 Wayne Wolf Example: direct-mapped vs. set-associative
  17. 17. Direct-mapped cache behavior After 001 access: Maths is not everything RMR©2012 © 2008 Wayne Wolf block tag 00 - 01 0 10 - 11 - data 1111 - After 010 access: block tag 00 - 01 0 10 0 11 - data 1111 0000 -
  18. 18. Direct-mapped cache behavior, cont’d. After 011 access: Maths is not everything RMR©2012 © 2008 Wayne Wolf block tag 00 - 01 0 10 0 11 0 data 1111 0000 0110 After 100 access: block tag 00 1 01 0 10 0 11 0 data 1000 1111 0000 0110
  19. 19. Direct-mapped cache behavior, cont’d. After 101 access: Maths is not everything RMR©2012 © 2008 Wayne Wolf block tag 00 1 01 1 10 0 11 0 data 1000 0001 0000 0110 After 111 access: block tag 00 1 01 1 10 0 11 1 data 1000 0001 0000 0100
  20. 20. 2-way set-associtive cache behavior Maths is not everything RMR©2012 © 2008 Wayne Wolf Final state of cache (twice as big as directmapped): set blk 0 tag 00 1 01 0 10 0 11 0 blk 0 data blk 1 tag 1000 - 1111 1 0000 - 0110 1 blk 1 data 0001 0100
  21. 21. 2-way set-associative cache behavior Final state of cache (same size as directmapped): Maths is not everything RMR©2012 © 2008 Wayne Wolf set blk 0 tag blk 0 data blk 1 tag blk 1 data 0 01 0000 10 1000 1 10 0111 11 0100
  22. 22. Maths is not everything Memory Organization MMU RMR©2012
  23. 23. Memory management units Memory management unit (MMU) translates addresses: logical address Maths is not everything RMR©2012 © 2008 Wayne Wolf CPU memory management unit physical address main memory
  24. 24. Memory management tasks Allows programs to move in physical memory during execution. Allows virtual memory: memory images kept in secondary storage; Maths is not everything RMR©2012 © 2008 Wayne Wolf images returned to main memory on demand during execution. Page fault: request for location not resident in memory.
  25. 25. Address translation Requires some sort of register/table to allow arbitrary mappings of logical to physical addresses. Two basic schemes: segmented; Maths is not everything RMR©2012 © 2008 Wayne Wolf paged. Segmentation and paging can be combined (x86).
  26. 26. Segments and pages page 1 page 2 segment 1 Maths is not everything RMR©2012 © 2008 Wayne Wolf memory segment 2
  27. 27. Segment address translation segment base address logical address + segment lower bound Maths is not everything RMR©2012 © 2008 Wayne Wolf segment upper bound range check physical address range error
  28. 28. Page address translation page offset page i base Maths is not everything RMR©2012 © 2008 Wayne Wolf concatenate page offset
  29. 29. Page table organizations page descriptor Maths is not everything RMR©2012 © 2008 Wayne Wolf page descriptor flat tree
  30. 30. Caching address translations Large translation tables require main memory access. TLB: cache for address translation. Maths is not everything RMR©2012 © 2008 Wayne Wolf Typically small.
  31. 31. ARM memory management Memory region types: section: 1 Mbyte block; large page: 64 kbytes; small page: 4 kbytes. Maths is not everything RMR©2012 © 2008 Wayne Wolf An address is marked as section-mapped or page-mapped. Two-level translation scheme.
  32. 32. ARM address translation Translation table base register descriptor 1st level table 1st index 2nd index offset concatenate concatenate Maths is not everything RMR©2012 © 2008 Wayne Wolf descriptor 2nd level table physical address

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