Maths is not everything

Embedded Systems
4 - Hardware Architecture

CPU
Input/Output mechanisms
Memory
Buses And Aux
Inpu...
Maths is not everything

CPU
ISA - Introduction

RMR©2012
Instruction Set Architecture
The computer ISA defines all of the programmer-visible
components and operations of the compu...
von Neumann architecture

Memory holds data & instructions.
Central processing unit (CPU) fetches
instructions from memory...
CPU + memory

address

memory

data

200
PC

CPU

Maths is not everything

RMR©2012

© 2008 Wayne Wolf

200

ADD r5,r1,r3
...
Harvard architecture

address
data memory

data
address

Maths is not everything

RMR©2012

© 2008 Wayne Wolf

program mem...
von Neumann vs. Harvard

Harvard can’t use self-modifying code.
Harvard allows two simultaneous memory
fetches.
Most DSPs ...
RISC vs. CISC

Complex instruction set computer (CISC):
many addressing modes;
many operations.

Reduced instruction set c...
Instruction set characteristics

Maths is not everything

RMR©2012

© 2008 Wayne Wolf

Fixed vs. variable length.
Addressi...
Multiple implementations

Successful architectures have several
implementations:
varying clock speeds;
different bus width...
Assembly language

Basic features:
One instruction per line.
Labels provide names for addresses (usually in first
column).
...
ARM assembly language example

header
LDR r1,[r4]
SUB r0,r0,r1
MOV
sp,#INIT_SP
ADR
lr, start+1
BX
lr

start

CODE16

; 3 a...
MSP430 assembly language example

MOV.w
MOV.w
CMP.w!

#0x05,R5! !
!
!
!
#0x03,R6! !
!
!
!
R6, R5! !
!
!
!

Maths is not ev...
Maths is not everything

CPU
ARM ISA

RMR©2012
ARM versions

Maths is not everything

RMR©2012
ARM core family

Maths is not everything

RMR©2012
ARM Processor Core
— Current low-end ARM core for applications like digital

mobile phones

— TDMI
— T: Thumb, 16-bit i...
ARM programming model

Maths is not everything

RMR©2012

© 2008 Wayne Wolf

r0
r1
r2
r3
r4
r5
r6
r7

r8
r9
r10
r11
r12
r1...
Maths is not everything

RMR©2012

© 2008 Wayne Wolf

ARM core structure
Endianness

Relationship between bit and byte/word
ordering defines endianness:
bit 31

bit 0

byte 3 byte 2 byte 1 byte 0...
ARM data types

Word is 32 bits long.
Word can be divided into four 8-bit
bytes.
ARM addresses can be 32 bits long.

Maths...
ARM states
When the processor is executing in ARM state:
All instructions are 32 bits wide
All instructions must be word a...
Processor Core Vs CPU Core

Processor Core
The engine that fetches instructions and execute them
E.g.: ARM7TDMI, ARM9TDMI,...
ARM status bits

Every arithmetic, logical, or shifting
operation sets CPSR bits:
N (negative), Z (zero), C (carry),V (ove...
ARM data instructions

Basic format:
ADD r0,r1,r2
Computes r1+r2, stores in r0.

Immediate operand:

Maths is not everythi...
ARM data instructions

ADD, ADC
carry)

:

add

(w.

AND, ORR, EOR
BIC : bit clear

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ASL, ASR : arithmetic
shift ...
Data operation varieties

Logical shift:
fills with zeroes.

Arithmetic shift:

Maths is not everything

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© 2008 W...
ARM comparison instructions

CMP : compare
CMN : negated compare
TST : bit-wise test

Maths is not everything

RMR©2012

©...
ARM move instructions

MOV, MVN : move (negated)

Maths is not everything

RMR©2012

© 2008 Wayne Wolf

!
! MOV r0, r1 ; s...
ARM load/store instructions

LDR, LDRH, LDRB : load (half-word, byte)
STR, STRH, STRB : store (half-word,
byte)
Addressing...
ARM ADR pseudo-op

Cannot refer to an address directly in an
instruction.

Maths is not everything

RMR©2012

© 2008 Wayne...
Example: C assignments
x = (a + b) - c;

Assembler:
! ADR r4,a! ! ; get address for a
! LDR r0,[r4]!; get value of a
! ADR...
Example: C assignment
y = a*(b+c);

Assembler:
! ADR r4,b ; get address for b
! LDR r0,[r4] ; get value of b
! ADR r4,c ; ...
Example: C assignment

z = (a << 2) |

(b & 15);

Assembler:
! ADR r4,a ; get address for a
! LDR r0,[r4] ; get value of a...
Additional addressing modes

Base-plus-offset addressing:
LDR r0,[r1,#16]
Loads from location r1+16

Auto-indexing increme...
ARM flow of control

All operations can be performed
conditionally, testing CPSR:
EQ, NE, CS, CC, MI, PL,VS,VC, HI, LS, GE,...
Example: if statement

if (a < b) { x = 5; y = c + d; } else x = c - d;

Assembler:
; compute and test condition
! ADR r4,...
If statement, cont’d.
; true block
! MOV r0,#5 ; generate value for x
! ADR r4,x ; get address for x
! STR r0,[r4] ; store...
If statement, cont’d.

; false block
fblock ADR r4,c ; get address for c
! LDR r0,[r4] ; get value of c
! ADR r4,d ; get a...
Example: Conditional instruction implementation
; true block
! MOVLT r0,#5 ; generate value for x
! ADRLT r4,x ; get addre...
Conditional instruction implementation, cont’d.

; false block
! ADRGE r4,c ; get address for c
! LDRGE r0,[r4] ; get valu...
ARM subroutine linkage

Branch and link instruction:
BL foo
Copies current PC to r14.

To return from subroutine:

Maths i...
Nested subroutine calls

Nesting/recursion requires coding
convention:
f1! LDR r0,[r13] ; load arg into r0 from stack
!
! ...
Maths is not everything

CPU
MSP430 ISA

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MSP430 ISA
RISC/CISC machine
27 orthogonal instructions
8 jump instructions
7 single operand instructions
12 double operan...
MSP 430 Micro-Architecture

Maths is not everything

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46
MSP430 Registers
R0 (PC) – Program Counter
This register always points to the next instruction to be fetched
Each instruct...
MSP430 Registers
R2 (SR/CG1) – Status Register
The status of the MSP430 CPU is contained in register R2
Only accessible th...
MSP430 ALU

16 bit Arithmetic Logic Unit
(ALU).
Performs instruction arithmetic and logical
operations
Instruction executi...
MSP430 Memory Organization

Maths is not everything

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50
MSP430X CPU

Maths is not everything

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51
MSP430X Memory Organization

Maths is not everything

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52
MSP430X Registers

Maths is not everything

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53
MSP430 Instructions

There are three formats used to encode
instructions for processing by the CPU core
Double operand
Sin...
MSP430 Instructions
Memory
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1

14

13

12

11

10

9

8

7

6...
MSP430X Instructions

Maths is not everything

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56
MPS430 Instruction Formats

Format I: Instructions with two operands:
15

14

13

12

11

10

Op-code

9

8

6

Ad

S-reg
...
Format I: Double Operand

Double operand instructions:
Mnemonic

Operation

Description

ADD(.B or .W) src,dst

src+dst→ds...
Example: Double Operand

Copy the contents of a register to
another register
Assembly:	

 mov.w r5,r4
Instruction code:	

...
Format II: Single Operand

Single operand instructions:
Mnemonic

Operation

Description

Logical and register control ins...
Example: Single Operand

Logically shift the contents of register r5 to
the right through the status register carry
Assemb...
Jump Instruction Format
15

14
Op-code

13

12

11

10

Condition

9

8

7

6

5

4

3

2

1

0

10-bit, 2’s complement PC...
Jump Instruction Format
Jump instructions are executed based on the
current PC and the status register
Conditional jumps a...
Example: Jump Format

Continue execution at the label main if
the carry bit is set
Assembly:	

 jc main
Instruction code:	...
Source Addressing Modes

The MSP430 has four modes for the
source address:
00 = Rs - Register
01 = x(Rs) - Indexed Registe...
Destination Addressing Modes

There are two modes for the destination
address:
0 = Rd - Register
1 = x(Rd) - Indexed Regis...
00 = Register Mode

add.w r4,r10
Memory
PC
PC

0x540a

A

ss
ddre

;r10 = r4 + r10

Bus

Data Bus (1

CPU
cycle)

Register...
01 = Indexed Mode

add.w 6(r4),r10 ;r10 = M(r4+6) + r10
Memory
PC
PC
PC

0x541a
0x0006

A

ss
ddre

Bus

CPU

cycle)
Data ...
10 = Indirect Register Mode

add.w @r4,r10
Memory
PC
PC

0x542a

A

ss
ddre

;r10 = M(r4) + r10

Bus

CPU

Data Bus (1

cy...
11 = Indirect Auto-increment Mode

add.w @r4+,r10
Memory
PC
PC

0x543a

A

ss
ddre

Bus

CPU

Data Bus (1

d
Ad

res

s

;...
01 w/R0 = Symbolic Mode (PC Relative)

add.w cte,r10
Memory
PC
PC
PC

0x501a
0x000c

A

ss
ddre

;r10 = M(cte) + r10

Bus
...
01 w/R2 = Absolute Mode

add.w &cte,r10
Memory
PC
PC
PC

0x521a
0xc018

A

ss
ddre

Bus

Data Bus (1

CPU
cycle)

Data Bus...
11 w/R0 = Immediate Mode

add.w #100,r10
Memory
PC
PC
PC

0x503a
0x0064

A

ss
ddre

;r10 = #100 + r10

Bus

CPU

Data Bus...
Constant Generator

add.w #1,r10
Memory
PC
PC

0x531a

A

ss
ddre

;r10 = #1 + r10

Bus

Data Bus (1

CPU
cycle)

Register...
3 Word Instruction (6 cycles)

add.w cte,var
Memory
PC
PC
PC

PC

0x501a
0x000c
0x0218

A

ss
ddre

;var = M(cte) + M(var)...
Addressing Mode Examples

Source

Example
mov r10,r11

Rn x(Rn) Sym &abs @Rn @Rn+ #n Rn x(Rn) Sym &abs Len

3

M(2+r5) → M...
Cycles Per Instruction

Instruction timing:
1 cycle to fetch instruction word
+1 cycle if source is @Rn, @Rn+, or #Imm
+2 ...
Example Cycles Per Instruction

Example

Rm

1

1

@Rn

Rm

2

1

mov @R5+,R0

@Rn+

PC

3

1

add R5,4(R6)

Rn

x(Rm)

4
...
MSP30 µController

Maths is not everything

RMR©2012

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S emb t4-arch_cpu

  1. 1. Maths is not everything Embedded Systems 4 - Hardware Architecture CPU Input/Output mechanisms Memory Buses And Aux Input/Output interfaces RMR©2012 Power Management
  2. 2. Maths is not everything CPU ISA - Introduction RMR©2012
  3. 3. Instruction Set Architecture The computer ISA defines all of the programmer-visible components and operations of the computer Maths is not everything RMR©2012 3 © 2008 Wayne Wolf Memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? Register set how many? what size? how are they used? Instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language).
  4. 4. von Neumann architecture Memory holds data & instructions. Central processing unit (CPU) fetches instructions from memory. Separate CPU and memory distinguishes programmable computer. Maths is not everything RMR©2012 © 2008 Wayne Wolf CPU registers help out: program counter (PC), instruction register (IR), generalpurpose registers, etc.
  5. 5. CPU + memory address memory data 200 PC CPU Maths is not everything RMR©2012 © 2008 Wayne Wolf 200 ADD r5,r1,r3 IR ADD r5,r1,r3
  6. 6. Harvard architecture address data memory data address Maths is not everything RMR©2012 © 2008 Wayne Wolf program memory data PC CPU
  7. 7. von Neumann vs. Harvard Harvard can’t use self-modifying code. Harvard allows two simultaneous memory fetches. Most DSPs use Harvard architecture for streaming data: Maths is not everything RMR©2012 © 2008 Wayne Wolf greater memory bandwidth; more predictable bandwidth.
  8. 8. RISC vs. CISC Complex instruction set computer (CISC): many addressing modes; many operations. Reduced instruction set computer (RISC): load/store; Maths is not everything RMR©2012 © 2008 Wayne Wolf pipelinable instructions.
  9. 9. Instruction set characteristics Maths is not everything RMR©2012 © 2008 Wayne Wolf Fixed vs. variable length. Addressing modes. Number of operands. Types of operands.
  10. 10. Multiple implementations Successful architectures have several implementations: varying clock speeds; different bus widths; Maths is not everything RMR©2012 © 2008 Wayne Wolf different cache sizes; ...
  11. 11. Assembly language Basic features: One instruction per line. Labels provide names for addresses (usually in first column). Instructions often start in later columns. Maths is not everything RMR©2012 © 2008 Wayne Wolf Columns run to end of line.
  12. 12. ARM assembly language example header LDR r1,[r4] SUB r0,r0,r1 MOV sp,#INIT_SP ADR lr, start+1 BX lr start CODE16 ; 3 addresses instruction ; set-up stack pointer ; Processor starts in ARM state, ; so small ARM code header used ; to call Thumb main program. ; Subsequent instructions are Thumb. Maths is not everything RMR©2012 © 2008 Wayne Wolf ;********************************************************************** ;* This an example of 16 bits code (Thumb mode) ;********************************************************************** BL forever BL MOV BL chksw0 BL AND BEQ irq_init ; init. interrupts seg_rot r0,#0xf leds_on ; check display of hex digits sw_rd r0,r0 chksw0 ; read DIP_SW port, r0 carries word ; check if any DIP_SW has been mod. ; if not, keep checking ; sw on the leds
  13. 13. MSP430 assembly language example MOV.w MOV.w CMP.w! #0x05,R5! ! ! ! ! #0x03,R6! ! ! ! ! R6, R5! ! ! ! ! Maths is not everything RMR©2012 © 2008 Wayne Wolf JNE! somewhere! ! ! ; ; ; ; ; ; move source to destination assign a hexadecimal value 0x05 to Register R5 move source to destination assign a hexadecimal value 0x03 to Register R6 compare source to destination R5-R6 = 5-3 = 2 greater than 0, so R5 > R6 ; jump if not equal ; The program will jump to “somewhere” because R5 ≠ R6
  14. 14. Maths is not everything CPU ARM ISA RMR©2012
  15. 15. ARM versions Maths is not everything RMR©2012
  16. 16. ARM core family Maths is not everything RMR©2012
  17. 17. ARM Processor Core — Current low-end ARM core for applications like digital mobile phones — TDMI — T: Thumb, 16-bit instruction set — D: on-chip Debug support, enabling the processor to halt in response to a debug request — M: enhanced Multiplier, yield a full 64-bit result, high performance — I: EmbeddedICE hardware Maths is not everything RMR©2012 6 — Von Neumann architecture — 3-stage pipeline
  18. 18. ARM programming model Maths is not everything RMR©2012 © 2008 Wayne Wolf r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 31 Status Register 0 CPSR N Z CV link reg. in BL r15 (PC) sp for procedure linkage
  19. 19. Maths is not everything RMR©2012 © 2008 Wayne Wolf ARM core structure
  20. 20. Endianness Relationship between bit and byte/word ordering defines endianness: bit 31 bit 0 byte 3 byte 2 byte 1 byte 0 Maths is not everything RMR©2012 © 2008 Wayne Wolf little-endian bit 31 bit 0 byte 0 byte 1 byte 2 byte 3 big-endian
  21. 21. ARM data types Word is 32 bits long. Word can be divided into four 8-bit bytes. ARM addresses can be 32 bits long. Maths is not everything RMR©2012 © 2008 Wayne Wolf Address refers to byte. Address 4 starts at byte 4. Can be configured at power-up as either little- or big-endian mode.
  22. 22. ARM states When the processor is executing in ARM state: All instructions are 32 bits wide All instructions must be word aligned When the processor is executing in Thumb state: All instructions are 16 bits wide All instructions must be halfword aligned Maths is not everything RMR©2012 © 2008 Wayne Wolf When the processor is executing in Jazelle state: All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once
  23. 23. Processor Core Vs CPU Core Processor Core The engine that fetches instructions and execute them E.g.: ARM7TDMI, ARM9TDMI, ARM9E-S Maths is not everything RMR©2012 15 © 2008 Wayne Wolf CPU Core Consists of the ARM processor core and some tightly coupled function blocks Cache and memory management blocks E.g.: ARM710T, ARM720T, ARM74T, ARM920T, ARM922T, ARM940T, ARM946E-S, and ARM966E-S ARM710T
  24. 24. ARM status bits Every arithmetic, logical, or shifting operation sets CPSR bits: N (negative), Z (zero), C (carry),V (overflow). Maths is not everything RMR©2012 © 2008 Wayne Wolf Examples: -1 + 1 = 0: NZCV = 0110. 231-1+1 = -231: NZCV = 0101.
  25. 25. ARM data instructions Basic format: ADD r0,r1,r2 Computes r1+r2, stores in r0. Immediate operand: Maths is not everything RMR©2012 © 2008 Wayne Wolf ADD r0,r1,#2 Computes r1+2, stores in r0.
  26. 26. ARM data instructions ADD, ADC carry) : add (w. AND, ORR, EOR BIC : bit clear RMR©2012 ASL, ASR : arithmetic shift left/right MUL, MLA : multiply (and accumulate) Maths is not everything LSL, LSR : logical shift left/right RSB, RSC : reverse subtract (w. carry) © 2008 Wayne Wolf SUB, SBC : subtract (w. carry) ROR : rotate right RRX : rotate right extended with C
  27. 27. Data operation varieties Logical shift: fills with zeroes. Arithmetic shift: Maths is not everything RMR©2012 © 2008 Wayne Wolf fills with ones. RRX performs 33-bit rotate, including C bit from CPSR above sign bit.
  28. 28. ARM comparison instructions CMP : compare CMN : negated compare TST : bit-wise test Maths is not everything RMR©2012 © 2008 Wayne Wolf TEQ : bit-wise negated test These instructions set only the NZCV bits of CPSR.
  29. 29. ARM move instructions MOV, MVN : move (negated) Maths is not everything RMR©2012 © 2008 Wayne Wolf ! ! MOV r0, r1 ; sets r0 to r1
  30. 30. ARM load/store instructions LDR, LDRH, LDRB : load (half-word, byte) STR, STRH, STRB : store (half-word, byte) Addressing modes: Maths is not everything RMR©2012 © 2008 Wayne Wolf register indirect : LDR r0,[r1] with second register : LDR r0,[r1,-r2] with constant : LDR r0,[r1,#4]
  31. 31. ARM ADR pseudo-op Cannot refer to an address directly in an instruction. Maths is not everything RMR©2012 © 2008 Wayne Wolf Generate value by performing arithmetic on PC. ADR pseudo-op generates instruction required to calculate address: ADR r1,FOO
  32. 32. Example: C assignments x = (a + b) - c; Assembler: ! ADR r4,a! ! ; get address for a ! LDR r0,[r4]!; get value of a ! ADR r4,b! ! ; get address for b, reusing r4 ! LDR r1,[r4]!; get value of b ! ADD r3,r0,r1! compute a+b ; ! ADR r4,c! ! ; get address for c ! LDR r2[r4]! ; get value of c Maths is not everything © 2008 Wayne Wolf SUB r3,r3,r2! complete computation of x ; ! ADR r4,x! ! ; get address for x ! STR r3,[r4]!; store value of x RMR©2012
  33. 33. Example: C assignment y = a*(b+c); Assembler: ! ADR r4,b ; get address for b ! LDR r0,[r4] ; get value of b ! ADR r4,c ; get address for c ! LDR r1,[r4] ; get value of c ! ADD r2,r0,r1 ; compute partial result ! ADR r4,a ; get address for a ! LDR r0,[r4] ; get value of a Maths is not everything RMR©2012 © 2008 Wayne Wolf ! MUL r2,r2,r0 ; compute final value for y ! ADR r4,y ; get address for y ! STR r2,[r4] ; store y
  34. 34. Example: C assignment z = (a << 2) | (b & 15); Assembler: ! ADR r4,a ; get address for a ! LDR r0,[r4] ; get value of a ! MOV r0,r0,LSL 2 ; perform shift ! ADR r4,b ; get address for b ! LDR r1,[r4] ; get value of b ! AND r1,r1,#15 ; perform AND Maths is not everything © 2008 Wayne Wolf ! ORR r1,r0,r1 ; perform OR ! ADR r4,z ; get address for z ! STR r1,[r4] ; store value for z RMR©2012
  35. 35. Additional addressing modes Base-plus-offset addressing: LDR r0,[r1,#16] Loads from location r1+16 Auto-indexing increments base register: LDR r0,[r1,#16]! Maths is not everything RMR©2012 © 2008 Wayne Wolf Post-indexing fetches, then does offset: LDR r0,[r1],#16 Loads r0 from r1, then adds 16 to r1.
  36. 36. ARM flow of control All operations can be performed conditionally, testing CPSR: EQ, NE, CS, CC, MI, PL,VS,VC, HI, LS, GE, LT, GT, LE Branch operation: Maths is not everything RMR©2012 © 2008 Wayne Wolf B #100 Can be performed conditionally.
  37. 37. Example: if statement if (a < b) { x = 5; y = c + d; } else x = c - d; Assembler: ; compute and test condition ! ADR r4,a ; get address for a ! LDR r0,[r4] ; get value of a ! ADR r4,b ; get address for b ! LDR r1,[r4] ; get value for b ! CMP r0,r1 ; compare a < b Maths is not everything RMR©2012 © 2008 Wayne Wolf ! BGE fblock ; if a >= b, branch to false block
  38. 38. If statement, cont’d. ; true block ! MOV r0,#5 ; generate value for x ! ADR r4,x ; get address for x ! STR r0,[r4] ; store x ! ADR r4,c ; get address for c ! LDR r0,[r4] ; get value of c ! ADR r4,d ; get address for d ! LDR r1,[r4] ; get value of d ! ADD r0,r0,r1 ; compute y Maths is not everything © 2008 Wayne Wolf ! ADR r4,y ; get address for y ! STR r0,[r4] ; store y ! B after ; branch around false block RMR©2012
  39. 39. If statement, cont’d. ; false block fblock ADR r4,c ; get address for c ! LDR r0,[r4] ; get value of c ! ADR r4,d ; get address for d ! LDR r1,[r4] ; get value for d ! SUB r0,r0,r1 ; compute a-b Maths is not everything © 2008 Wayne Wolf ! ADR r4,x ; get address for x ! STR r0,[r4] ; store value of x after ... RMR©2012
  40. 40. Example: Conditional instruction implementation ; true block ! MOVLT r0,#5 ; generate value for x ! ADRLT r4,x ; get address for x ! STRLT r0,[r4] ; store x ! ADRLT r4,c ; get address for c ! LDRLT r0,[r4] ; get value of c ! ADRLT r4,d ; get address for d ! LDRLT r1,[r4] ; get value of d ! ADDLT r0,r0,r1 ; compute y Maths is not everything RMR©2012 © 2008 Wayne Wolf ! ADRLT r4,y ; get address for y ! STRLT r0,[r4] ; store y
  41. 41. Conditional instruction implementation, cont’d. ; false block ! ADRGE r4,c ; get address for c ! LDRGE r0,[r4] ; get value of c ! ADRGE r4,d ; get address for d ! LDRGE r1,[r4] ; get value for d ! SUBGE r0,r0,r1 ; compute a-b Maths is not everything RMR©2012 © 2008 Wayne Wolf ! ADRGE r4,x ; get address for x ! STRGE r0,[r4] ; store value of x
  42. 42. ARM subroutine linkage Branch and link instruction: BL foo Copies current PC to r14. To return from subroutine: Maths is not everything RMR©2012 © 2008 Wayne Wolf MOV r15,r14
  43. 43. Nested subroutine calls Nesting/recursion requires coding convention: f1! LDR r0,[r13] ; load arg into r0 from stack ! ! ! ; call f2() ! ! STR r14,[r13]! ; store f1’s return adrs ! ! STR r0,[r13]! ; store arg to f2 on stack ! ! BL f2 ; branch and link to f2 ! ! ; return from f1() Maths is not everything RMR©2012 © 2008 Wayne Wolf ! ! SUB r13,#4 ; pop f2’s arg off stack ! ! LDR r15,[r13]#-4 ; restore register and return
  44. 44. Maths is not everything CPU MSP430 ISA RMR©2012
  45. 45. MSP430 ISA RISC/CISC machine 27 orthogonal instructions 8 jump instructions 7 single operand instructions 12 double operand instructions 7 addressing modes. 8/16-bit instruction addressing formats. Memory architecture 16 16-bit registers 16-bit Arithmetic Logic Unit (ALU). Maths is not everything 16-bit address bus (64K address space) 16-bit data bus (8-bit addressability) RMR©2012 45 8/16-bit peripherals
  46. 46. MSP 430 Micro-Architecture Maths is not everything RMR©2012 46
  47. 47. MSP430 Registers R0 (PC) – Program Counter This register always points to the next instruction to be fetched Each instruction occupies an even number of bytes. Therefore, the least significant bit (LSB) of the PC register is always zero. After fetch of an instruction, the PC register is incremented by 2, 4, or 6 to point to the next instruction. R1 (SP) – Stack Pointer The MSP430 CPU stores the return address of routines or interrupts on the stack User programs store local data on the stack The SP can be incremented or decremented automatically with each stack access Maths is not everything RMR©2012 47 The stack “grows down” thru RAM and thus SP must be initialized with a valid RAM address SP always points to an even address, so its LSB is always zero
  48. 48. MSP430 Registers R2 (SR/CG1) – Status Register The status of the MSP430 CPU is contained in register R2 Only accessible through register addressing mode - all other addressing modes are reserved to support the constants generator V SCG1 GIE General interrupt enable N Negative bit Zero bit C 48 Turns off the CPU. Z R4-R15 – General Purpose registers Oscillator off CPUOFF RMR©2012 Turns off the DCO dc generator. OSCOFF Maths is not everything Turns off the SMCLK. SCG0 R3 (CG2) – Constant Generator Overflow bit Carry bit
  49. 49. MSP430 ALU 16 bit Arithmetic Logic Unit (ALU). Performs instruction arithmetic and logical operations Instruction execution affects the state of the following flags: Zero (Z) Carry (C) Overflow (V) Negative (N) Maths is not everything RMR©2012 49 The MCLK (Master) clock signal drives the CPU.
  50. 50. MSP430 Memory Organization Maths is not everything RMR©2012 50
  51. 51. MSP430X CPU Maths is not everything RMR©2012 51
  52. 52. MSP430X Memory Organization Maths is not everything RMR©2012 52
  53. 53. MSP430X Registers Maths is not everything RMR©2012 53
  54. 54. MSP430 Instructions There are three formats used to encode instructions for processing by the CPU core Double operand Single operand Jumps Maths is not everything RMR©2012 54 The instructions for double and single operands, depend on the suffix used, (.w) word or (.b) byte These suffixes allow word or byte data access If the suffix is ignored, the instruction processes word data by default
  55. 55. MSP430 Instructions Memory 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 14 13 12 11 10 9 8 7 6 5 4 PC jc main 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 15 rrc.w r5 0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 Instruction Register mov.w r5,r4 mov.w #0x0600,r1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 3 2 1 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 Op-code 4 to 16 Decoder Maths is not everything RMR©2012 55 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Op-code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Instruction Undefined RCC, SWPB, RRA, SXT, PUSH, CALL, RETI JNE, JEQ, JNC, JC JN, JGE, JL, JMP MOV ADD ADDC SUBC SUB CMP DADD BIT BIC BIS XOR AND Format Single Operand Jumps Double Operand
  56. 56. MSP430X Instructions Maths is not everything RMR©2012 56
  57. 57. MPS430 Instruction Formats Format I: Instructions with two operands: 15 14 13 12 11 10 Op-code 9 8 6 Ad S-reg 7 5 b/w 4 3 2 As 1 0 D-reg Format II: Instruction with one operand: 15 14 13 12 11 10 9 8 7 Op-code 6 5 b/w 4 3 2 Ad 1 0 D/S-reg Format III: Jump instructions: 15 Maths is not everything RMR©2012 57 14 Op-code 13 12 11 10 Condition 9 8 7 6 5 4 3 2 1 10-bit, 2’s complement PC offset 0
  58. 58. Format I: Double Operand Double operand instructions: Mnemonic Operation Description ADD(.B or .W) src,dst src+dst→dst Add source to destination ADDC(.B or .W) src,dst src+dst+C→dst Add source and carry to destination DADD(.B or .W) src,dst src+dst+C→dst (dec) Decimal add source and carry to destination SUB(.B or .W) src,dst dst+.not.src+1→dst Subtract source from destination SUBC(.B or .W) src,dst dst+.not.src+C→dst Subtract source and not carry from destination Arithmetic instructions Logical and register control instructions AND(.B or .W) src,dst src.and.dst→dst AND source with destination BIC(.B or .W) src,dst .not.src.and.dst→dst Clear bits in destination BIS(.B or .W) src,dst src.or.dst→dst Set bits in destination BIT(.B or .W) src,dst src.and.dst Test bits in destination XOR(.B or .W) src,dst src.xor.dst→dst XOR source with destination CMP(.B or .W) src,dst dst-src Compare source to destination MOV(.B or .W) src,dst src→dst Move source to destination Data instructions Maths is not everything RMR©2012 58
  59. 59. Example: Double Operand Copy the contents of a register to another register Assembly: mov.w r5,r4 Instruction code: 0x4504 Op-code mov S-reg r5 Ad Register b/w 16-bits As Register D-reg r4 0100 0101 0 0 00 0100 One word instruction Maths is not everything RMR©2012 59 The instruction instructs the CPU to copy the 16-bit 2’s complement number in register r5 to register r4
  60. 60. Format II: Single Operand Single operand instructions: Mnemonic Operation Description Logical and register control instructions RRA(.B or .W) dst MSB→MSB→… LSB→C Roll destination right RRC(.B or .W) dst C→MSB→…LSB→C Roll destination right through carry SWPB( or .W) dst Swap bytes Swap bytes in destination SXT dst bit 7→bit 8…bit 15 Sign extend destination PUSH(.B or .W) src SP-2→SP, src→@SP Push source on stack Program flow control instructions Maths is not everything CALL(.B or .W) dst SP-2→SP, PC+2→@SP dst→PC RETI RMR©2012 60 @SP+→SR, @SP+→SP Subroutine call to destination Return from interrupt
  61. 61. Example: Single Operand Logically shift the contents of register r5 to the right through the status register carry Assembly: rrc.w r5 Instruction code: 0x1005 Op-code rrc b/w 16-bits Ad Register D-reg r5 000100000 0 00 0101 One word instruction Maths is not everything RMR©2012 61 The CPU shifts the 16-bit register r5 one bit to the right (divide by 2) – the carry bit prior to the instruction becomes the MSB of the result while the LSB shifted out replaces the carry bit in the status register
  62. 62. Jump Instruction Format 15 14 Op-code 13 12 11 10 Condition 9 8 7 6 5 4 3 2 1 0 10-bit, 2’s complement PC offset Jump instructions are used to direct program flow to another part of the program. The condition on which a jump occurs depends on the Condition field consisting of 3 bits: Maths is not everything RMR©2012 62 000: jump if not equal 001: jump if equal 010: jump if carry flag equal to zero 011: jump if carry flag equal to one 100: jump if negative (N = 1) 101: jump if greater than or equal (N = V) 110: jump if lower (N ≠ V) 111: unconditional jump
  63. 63. Jump Instruction Format Jump instructions are executed based on the current PC and the status register Conditional jumps are controlled by the status bits Status bits are not changed by a jump instruction The jump off-set is represented by the 10-bit, 2’s complement value: Maths is not everything RMR©2012 63 Thus, the range of the jump is -511 to +512 words, (-1023 to 1024 bytes ) from the current instruction Note: Use a BR instruction to jump to any address
  64. 64. Example: Jump Format Continue execution at the label main if the carry bit is set Assembly: jc main Instruction code: 0x2fe4 Op-code JC Condition Carry Set 10-Bit, 2’s complement PC offset -28 001 011 1111100100 One word instruction Maths is not everything RMR©2012 64 The CPU will add to the incremented PC (R0) the value -28 x 2 if the carry is set
  65. 65. Source Addressing Modes The MSP430 has four modes for the source address: 00 = Rs - Register 01 = x(Rs) - Indexed Register 10 = @Rs - Register Indirect 11 = @Rs+ - Indirect Auto-increment In combination with registers R0-R3, three additional source addressing modes are available: Maths is not everything RMR©2012 65 label - PC Relative, x(PC) &label – Absolute, x(SR) #n – Immediate, @PC+
  66. 66. Destination Addressing Modes There are two modes for the destination address: 0 = Rd - Register 1 = x(Rd) - Indexed Register In combination with registers R0/R2, two additional destination addressing modes are available: label - PC Relative, x(PC) Maths is not everything RMR©2012 66 &label – Absolute, x(SR)
  67. 67. 00 = Register Mode add.w r4,r10 Memory PC PC 0x540a A ss ddre ;r10 = r4 + r10 Bus Data Bus (1 CPU cycle) Registers 0x540a IR PC R4 ADDER R10 ALU Maths is not everything RMR©2012 67
  68. 68. 01 = Indexed Mode add.w 6(r4),r10 ;r10 = M(r4+6) + r10 Memory PC PC PC 0x541a 0x0006 A ss ddre Bus CPU cycle) Data Bus (1 Registers 0x541a IR PC Data Bus (+1 cycle) R4 Address Bus ADDER R10 Data Bus (+1 cycle ) ALU Maths is not everything RMR©2012 68
  69. 69. 10 = Indirect Register Mode add.w @r4,r10 Memory PC PC 0x542a A ss ddre ;r10 = M(r4) + r10 Bus CPU Data Bus (1 cycle) Registers 0x542a IR PC Addre Data Bus s R4 s Bus ADDER R10 (+1 cycle ) ALU Maths is not everything RMR©2012 69
  70. 70. 11 = Indirect Auto-increment Mode add.w @r4+,r10 Memory PC PC 0x543a A ss ddre Bus CPU Data Bus (1 d Ad res s ;r10 = M(r4+) + r10 cycle) Registers 0x543a IR PC s Bu 0002 R4 ADDER R10 Data Bus (+1 cycle ) ALU Maths is not everything RMR©2012 70
  71. 71. 01 w/R0 = Symbolic Mode (PC Relative) add.w cte,r10 Memory PC PC PC 0x501a 0x000c A ss ddre ;r10 = M(cte) + r10 Bus CPU cycle) Data Bus (1 0x501a IR PC Registers PC Data Bus (+1 cycle) Address Bus ADDER R10 Data Bus (+1 cycle ) ALU Maths is not everything RMR©2012 71
  72. 72. 01 w/R2 = Absolute Mode add.w &cte,r10 Memory PC PC PC 0x521a 0xc018 A ss ddre Bus Data Bus (1 CPU cycle) Data Bus (+1 cycle) Data Bus RMR©2012 72 Registers 0x521a IR PC Address Maths is not everything ;r10 = M(cte) + r10 Bus 0000 ADDER R10 (+1 cycle ) ALU
  73. 73. 11 w/R0 = Immediate Mode add.w #100,r10 Memory PC PC PC 0x503a 0x0064 A ss ddre ;r10 = #100 + r10 Bus CPU Data Bus (1 cycle) Registers 0x503a IR PC Dat aB us (+ 1c ycl e) ADDER R10 ALU Maths is not everything RMR©2012 73
  74. 74. Constant Generator add.w #1,r10 Memory PC PC 0x531a A ss ddre ;r10 = #1 + r10 Bus Data Bus (1 CPU cycle) Registers 0x531a IR ADDER 0000 0001 0002 0004 0008 ffff ALU Maths is not everything RMR©2012 74 PC R10
  75. 75. 3 Word Instruction (6 cycles) add.w cte,var Memory PC PC PC PC 0x501a 0x000c 0x0218 A ss ddre ;var = M(cte) + M(var) Bus CPU Data Bus (1 cycle) 0x501a IR PC Data Bus (+1 cycle) Data Bus (+1 cycle) Address Data Bus Bus (+1 cycle ADDER ) Address Bus Data Bus (+1 cycle) Maths is not everything RMR©2012 75 Data Bus (+1 cycl e) ALU Registers PC
  76. 76. Addressing Mode Examples Source Example mov r10,r11 Rn x(Rn) Sym &abs @Rn @Rn+ #n Rn x(Rn) Sym &abs Len 3 M(2+r5) → M(6+r6) 3 M(EDE) → M(TONI) 3 M(MEM) → M(TCDAT) 1 M(r10) → r11 2 M(r10) → M(tab+r6) , r10+2 → r10 3 #45 → M(TONI) 2 #2 → M(MEM) 1 #1 → r11 • 2 #45 → r11 • • • mov @r10,r11 • • mov @r10+,tab(r6) • • mov #45,TONI • • mov #2,&MEM mov #1,r11 C • C mov #45,r11 76 r10 → r11 • mov &MEM,&TCDAT RMR©2012 1 • • mov EDE,TONI Operation • • mov 2(r5),6(r6) Maths is not everything Destination • •
  77. 77. Cycles Per Instruction Instruction timing: 1 cycle to fetch instruction word +1 cycle if source is @Rn, @Rn+, or #Imm +2 cycles if source uses indexed mode 1st to fetch base address 2nd to fetch source Includes absolute and symbolic modes Maths is not everything RMR©2012 77 +2 cycles if destination uses indexed mode +1 cycle if writing destination back to memory +1 cycle if writing to PC (R0) Jump instructions are always 2 cycles
  78. 78. Example Cycles Per Instruction Example Rm 1 1 @Rn Rm 2 1 mov @R5+,R0 @Rn+ PC 3 1 add R5,4(R6) Rn x(Rm) 4 2 add R8,EDE Rn EDE 4 2 add R5,&EDE Rn &EDE 4 2 add #100,TAB(R8) 78 Rn add @R5,R6 RMR©2012 Dst add R5,R8 Maths is not everything Src #n x(Rm) 5 3 add &TONI,&EDE &TONI &EDE 6 3 add #1,&EDE #1 4 2 &EDE Cycles Length
  79. 79. MSP30 µController Maths is not everything RMR©2012 79

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