Cache Memory

2. • Defination
• Working
• Level
• Organization
• Application
INTRODUCTION
• Direct Mapping
• Associative Mapping
• Set-associative Mapping
MAPPING TECHNIQUES
CACHE COHERENCY
• Spatial Locality of reference
• Temporal Locality of reference
LOCALITY OF REFERENCE
CACHE PERFORMANCE

3. Cache memory is a small-sized type of volatile computer
memory that provides high-speed data access to a
processor and stores frequently used computer programs,
applications and data.
It stores and retains data only until a computer is powered
up.
Cache memory is used to reduce the average time to
access data from the Main memory.
The cache is a smaller and faster memory which stores
copies of the data from frequently used main memory
locations.

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6. • A LEVEL 1 CACHE (L1 CACHE) IS A MEMORY CACHE THAT IS DIRECTLY BUILT
INTO THE MICROPROCESSOR, WHICH IS USED FOR STORING THE
MICROPROCESSOR’S RECENTLY ACCESSED INFORMATION, THUS IT IS ALSO
CALLED THE PRIMARY CACHE.
• IT IS ALSO REFERRED TO AS THE INTERNAL CACHE OR SYSTEM CACHE.
• L1 CACHE IS THE FASTEST CACHE MEMORY, SINCE IT IS ALREADY BUILT
WITHIN THE CHIP WITH A ZERO WAIT-STATE INTERFACE, MAKING IT THE MOST
EXPENSIVE CACHE AMONG THE CPU CACHES.
• IT IS USED TO STORE DATA THAT WAS ACCESSED BY THE PROCESSOR
RECENTLY, CRITICAL FILES THAT NEED TO BE EXECUTED IMMEDIATELY AND IT
IS THE FIRST CACHE TO BE ACCESSED AND PROCESSED WHEN THE
PROCESSOR ITSELF PERFORMS A COMPUTER INSTRUCTION.
• IN MORE RECENT MICROPROCESSORS, THE L1 CACHE IS DIVIDED EQUALLY
INTO TWO: A CACHE THAT IS USED TO KEEP PROGRAM DATA AND ANOTHER
CACHE THAT IS USED TO KEEP INSTRUCTIONS FOR THE MICROPROCESSOR.
• IT IS IMPLEMENTED WITH THE USE OF STATIC RANDOM ACCESS MEMORY
(SRAM), WHICH COMES IN DIFFERENT SIZES DEPENDING ON THE GRADE OF
THE PROCESSOR.

7. • A LEVEL 2 CACHE (L2 CACHE) IS A CPU CACHE MEMORY THAT IS LOCATED
OUTSIDE AND SEPARATE FROM THE MICROPROCESSOR CHIP CORE,
• ALTHOUGH, IT IS FOUND ON THE SAME PROCESSOR CHIP PACKAGE. EARLIER
L2 CACHE DESIGNS PLACED THEM ON THE MOTHERBOARD WHICH MADE
THEM QUITE SLOW.
• INCLUDING L2 CACHES IN MICROPROCESSOR DESIGNS ARE VERY COMMON
IN MODERN CPUS EVEN THOUGH THEY MAY NOT BE AS FAST AS THE L1
CACHE, BUT SINCE IT IS OUTSIDE OF THE CORE, THE CAPACITY CAN BE
INCREASED AND IT IS STILL FASTER THAN THE MAIN MEMORY.
• A LEVEL 2 CACHE IS ALSO CALLED THE SECONDARY CACHE OR AN EXTERNAL
CACHE.
• THE LEVEL 2 CACHE SERVES AS THE BRIDGE FOR THE PROCESS AND
MEMORY PERFORMANCE GAP.
• ITS MAIN GOAL IS TO PROVIDE THE NECESSARY STORED INFORMATION TO
THE PROCESSOR WITHOUT ANY INTERRUPTIONS OR ANY DELAYS OR WAIT-
STATES.
• MODERN MICROPROCESSORS SOMETIMES INCLUDE A FEATURE CALLED DATA
PRE-FETCHING, AND THE L2 CACHE BOOSTS THIS FEATURE BY BUFFERING
THE PROGRAM INSTRUCTIONS AND DATA THAT IS REQUESTED BY THE
PROCESSOR FROM THE MEMORY, SERVING AS A CLOSER WAITING AREA
COMPARED TO THE RAM.

8. • A LEVEL 3 (L3) CACHE IS A SPECIALIZED CACHE THAT
THAT IS USED BY THE CPU AND IS USUALLY BUILT ONTO
THE MOTHERBOARD AND, IN CERTAIN SPECIAL
PROCESSORS, WITHIN THE CPU MODULE ITSELF.
• IT WORKS TOGETHER WITH THE L1 AND L2 CACHE TO
IMPROVE COMPUTER PERFORMANCE BY PREVENTING
BOTTLENECKS DUE TO THE FETCH AND EXECUTE CYCLE
TAKING TOO LONG.
• THE L3 CACHE IS USUALLY BUILT ONTO THE
MOTHERBOARD BETWEEN THE MAIN MEMORY (RAM) AND
THE L1 AND L2 CACHES OF THE PROCESSOR MODULE.
• THIS SERVES AS ANOTHER BRIDGE TO PARK INFORMATION
LIKE PROCESSOR COMMANDS AND FREQUENTLY USED
DATA IN ORDER TO PREVENT BOTTLENECKS RESULTING
FROM THE FETCHING OF THESE DATA FROM THE MAIN
MEMORY.

9. • USUALLY, THE CACHE MEMORY CAN STORE A
REASONABLE NUMBER OF BLOCKS AT ANY
GIVEN TIME, BUT THIS NUMBER IS SMALL
COMPARED TO THE TOTAL NUMBER OF BLOCKS
IN THE MAIN MEMORY.
• THE CORRESPONDENCE BETWEEN THE MAIN
MEMORY BLOCKS AND THOSE IN THE CACHE IS
SPECIFIED BY A MAPPING FUNCTION.
• A PRIMARY CACHE IS ALWAYS LOCATED ON THE
PROCESSOR CHIP. THIS CACHE IS SMALL AND ITS
ACCESS TIME IS COMPARABLE TO THAT OF
PROCESSOR REGISTERS.
• SECONDARY CACHE IS PLACED BETWEEN THE
PRIMARY CACHE AND THE REST OF THE MEMORY. IT
IS REFERRED TO AS THE LEVEL 2 (L2) CACHE.
OFTEN, THE LEVEL 2 CACHE IS ALSO HOUSED ON
THE PROCESSOR CHIP.

10. The transformation of data
from the main memory to
the cache memory is
referred to as cache
memory mapping.

11. • THE SIMPLEST TECHNIQUE, KNOWN AS DIRECT MAPPING, MAPS EACH BLOCK OF MAIN MEMORY INTO ONLY ONE POSSIBLE
CACHE LINE.
• IN DIRECT MAPPING, ASSIGNED EACH MEMORY BLOCK TO A SPECIFIC LINE IN THE CACHE.
• IF A LINE IS PREVIOUSLY TAKEN UP BY A MEMORY BLOCK WHEN A NEW BLOCK NEEDS TO BE LOADED, THE OLD BLOCK IS
TRASHED.
• AN ADDRESS SPACE IS SPLIT INTO TWO PARTS INDEX FIELD AND TAG FIELD.
• THE CACHE IS USED TO STORE THE TAG FIELD WHEREAS THE REST IS STORED IN THE MAIN MEMORY.

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15. Address length = (s + w) bitsAddress
Number of addressable units = 2s+w words or bytesNumber
Block size = line size = 2w words or bytesBlock
Number of lines in cache = m = 2rNumber
Size of tag = (s – r) bitsSize

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20. Address length = (s + w) bitsAddress
Number of addressable units = 2s+w words or bytesNumber
Block size = line size = 2w words or bytesBlock
Number of lines in cache = undeterminedNumber
Size of tag = s bitsSize

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25. Address length = (s + w) bitsAddress
Number of addressable units = 2s+w words or bytesNumber
Block size = line size = 2w words or bytesBlock
Number of blocks in main memory = 2dNumber
Number of lines in set = kNumber
Number of sets = v = 2dNumber
Size of tag = (s – d) bitsSize

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28. • LOCALITY OF REFERENCE REFERS TO A PHENOMENON IN
WHICH A COMPUTER PROGRAM TENDS TO ACCESS SAME SET
OF MEMORY LOCATIONS FOR A PARTICULAR TIME PERIOD.
• LOCALITY OF REFERENCE REFERS TO THE TENDENCY OF
THE COMPUTER PROGRAM TO ACCESS INSTRUCTIONS
WHOSE ADDRESSES ARE NEAR ONE ANOTHER.
• THE PROPERTY OF LOCALITY OF REFERENCE IS MAINLY
SHOWN BY LOOPS AND SUBROUTINE CALLS IN A PROGRAM.

29. • IN CASE OF LOOPS IN PROGRAM
CONTROL PROCESSING UNIT
REPEATEDLY REFERS TO THE SET OF
INSTRUCTIONS THAT CONSTITUTE THE
LOOP.
• IN CASE OF SUBROUTINE CALLS,
EVERYTIME THE SET OF
INSTRUCTIONS ARE FETCHED FROM
MEMORY.
• REFERENCES TO DATA ITEMS ALSO
GET LOCALIZED THAT MEANS SAME
DATA ITEM IS REFERENCED AGAIN AND
AGAIN.

30. •IN FIGURE, YOU CAN SEE THAT CPU WANTS TO READ OR
FETCH THE DATA OR INSTRUCTION.FIRST IT WILL ACCESS
THE CACHE MEMORY AS IT IS NEAR TO IT AND PROVIDES
VERY FAST ACCESS. IF THE REQUIRED DATA OR
INSTRUCTION IS FOUND, IT WILL BE FETCHED. THIS
SITUATION IS KNOWN AS CACHE HIT. BUT IF THE REQUIRED
DATA OR INSTRUCTION IS NOT FOUND IN THE CACHE
MEMORY THEN THIS SITUATION IS KNOWN AS CACHE
MISS.NOW THE MAIN MEMORY WILL BE SEARCHED FOR
THE REQUIRED DATA OR INSTRUCTION THAT WAS BEING
SEARCHED AND IF FOUND WILL GO THROUGH ONE OF THE
TWO WAYS:
•FIRST WAY IS THAT THE CPU SHOULD FETCH THE
REQUIRED DATA OR INSTRUCTION AND USE IT AND THAT’S
IT BUT WHAT, WHEN THE SAME DATA OR INSTRUCTION IS
REQUIRED AGAIN.CPU AGAIN HAS TO ACCESS SAME MAIN
MEMORY LOCATION FOR IT AND WE ALREADY KNOW THAT
MAIN MEMORY IS THE SLOWEST TO ACCESS.
•THE SECOND WAY IS TO STORE THE DATA OR
INSTRUCTION IN THE CACHE MEMORY SO THAT IF IT IS
NEEDED SOON AGAIN IN NEAR FUTURE IT COULD BE
FETCHED IN A MUCH FASTER WAY.

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34. • THE PERFORMANCE OF THE CACHE IS MEASURED IN TERMS OF HIT
RATIO. WHEN CPU REFERS TO MEMORY AND FIND THE DATA OR
INSTRUCTION WITHIN THE CACHE MEMORY, IT IS KNOWN AS CACHE
HIT.
• IF THE DESIRED DATA OR INSTRUCTION IS NOT FOUND IN CACHE
MEMORY AND CPU REFERS TO THE MAIN MEMORY TO FIND THAT
DATA OR INSTRUCTION, IT IS KNOWN AS CACHE MISS.
• HIT + MISS = TOTAL CPU REFERENCE
• HIT RATIO(H) = HIT / (HIT+MISS)
• AVERAGE ACCESS TIME OF ANY MEMORY SYSTEM CONSISTS OF TWO
LEVELS: CACHE AND MAIN MEMORY. IF TC IS TIME TO ACCESS
CACHE MEMORY AND TM IS THE TIME TO ACCESS MAIN MEMORY
THEN WE CAN WRITE:
• TAVG = AVERAGE TIME TO ACCESS MEMORY
• TAVG = H*TC + (1-H)*(TM+TC)

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