Jason e stephens_resume


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Jason e stephens_resume

  1. 1. JASON E. STEPHENS JES_UO@ME.COM (845) 554 8430 31 Ontario St. #403 Cohoes, NY 12047 www.linkedin.com/in/jestephens EDUCATION University of Oregon - M.S. Applied Physics (2005) Southern Oregon University - B.S. Physics w/ Math Minor (2004) EXPERIENCE GLOBALFOUNDRIES | Malta/Albany/East Fishkill, NY Member of Technical Staff - Advanced Technology R&D 03/13-Present Lead, manage, and sustain 10NM BEoL, including some MoL, design rule development and technology definitions for both GlobalFoundries and ISDA/JDA.  Support all technology definition work for technology nodes below 10NM.  Work with digital design teams to enable competitive technology definitions, ground rules, and designs.  Hold weekly development meetings to review and monitor progress of all BEOL topics with representatives from every branch of development.  Patented unique and innovative design methodology for BEoL VNCAP devices using a new Mx process.  Submitted multiple patents on MoL and BEoL design methodology solutions to enable competitive std. cells, optimal pin accessibility and cell boundary conditions for best in class P&R results.  Lead the design rule development and research of the foundry industries first use of metal interconnect SADP (selfaligned pitch by spacer and double patterned with block/keep mask). Submitted patent applications and disclosures for innovative design rule and process solutions. Successfully developed router friendly Mx SADP design rule solutions for compatibility with foundries.  Playing a lead role in the development of solutions for triple color level colorless rules and decomposition.  Currently working with Coventor to develop and implement a virtual process flow for an SADP metal interconnect module. This will be used with the Coventor engine for early evaluation and studies of known limitations and risks.  Taught quarterly classes on design rule related topics like Monte Carlo methods and applications.  Taught quarterly classes on design rule and design manual training for dozens of departments.  The following roles and responsibilities, from 10/2010-03/2013, have not changed and also apply here.  Senior Engineer - Advanced Technology R&D 10/10 – 03/13 Lead the 10NM and 20NM BEoL design rule development for advanced technologies within GlobalFoundries and within ISDA/JDA for 10NM (as co-contributor for 20NM in ISDA). Consistently delivered innovative and competitive technology design rules on aggressive timelines.  Key activities include: Develop and maintain all BEoL design rules. Support all development of MoL design rules. Continuous collaboration with Integration, Patterning/OPC, Device, Reliability, design, DRC, Enablement, and Manufacturing to meet technology roadmap deadlines and deliver new innovative solutions to BEOL development challenges. Responsible for understanding full process flow, process assumptions and calculations, critical parameters and process risks, all possible failure mechanisms, and physical and electrical design rule impact on design. Evaluation of limiting parameters and design restrictions using statistical methodologies and approaches. Tools include Monte-Carlo method simulations, generating layouts for Litho simulations and pvBand analysis, 1D statistical calculations, 3D process modeling software, validation data, etc. along with process assumptions and the use of physical and mathematical models and principles. 
  2. 2. Work with DFM (Design for Manufacturing) team to define high to medium risk design rules and low risk design options for improved manufacturability. Work with patterning/OPC and integration teams to develop full RET solutions for each module. Evaluate rule implications and implement any necessary changes. Work with validation and test site teams on ground rule validation macros. Utilize the validation results to strengthen rules and process. Accommodate customer requests relating to the BEoL development and implementation. Continuously enhance the quality of the BEoL design rules and Design Manual through interaction with DRC, customers, design, or others. Example: Worked on creating and improving BEoL ground rule illustrations and illustration standards, resulting in 98% coverage and consistent standards. Create customer presentations for BEoL and some MoL Technology offerings and advantages. Present work to upper management on a regular basis. Continuous collaboration, indirect and direct, with EDA vendors on P&R and ground rule related BEoL development topics.  Drove task force groups working on the improvement of the PAD Class rules, Crackstop and Guardring re-design, and managed the development of an advanced custom Fill and density offering.  Contributed to the development of double patterned LELE design rules and colorless rules integration.  Played a key role in enabling a 576nm and 640nm competitive 9T Std. Cell Library through the invention and implementation of non standard limiting parameter simulation (NSLP) methodologies which has been filed for a US patent.  Made significant contributions to 20nm and 10nm BEoL design rule development through innovating and working hard to be inventor/co-inventor on 16 patent applications and invention disclosures, most of which are almost through the US patent application process.  Successfully mentored (and continue to mentor) an engineer to take ownership of the 20NM platform for design rules development, validation, and customer support. Ownership was transferred beginning of 2013.  Taught quarterly classes on design rule related topics like Monte Carlo methods and applications.  Taught quarterly classes on design rule and design manual training for dozens of departments. ON SEMICONDUCTOR | Gresham, OR Device Integration Engineer - Technology Integration & Development 08/07–2009 Played a lead role in the development and integration of a Dual Vertical Gate TrenchFET device technology. Regular Interfacing with business unit, unit process, and design organizations to accomplish deadlines and successfully ramp the technology into mfg.  Main Development & Integration Project Roles/Responsibilities/Contributions: Platform development and integration of optimal device parameters and process manufacturing. Ownership and generation of electrical design rules. Application of quantitative research methods, mathematical principles, statistical theories & methods, and principals of device physics to solve problems and optimize process and design solutions. Development of DOEs and investigation approaches for design solutions, design-process optimization, device centering, and EDR targeting. Si-to-model verification. E-test and Final-Test analysis, documentation, and validation. Electrical test-structure development. Root cause failure analysis using SPC data, In-Line Inspections, FA, XRD, E-test, DOEs, and bench testing. LVS support to ensure seamless integration into manufacturing  Created innovative new test conditions and structure modifications which enabled a number of critical parameters, both electrical and physical, to be isolated during parametric-testing as well as tested in tandem with multiple configurations. Comparing the automated combinations of parametric test results offered a much-needed solution to many ongoing issues.  
  3. 3.  Worked on all major & minor design/process/integration issue investigations. Offered creative investigation approaches and solutions to IDSS and IGSS parameter issues/roadblocks, which resulted in implementation of solutions for process & design targeting and optimization. Process/Device Yield Engineer - In-Line Yield Group 12/05 – 08/07 Planned, Developed, and Taught Trench-FET Device Physics Seminars. Taught classes on the devise physics, physical layout, and electrical operation of Trench-FET device technologies to ~63 engineers.  TrenchFET Technology Final Outgoing Inspection Development and Implementation. Developed a FAB outgoing inspection prior to Assembly & Final-Test to ensure defect events were detected, understood, documented, contained, and resolved. Developed standard conventions and methods for collecting, storing, and documenting accurate and dependable defect data. Wrote a detailed operational/procedural spec to ensure consistent and comprehensive inspection practices. Set up training routines and certification processes for specialists. Taught class on procedures, importance, and defects of interest. Determined Ave. cycle time impact & cost analysis per inspection. Overall, cycle time was reduced by 3 days with the above actions.  Sustaining Responsibilities and Improvement Activities: 0.13μm, 0.18μm CMOS, and TFET technologies - Owned FEOL and Far-BEOL inspections/trends and performed corrective actions against potential yield problems. Sustaining involved monitoring inspection data, SPC data, tool specific yield charts, and working with process owners and integration to resolve excursions and defect cases. Was instrumental in the documentation, research, and containment actions for over 11 high impact defect cases. Example: Engaged in driving a solution to residual poly defect excursion that damaged source contact barrier and resulted in IDSS fallout at EOL. Determined impact of affected wafers on assembly interruption rates at wafer saw, die bond, and wire pull, as well as IDSS variations and UIS yield at Final Test. Traveled to Malaysia Far-BEOL site to implement solution that resulted in the salvage of ~203 wafers with an ave. yield of 90%.  Owner of Automatic Defect Classification (ADC) System. ADC logically samples defects from inspected wafers using a trainable algorithm that differentiates between defect types and assigns them to predefined defect categories. Wrote in-depth procedural specs on creation, optimization, and maintenance of ADC production classifiers. Employed standards for ADC upkeep, DSA settings, naming conventions, and image sampling standards. Developed BKMs for advanced ADC accuracy and purity enhancement.  LSI LOGIC | Gresham, OR Internship - Process Integration 10/04 –12/05 Lead and monitored a 0.13μm BEOL yield vehicle targeting reliability and yield issues/improvements on 0.13μm products. Introduced and integrated the yield vehicle into the production environment to use the electrical bit mapping to inline optical production step inspection overlay capabilities for determining detectable and nondetectable defects, both systematic and random. Analyzed data results for process characterization and yield improvement/maintenance. This includes using data results to calculate precise kill ratios, trend dark yield to predict missed defects in-line, investigating the source of defectivity, and employing changes to correct yield fallout.  Electrical characterization/measurements/analysis of GIDL, Sub-threshold voltages, substrate sensitivity, mobility, IDSS variations, etc for 0.13 μm and 0.18 μm CMOS technologies.  AWARDS & HONORS Professional Awards:  Inventor/Co-Inventor on 8 Patent Applications and 8 Invention Disclosures. (2012/2013)  Excellence Award – GlobalFoundries Core Values and Behaviors – BEOL Achievements. (3/2012)
  4. 4. GlobalFoundries Global Recognition Award for commitment and hard work on technology deliverables. (4/2013) Engineering Excellence Award: Quickly Developing and Implementing a Final Outgoing Insp. Method, Procedure, Documentation, and Corrective Action Policy. (02/2007)  Engineering Excellence Award: Developing & Supporting EBRs, saving ~203 wafers from scrap. (06/2007)  Published-Co-Author of "Phase transitions in K2Cr2O7 and structural redeterminations of phase II" in Acta Crystallographica Section B: Structural Science. (2004) Academic Awards/Honors:  Ferroelectric material research at Southern Oregon University, funded by the NSF. (2003-2004)  Presented ferroelectric research results at the Oregon Academy of Science Conference. (2004)  Outstanding Achievement Award: Outstanding Research Contribution in the Field of Ferroelectric Compounds.  Outstanding Sophomore in Physics Award.  Ida and Eugene Bowman Encouragement Award and Scholarship in Mathematics.  Presidential Merit Match Scholarship & Plunkett Memorial Scholarship.  Elected into Who's Who Among Students in American Universities And Colleges.  Elected into Sigma Xi Research Honor Society.  Elected to The National Dean's List.   SKILLS  Design rule writing and development; understand DRC code; understand standard cell development and layouts; Proficient in generating test case layouts for litho simulations; understand OPC; Can perform pvBand analysis, orc analysis and understand the principles behind them. Very knowledgeable in the following, Process assumption calculations, BEOL process flows and details, Double Patterned Metal & Vias rule development, SADP/SID rule development, Design for Manufacturing, LELE Metal process and design rule development.  Computer Apps Skills: CalibreDRV, Unix, JMP, C-Sharp, Excel, Visual basic, Perl, DataPower, MatLab, Statistica, MS products, Klayout, Coventor, iDRM, DRC coding.  Device Development Characterization, Tech. Development, Device Layout & Process Optimization, assimilation of data results and statistical modeling for process/device modeling & yield modeling.  Experienced use & application of quantitative research methods, mathematical and statistical principles, statistical theories & methods, and principals of device physics to technology development.  Device physics and processing knowledge of Semiconductor devices, such as Trench-FETs, MOSFETs, CMOS/ASICs, Bipolar Devices, Passive Devices, etc.  Experienced at writing technical papers, reports, and patent disclosures. Much experience in communicating research/data through technical reports, presentations, and other methods.  Can Operate: SEMs, FIBs, KLA/AIT scanners, KLA-Automatic Defect Classifiers, ADC-Tool operation/optimization, ESM scanning tools, Optical Scopes, electrical bench test equipment & Probe Stations, Sorters, Parametric Analyzers-Agilent4156/Keithley4200/similar.