− 8051 Hardware Overview

Page 1 of 5

8051 Hardware Overview
•

•
•

3 basic versions of the MCS-51:
ROM
8051
4K bytes
80...
− 8051 Hardware Overview

Page 2 of 5

WR' – Write strobe to write external data memory.
RD' – Read strobe to read externa...
− 8051 Hardware Overview

Page 3 of 5

The first 256 bytes of internal data memory

ACC
B
PSW

Special function registers ...
− 8051 Hardware Overview

Page 4 of 5

PCON – Power control. Use in the 80C51 only.
IE
– Interrupt enable. 1=enable; 0=dis...
− 8051 Hardware Overview

Page 5 of 5

External RAM and I/O
Gnd
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

XTAL 1
XTAL 2

RS...
Upcoming SlideShare
Loading in …5
×

8051

484 views

Published on

Published in: Education, Technology, Business
0 Comments
1 Like
Statistics
Notes
  • Be the first to comment

No Downloads
Views
Total views
484
On SlideShare
0
From Embeds
0
Number of Embeds
2
Actions
Shares
0
Downloads
3
Comments
0
Likes
1
Embeds 0
No embeds

No notes for slide

8051

  1. 1. − 8051 Hardware Overview Page 1 of 5 8051 Hardware Overview • • • 3 basic versions of the MCS-51: ROM 8051 4K bytes 8031 none 8751 same as 8051 but with EPROM 8052 8K bytes 8032 8752 RAM 128 bytes I/O lines 32 256 bytes Counter/Timers 2 – 16 bit 3 – 16 bit Interrupt 5 (2 ext) “ “ 6 (2 ext) “ “ a duplex serial port bit-level Boolean processor 8051 Block diagram 256 Bytes RAM (8052) 128 Bytes RAM 8K ROM (8052) External Interrupts INT0' INT1' Internal Interrupts Interrupt Control 4K ROM Timer 2 (8052) T2 Timer 1 T1 Timer 0 T0 CPU RST Bus Control OSC XTAL1 Serial Port 4 I/O Ports XTAL2 WR' RD' EA' ALE PSEN' P0 P1 Address/ Data P2 P3 TXD RXD (8052) T2 P1.0 1 only T2EX P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P1.7 8 RST 9 RXD P3.0 10 TXD P3.1 11 INT0' P3.2 12 INT1' P3.3 13 T0 P3.4 14 T1 P3.5 15 WR' P3.6 16 RD' P3.7 17 XTAL2 18 XTAL1 19 Vss 20 8051 8051 Pinout 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0 AD0 P0.1 AD1 P0.2 AD2 P0.3 AD3 P0.4 AD4 P0.5 AD5 P0.6 AD6 P0.7 AD7 EA' Vpp ALE PROG' PSEN' P2.7 A15 P2.6 A14 P2.5 A13 P2.4 A12 P2.3 A11 P2.2 A10 P2.1 A9 P2.0 A8 Counter Inputs
  2. 2. − 8051 Hardware Overview Page 2 of 5 WR' – Write strobe to write external data memory. RD' – Read strobe to read external data memory. EA' – External address strobe for the 4K bytes of program memory. EA' = 0 for external 4K ROM. EA' = 1 for internal ROM. ALE – Address latch enable for latching the address signals on P0. ALE = 1 for latching address signals on P0. ALE = 0 for latching data signals on P0. PSEN' – Program store enable for reading external program memory. Memory map FFFF FFFF External 60K 1000 FF 0FFF Internal EA' = 1 4K 0000 External EA' = 0 4K Number of address lines 1 2 3 4 5 6 7 8 80 7F Number of bytes addressed in decimal (hex) 2 4 8 16 (10) 32 (20) 64 (40) 128 (80) 256 (100) 00 128 bytes Number of address lines Interrupt vector addresses in program memory Timer 2 interrupt → Serial port interrupt → Timer 1 interrupt → External interrupt 1 → Timer 0 interrupt → External interrupt 0 → Reset → 002B 0023 001B 0013 000B 0003 0000 64K Internal Data RAM Internal Data Memory Program Memory External RAM Special Function Registers 128 bytes 9 10 11 12 13 14 15 16 0000 External Data Memory Number of bytes addressed in decimal (hex) 512 (200) 1024=1K (400) 2048=2K (800) 4096=4K (1000) 8192=8K (2000) 16384=16K (4000) 32768=32K (8000) 65536=64K (10000)
  3. 3. − 8051 Hardware Overview Page 3 of 5 The first 256 bytes of internal data memory ACC B PSW Special function registers (SFR) (128 bytes) B ACC PSW T2CON IP P3 IE P2 SCON P1 TCON P0 RCAP2L RCAP2H TL2 TH2 TL0 DPL TL1 DPH TH0 TH1 SBUF TMOD SP PCON Scratch pad area (80 bytes) F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 78 70 68 60 58 50 48 40 38 30 28 20 18 10 8 0 Can be addressed as 16 bytes or 128 individual bits. Byte addresses are 20H to 2F. Bit addresses are 00H to 7F. Reg 0 Reg 1 Reg 2 Reg 3 Reg 4 Reg 5 Reg 6 Reg 7 Reg 0 Reg 1 Reg 2 Reg 3 Reg 4 Reg 5 Reg 6 Reg 7 Reg 0 Reg 1 Reg 2 Reg 3 Reg 4 Reg 5 Reg 6 Reg 7 Reg 0 Reg 1 Reg 2 Reg 3 Reg 4 Reg 5 Reg 6 Reg 7 Bank 3 Bank 2 Bank 1 Bank 0 – Accumulator – B register for multiply and divide. – program status word PSW.7 – Carry flag (CY) PSW.6 – Auxiliary carry flag (AC) PSW.5 – User define PSW.4 & 3 – Register bank select (RS1, RS0): 00=Bank 0; 01=Bank 1; 10=Bank 2; 11=Bank 3 PSW.2 – Overflow flag (OV) PSW.1 – User define PSW.0 – Parity flag (P) SP – Stack pointer. Initialized to 07H. SP is incremented before data is pushed on the stack. DPTR – Data pointer (DPH, DPL). To store a 16-bit address for certain instructions. P0, P1, P2, P3 – Port latches matching the 4 I/O ports. SBUF – Serial data buffer. Read and write registers for the serial port. SCON – Serial port control. TMOD – Timer mode. TCON – Timer control. T2CON – 8052 timer 2 control.
  4. 4. − 8051 Hardware Overview Page 4 of 5 PCON – Power control. Use in the 80C51 only. IE – Interrupt enable. 1=enable; 0=disable. IE.7 – all interrupts (EA). IE.6 – not used. IE.5 – timer 2 (ET2). (8052 only). IE.4 – serial port (ES). IE.3 – timer 1 (ET1). IE.2 – external interrupt 1(EX1). IE.1 – timer 0 (ET0). IE.0 – external interrupt 0 (EX0). IP – Interrupt priority. 1=high priority; 0=low priority. IP.7 – not used. IP.6 – not used. IP.5 – timer 2 (PT2). (8052 only). IP.4 – serial port (PS). IP.3 – timer 1 (PT1). IP.2 – external interrupt 1 (PX1). IP.1 – timer 0 (PT0). IP.0 – external interrupt 0 (PX0). RCAP2L – 8052 only. source IE0. source TF0. source IE1. source TF1. source R1 & T1. source TF2 & EXF2. interrupt address at 002B. interrupt address at 0023. interrupt address at 001B. interrupt address at 0013. interrupt address at 000B. interrupt address at 0003. External program memory using a 2732 4K EPROM XTAL 2 8051 RST ALE P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 PSEN' I/O DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 STB Gnd DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Vcc Gnd A8 A9 A10 A11 A7 A6 A5 A4 A3 A2 A1 A0 2732 EPROM 4K P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL 1 EA' Vcc Gnd 8282 Vcc OE' * D7 D6 D5 D4 D3 D2 D1 D0 OE' * These pins are not available as I/O when any part of Port 2 is being used as an address bus. CE'
  5. 5. − 8051 Hardware Overview Page 5 of 5 External RAM and I/O Gnd P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL 1 XTAL 2 RST EA' P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 8051 +5v P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 WR' P3.7 RD' IO ALE IO IO Vcc P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 PSEN' IO/M' RD' WR' Gnd 8155 256 bytes RAM Vcc PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PA.6 PA.7 PC.0 PC.1 PC.2 PC.3 PC.4 PC.5 IO ALE PB.0 PB.1 PB.2 PB.3 PB.4 PB.5 PB.6 Timer Timer PB.7 out' in CE' Address Lines 1 2 3 4 5 6 7 8 A15 Decimal Hex 2 4 8 16 32 64 128 256 2 4 8 10 20 40 80 100 A13 A12 A14 Address Lines 9 10 11 12 13 14 15 16 A11 A10 Decimal Hex 512 (1K) 1024 ( 2K) 2048 (4K) 4096 (8K) 8192 (16K) 16384 (32K) 32768 (64K) 65536 200 400 800 1000 2000 4000 8000 10000 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

×