TIMERS / COUNTERS
- Two 16 bit timer/counters
- Can be programmed independently as – timer or event
- Four-SFR’s connected with TIMER/COUNTER operation
- TMOD – Timer Mode Register
- TCON – Timer Control Register
- TH0, TL0 – Timer/Counter - 0
- TH1, TL1 – Timer/Counter - 1
- Two pins of 8051 connected with Timer/counter.
T0 – Timer 0 external input – P3.4
T1 – Timer 1 external input – P3.5
- INT0 and INT1 are also used for controlling the
Timer Register (TH0, TL0 or TH1, TL1) incremented every m/c cycle. Thus
working at increment frequency of 1/12 of oscillator frequency ( for 12
oscillator machine cycle ). Any preset value i.e. initial count can be loaded to
TH0, TL0 or TH1, TL1.
For Example – Clock frequency = 12 MHZ
Clock period = 1/12 µ sec
Machine cycle time = 1 µ sec
Thus timer register will be incremented every microsecond.
- If timer is initialized to 0000H
Max. count = FFFFH
max. time measured = 216 µ sec
= 26 x 210 µ sec
≈ 26 millisecond
≈ 64 millisecond
= 65.5 millisecond
- Counts pulses occurring at T0 pin (Timer/Counter 0) and/or
T1 pin (Timer/counter 1).
- May correspond to event like
• Passing of railway coach from a point – axle counter
• Rotation of speedometer cable
– speedometer of vehicle
• No. of persons visiting exhibition.
- T0, T1 scanned every m/c cycle
• nth m/c cycle – T1 or T0 = High
• (n+1)th m/c – T1 or T0 = Low
• Timer 0 or timer 1 incremented in (n+1)th m/c cycle
- Count frequency = min 2 m/c cycle per count
- T0- P3.4, T1- P3.5
In 12 MHz 8051 – m/c cycle = 1 µ sec
- 8051 can count at the rate of 2 µ sec per count or higher
- Any event when takes less than 2 µ sec may go unnoticed
- C/T bit of TMOD selects Timer or counter operation for
Timer 0 or Timer 1.
- Timer/Counter operations are controlled by
- Gate bit of TMOD
- TR0 bit of TCON
When Gate = 0 then
TR0, TR1 act as
Timer run control bits.
- Thus make Gate = 0 in TMOD
By making TR0 (TCON. 4) or TR1 (TCON. 6) = 1 .
through instruction, Timer/Counter 0 or
Timer/Counter 1 may be started.
- For starting and stopping the Timer/Counter
from outside through hardware.
Make Gate = 1, TR0 = 1 through software.
- By making INT0 or INT1 pin High will start
Timer/Counter 0 or Timer/Counter 1
Make INT0 or INT1 Low to stop the Timer/Counter.
INT0 - P3.2
INT1 - P3.3
As value in Timer register rolls from all ones
(i.e. FFFFH) to all zero’s (i.e. 0000H) interrupt
flag (TF0 or TF1) will be set.
- TF0 (for Timer 0) and TF1 (for Timer 1) are
bits of TCON SFR.
IF Timer 0 or Timer 1 interrupt is enabled then
program control will branch to interrupt servicing
13 bit counter
16 bit counter
8 bit counter + auto reload
Split operation – Timer 0
- Modes are set by M1 M0 bits of TMOD register.
Mode 0 - 13 bit counter operation
- TH0, TL0 (for Timer 0) or TH1, TL1 (for Timer 1)
used as 13 bit counter.
- All 8 bits of TH0 or TH1
- 5 lower bits of TL0 or TL1
are used, for counting.
- When count rolls over from all 1’s to all 0’s, interrupt flag TF0 or TF1 is set.
In above figure when C/T = 0 - timer operation
count incremented every m/c cycle.
TR0 (TCON. 4) or TR1 (TCON. 6) = 1
and Gate (TMOD. 3) or (TMOD. 7) = 0
Other way is- TR0 or TR1 =1
- Gate = 1 and INT0 or INT1 = 1
- Thus by sending Logic High signal on INT0 (or INT1) pins
Timer 0 or Timer 1 can be started.
- This can be used for finding pulse width in the
C/T = 0 – Timer operation
TR0 or TR1 = 1
Gate = 1
Source of pulse connected to INT0 or INT1 pin
- When pulse goes high timer starts counting at the
rate 1/12 clock frequency
- Which pulse goes low – Timer stops.
INT0 or INT1 = Low - causes interrupt.
- ISR can read the timer value.
- ISR can store the timer value and process it as
required by the application.
- Only TL0 or TL1 are used i.e. 8 bit counting.
- Initial preset value is loaded to TH0 or TH1 by
- The value is loaded to TL0 or TL1 by hardware
automatically before starts of counting.
- When count rolls from all 1’s (i.e. FFH) to all 0’s
- TF0 or TF1 flag is set
- Preset value in TH0 or TH1 is reloaded to TL0 or TL1
- Operation i.e. Counting starts automatically.
- When Timer 0 is put in mode 3
- Acts as two 8 bit counters i.e. TL0 and TH0
become two separate counter.
TL0 – 8 bit operation in mode 0 or mode 1
(Timer or Counter) controlled by C/T, TR0,
– Sets TF0 when count rolls to all 0’s from all 1’s.
TH0 – Timer function only.
– Controlled by TR1 i.e. starts when TR1 = 1.
When count rolls to all 0’s from all 1’s – TF1 flag is
Note – TR1 and TF1 are used in
Timer 0 (TH0) even though they are
bits for Timer 1.
When Timer 1 is put in mode 3 –
It just holds the preset count
– same as TR0 = 0 i.e. opening the switch.
[Modes 0, 1 and 2 are mostly used]
Timer Mode Control Register - TMOD
M1 and M0 specify the mode as follows:
Description in brief
8-bit counter with autoreload
Split Timer 0 into two 8-bit counters or to stop Timer 1
If C/T = 1, the timers function as counters to
count the negative transitions at T0 or T1 pins.
If C/T = 0, the timers function as timers, that is,
they basically count the number of machine
Gate = 0 means that the timer is controlled by
TR1 or TR0 only, irrespective of INT0 or INT1.
Gate = 1 means that the timer control will
depend on INT0 or INT1 and also on TR0 or TR1
When data is written it gets latched.
TMOD is used for setting mode bits M1, M0,
Gate bit and C/T for Timer 0 and Timer 1.
Bit 0 to 3 for Timer 0.
Bit 4 to 7 for Timer 1.
Timer Control Register - TCON
Bit 0 to 3 – used for interrupt functions
Bit 4 to 7 – used for setting TR0, TR1 by software
- Setting TF0, TF1 by counter i.e. hardware
When count rolls from all 1’s to all 0’s.
Timer 1 overflow flag. Set by hardware when the timer/counter overflows.
Cleared by hardware when the processor vectors to the interrupt routine.
TR1: Timer 1 run control bit. Set/cleared by software to turn the timer/counter
Timer 0 overflow flag. Set by hardware when the timer/counter overflows.
Cleared by hardware when the processor vectors to the interrupt routine.
TR0: Timer 0 run control bit. Set/cleared by software to turn the timer/counter
a. Configuring Timer/Counter using TMOD
b. To load initial count as preset value
- Work out the preset value = ABCDH – Timer 0
- Load the preset value
= 0000H - Timer 1
d. When count value in Timer Register
transits from all 1’s to all 0’s
- Following tasks need to be done.
Preset value to be loaded to Timer Register
Timer interrupt flag (TF0 or TF1) to be cleared
For continuous operation of Timer/Counter
Pulse train generation etc.
- Can be achieved in 2 ways:
1. - Check Timer interrupt flag in loop.
JNB TCON.5, $ or JNB TCON.7, $
- When interrupt flag is set then clear the flag.
CLR TCON.5 or CLR TCON.7
- Load the preset count and restart
SJMP to b
2. Write ISR for Timer 0 or Timer 1 and store at
location 000BH (for Timer 0) or 001BH (for Timer
- Enable Timer 0 or Timer 1 interrupt
by making bits ET0 (IE.1) or ET1(IE.3) = 1.
SETB IE.1 or SETB IE.3
- When TF0 or TF1 is set
- Interrupt will occur and program will branch to
ISR location (000BH for Timer 0) or (001BH for
- clear flag TF0 or TF1
- load preset value
- Restart timer/counter
Step d will be different for different applications.
- Generate a square wave of 50% duty cycle at pin p1.7.
Use Timer 1 to generate time delay.
Clock frequency = 12 MHz, 12 oscillator clock. Pulse
width = 50 millisecond.
- Let us work out the initial preset value.
1 m/c cycle = 1 microsecond
50 millisecond = 50 x 103 microsecond
= 50, 000 m/c cycle
FFFF = 65535
Difference = 65535 - 50000 = 15535 m/c cycle
- Since count will roll from FFFF to 0000 additional m/c cycle
will be required to set TF0 or TF1 .
Thus initial count must be 15536
i.e. = 3CB0H
By putting initial preset count of
3CB0H (or 15536 decimal), the register will
reach FFFF in 49999 m/c cycle and roll over to
0000 in 50,000th m/c cycle accounting for 50
a. Configure Timer 1
Gate = 0, C/T = 0, Mode = 01
(16 bit operator)
MOV TMOD , # 1 0 H
Make P1.7 = Low initially
Load Preset Value
c. Complement P1.7
d. Start Timer 1 (TR1 = 1)
e. Check for TF1=1 in loop
JNB TCON.7, $
f. TF1=1, Make TF1=0
g. Stop Timer 1 Make TR1=0
h. SJMP KK
To reload preset value
Start Timer 1.
Steps d to g can be written as subroutine.
Example – 8051 with clock frequency = 18 MHz
a. Generate a square wave of frequency 2 KHz
on pin P1.0 using mode 2.
b. Calculate the smallest frequency possible
without using software counter.
Clock frequency = 18 MHz
Clock period = 1/18 µ sec.
1 m/c cycle = 12/18 µ sec = 2/3 µ sec.
2 KHz square wave
clock period = ½ 10-3 sec. = 0.5 millisecond
<- - - - - - 0.5 ms - - - - ->
Up time = 0.25 ms
Dn time = 0.25 ms
Up time = 0.25 ms = 0.25 x 103 µ sec
No. of m/c cycles in up time = (¼ x 103)/(2/3)
= ¼ x 103 x 3/2 = 3/8 x 103
= 3000/8 = (30 x 25)/2
= 15 x 25 = 375
- Delay of 375 m/c cycle can be achieved in many
375/3 = 125 – Generate delay of 125 m/c cycle 3 times
375/5 = 75 – Generate delay of 75 m/c cycle 5 times
375/15 = 25 – Generate delay of 25 m/c cycle 15 times
We can take any of the options. Let us take 1st one.
To generate delay of 125 m/c cycle
(FFH) 255 – 125 = 130
Accounting for additional m/c cycle
Preset = 131 = 83H
; Configure TMOD.
Let us use Timer 0
TF0 in loop
timer by making TR0=0
Decrement and Branch to start timer.
Delay of 375 m/c cycle completed.
b. – Frequency is smallest when
clock period = maximum
i.e. Up time and Down time = maximum
i.e. Delay is maximum.
Delay is maximum when preset value =0
i.e. No. of m/c cycles in Up time = FF+1
No. of m/c cycles in Dn time = FF+1
Up time = 256 x 2/3 µ sec = 512/3 ≈ 170 µ sec
Clock period = 341 µ sec.
Frequency = 1/341 MHz = 1000/341 KHz
= 2.92 KHz
Example – Counter Operation
- Design a counter to count pulses input at P3.4.
- Determine the no. of pulses received in 1 minute.
- 8051 is 12 MHz, 12 Clock m/c cycle.
-> P3.4 pin is T0 i.e. -> external input to Timer 0
C/T = 1 – Counter operation
Gate = 0, M1 M0 = 01 - 16 bit operation
Timer value to 0000H
; Start Counterby making TR0 = 1
; Read timer value and output on P2, P1
Let us calculate the maximum no. of pulses
that can be counted.
- In 16 bit operation i.e. Mode 01 –
(FFFF+1) = 65535 + 1 = 65536
- In 13 bit operation i.e. Mode 00 –
1FFF+1 = 8191 = 8192
- In 8 bit operation i.e. Mode 02 & Mode 03 –
FF+1 = 255+1 = 256
Let us assume that 1 pulse corresponds to
– one rotation of is wheel
– circumference of wheel = 1 meter
Max. distance travelled in 1 minute can be
8 bit operation – 256 meter.
13 bit operation – 8192 meter
16 bit operation – 65536 meter.
Considering that overflow takes place in 1 minute
Max. distance travelled in 1 hour that can be
measured with be
8 bit operation – 256 x 60 = 14760 meter
= 14.76 KMPH
13 bit operation – 8192 x 60
= 491520 = 491.52 KMPH
16 bit operation – 65536 x 60 = 3932160 meter.
= 3932.16 KMPH
For measuring automobile speed –
13 bit or 16 bit operation will be o.k.
- Delay operation can also be managed using hardware timer
so that micro controller is free for carrying out other tasks.
Let us assume that Timer 1 is used for incorporating 1
12 MHz clock
1 m/c cycle = 1 µ sec
1 second = 106 µ sec = 106 m/c cycle
= 220 m/c cycle
= 24 x 216 m/c cycle.
Thus 0000 to FFFF+1, counter has to repeat 16 times for delay
of 1 sec.
For 1 Minute delay
1 minute = 60 x 16 x216
– 1 second delay must be repeated in loop by 60 times
Now, TMOD will become
= 15 H
C/T = 0 for Timer 1 – Timer operation
TMOD, #05H will get modified
to MOV TMOD, #15H
R3, #3CH ; for 60 seconds
R4, #10H ; for 16 times
repeat for 1 second
We could also use interrupt servicing routine
of timer interrupt for this purpose.