SSRLabs
Energy- and Instruction-Efficient HPC
August 2013
© 2013 Scalable Systems Research Labs, Inc.
Axel Kloth, Presiden...
August 2013
SSRLabs Overview
2
The “Big Data” Challenge
Achieve accuracy and speed goals
Solve the (power = heat) problem
August 2013 SSRLabs Overview 3
Efficiency is the Benchmark
August 2013
SSRLabs Overview
4
The “Big Data” Solution
Achieve accuracy and speed goals
Solve (power = heat) problem
De-co...
August 2013
SSRLabs Overview
5
SSRLabs
Addresses “Big Data” challenge using
coprocessors and APIs to optimize performance
...
August 2013
SSRLabs Overview
6
pScale™ Product Attributes
Instruction- and energy-efficient neural network
and floating-po...
August 2013
SSRLabs Overview
7
pScale Coprocessor
Schematic
Coprocessor Implementation
August 2013 SSRLabs Overview 8
pScale™
Floating-Point
or Neural Net
Coprocessor
Massively
Paral...
System Implementation
August 2013 SSRLabs Overview 9
August 2013
SSRLabs Overview
10
Development Status
Core IP and ASIC building blocks in-house for
pScale™ coprocessor desig...
August 2103
SSRLabs Overview
11
Summary
Hyperscale and micro server markets share common
performance vs. efficiency challe...
August 2013 SSRLabs Overview 12
Contact
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SSRLabs Podcast: Energy- and Instruction-Efficient HPC

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This presentation from SSRLabs describes the company's innovative Big Data hardware architecture optimized for bandwidth and power efficiency. The company is in the early stages of development, and at this point is seeking partners and investors.

Watch the presentation video:
http://insidehpc.com/2013/09/03/slidecast-ssrlabs-develops-energy-instruction-efficient-hpc/

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SSRLabs Podcast: Energy- and Instruction-Efficient HPC

  1. 1. SSRLabs Energy- and Instruction-Efficient HPC August 2013 © 2013 Scalable Systems Research Labs, Inc. Axel Kloth, President & CEO
  2. 2. August 2013 SSRLabs Overview 2 The “Big Data” Challenge Achieve accuracy and speed goals Solve the (power = heat) problem
  3. 3. August 2013 SSRLabs Overview 3 Efficiency is the Benchmark
  4. 4. August 2013 SSRLabs Overview 4 The “Big Data” Solution Achieve accuracy and speed goals Solve (power = heat) problem De-couple system management and transaction or numerically intensive operations CPU and Coprocessor/Accelerator Approach
  5. 5. August 2013 SSRLabs Overview 5 SSRLabs Addresses “Big Data” challenge using coprocessors and APIs to optimize performance and efficiency of both high-transaction count and numerically intensive applications Developing a novel MPP architecture that is easier to program and takes less energy to execute tasks than traditional processors
  6. 6. August 2013 SSRLabs Overview 6 pScale™ Product Attributes Instruction- and energy-efficient neural network and floating-point coprocessors Concurrent improvements in per-core performance, number of cores and efficient intra-core communications with reduced latency for better system performance Platform agnostic
  7. 7. August 2013 SSRLabs Overview 7 pScale Coprocessor Schematic
  8. 8. Coprocessor Implementation August 2013 SSRLabs Overview 8 pScale™ Floating-Point or Neural Net Coprocessor Massively Parallel Processor with 64-bit cores HMC DRAM
  9. 9. System Implementation August 2013 SSRLabs Overview 9
  10. 10. August 2013 SSRLabs Overview 10 Development Status Core IP and ASIC building blocks in-house for pScale™ coprocessor design Raising A Round financing for product design/ engineering Will market coprocessors/cards and license building blocks/IP for secondary revenue stream
  11. 11. August 2103 SSRLabs Overview 11 Summary Hyperscale and micro server markets share common performance vs. efficiency challenges $2B annual market opportunity for SSRLabs Design approach – confirmed by Technology Advisory Board – brings simplicity to MPP deployment Current disruption in server CPU choice validates market readiness to change
  12. 12. August 2013 SSRLabs Overview 12 Contact

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