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Evolving System Design for HPC: Next Generation AMD CPU and Accelerator Technologies

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In this deck from the Rice Oil & Gas Conference, Forrest Norrodd from AMD presents: Evolving System Design for HPC: Next Generation CPU and Accelerator Technologies.

"As the definition of High Performance Computing (HPC) expands to include Big Data Analytics, Machine Learning, and Artificial Intelligence (AI), a more scalable, powerful, and secure approach is required to meet these ever growing demands. This talk will discuss how next generation CPU and accelerator technologies, partnered with innovative system designs and software advances, can propel the industry to pre-exascale and exascale systems. Unlocking the full potential of these new technologies and architectures will require innovation throughout the ecosystem."

Watch the video: https://wp.me/p3RLHQ-lBM

Learn more: http://amd.com
and
https://rice2019oghpc.rice.edu/program/

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Evolving System Design for HPC: Next Generation AMD CPU and Accelerator Technologies

  1. 1. 2 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 This presentation contains forward-looking statements concerning Advanced Micro Devices, Inc. (AMD) including, but not limited to, the features, functionality, expected benefits and availability of AMD’s future products; and AMD’s technology roadmap, which are made pursuant to the Safe Harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are commonly identified by words such as "would," "may," "expects," "believes," "plans," "intends," "projects" and other terms with similar meaning. Investors are cautioned that the forward-looking statements in this presentation are based on current beliefs, assumptions and expectations, speak only as of the date of this presentation and involve risks and uncertainties that could cause actual results to differ materially from current expectations. Such statements are subject to certain known and unknown risks and uncertainties, many of which are difficult to predict and generally beyond AMD's control, that could cause actual results and other future events to differ materially from those expressed in, or implied or projected by, the forward-looking information and statements. Investors are urged to review in detail the risks and uncertainties in AMD's Securities and Exchange Commission filings including, but not limited to, AMD’s Annual Report on Form 10-K for the year ended December 29, 2018.​ CAUTIONARY STATEMENT
  2. 2. 3 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 20193 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  3. 3. 4 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 20194 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  4. 4. 5 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 20195 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  5. 5. 6 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 20196 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  6. 6. 7 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 20197 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 intel nVIDIA Use of third-party marks / logos is for informational purposes only and no endorsement of or by AMD is intended or implied. GD-83
  7. 7. 8 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 20198 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 See Endnotes for Source
  8. 8. 9 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 nanometers Source: ark.intel.com 180nm 130nm 90nm 65nm 45nm 32nm 22nm 14nm
  9. 9. 10 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201910 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  10. 10. 11 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 m14nm I/O DIE I/O DD R DD R DD R DD R ∞ DD R DD R DD R DD R 7nm CPU die 7nm CPU die ∞ ∞ ∞ I/O ∞ ∞ ∞ ∞ 7nm CPU die 7nm CPU die 7nm CPU die 7nm CPU die 7nm CPU die 7nm CPU die Monolithic die Multi-die MCM Chiplet
  11. 11. 12 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 ▪ ▪ ▪ ▪ ▪ System optimizing packaging
  12. 12. 13 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 WITHIN SOCKET Package FABRIC On-Package and Between Sockets Scalable Fabrics Enabling Architectural Innovation Rapid Development with Heterogenous IP CPU WITHIN SOCKET Package BETWEEN SOCKETS CPU CPU CPU CPU CPU CPU CPU
  13. 13. 14 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 Die Stacking and 2.5D Integration HBM2 DRAM Die HBM2 DRAM Die HBM2 DRAM Die HBM2 DRAM Die Memory Controller Interposer Package Substrate GPU
  14. 14. 15 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201915 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 Use of third-party marks / logos is for informational purposes only and no endorsement of or by AMD is intended or implied. GD-83
  15. 15. 16 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  16. 16. 17 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  17. 17. 18 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201917 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  18. 18. 19 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201919 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 WORLD RECORD SPECrate 2017_fp_peak See Endnote NAP-106
  19. 19. 20 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201920 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  20. 20. 21 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201921 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  21. 21. 22 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201922 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  22. 22. RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  23. 23. 24 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  24. 24. 25 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  25. 25. 26 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201926 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 Use of third-party marks / logos is for informational purposes only and no endorsement of or by AMD is intended or implied. GD-83
  26. 26. 27 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201927 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  27. 27. 28 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 201928 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  28. 28. 29 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 nVIDIA 29 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019
  29. 29. ROAD TO EXASCALE
  30. 30. 31 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 ENDNOTES Slide 7 – FREQUENCY SCALING: ORIGINAL DATA UP TO THE YEAR 2010 COLLECTED AND PLOTTED BY M. HOROWITZ, F LABONTE O.SHACHAM, K. OLUKOTUN, L. HAMMOND, AND C. BATTEN. NEW PLOT AND DATA COLLECTED FOR 2010-2015 BY K. RUPP. HTTPS://WWW.KARLRUPP.NET/2015/06/40-YEARS-OF-MICROPROCESSOR- TREND-DATA/ NAP-106: The EPYC 7601 processor has the highest SPECrate®2017_fp_peak scores for both 1P and 2P. 1P at https://www.spec.org/cpu2017/results/res2018q2/cpu2017- 20180426-05035.html. 2P at https://www.spec.org/cpu2017/results/res2018q2/cpu2017-20180319-04087.html. SPECrate®2017_fp_peak as of Oct 30, 2018. https://www.spec.org/cpu2017/results/. SPEC®, SPECrate® and SPEC CPU® are registered trademarks of the Standard Performance Evaluation Corporation. See www.spec.org for more information. RIV-12: Testing Conducted by AMD performance labs on October 31, 2018, on a system comprising of Dual Socket Intel Xeon Gold 6130, 256GB DDR4 system memory, Ubuntu 16.04.5 LTS, AMD Radeon Instinct MI25 graphics, AMD Radeon Instinct MI60 graphics, ROCm 19.211 driver. Benchmark application: rocBLAS DEGEMM N=M=K=5760. AMD Radeon Instinct MI25 GFLOPS = 763. AMD Radeon Instinct MI60 TFLOPS = 6.717. Performance differential: 6717/763 = 8.8x more performance than Radeon Instinct MI25. Server manufacturers may vary configurations, yielding different results. Performance may vary based on use of latest drivers and optimizations. Calculated on Oct 22, 2018, the Radeon Instinct MI60 GPU resulted in 7.4 TFLOPS peak theoretical double precision floating-point (FP64) performance. AMD TFLOPS calculations conducted with the following equation: FLOPS calculations are performed by taking the engine clock from the highest DPM state and multiplying it by xx CUs per GPU. Then, multiplying that number by xx stream processors, which exist in each CU. Then, that number is multiplied by 1/2 FLOPS per clock for FP64. TFLOP calculations for MI60 can be found at https://www.amd.com/en/products/professional-graphics/instinct-mi60. RIV-14: Testing Conducted by AMD performance labs on October 31, 2018, on a system comprising of Dual Socket Intel Xeon Gold 6130, 256GB DDR4 system memory, Ubuntu 16.04.5 LTS, NVIDIA Tesla V100 PCIe with CUDA 10.0.130 and CUDNN 7.3, AMD Radeon Instinct MI60 graphics with ROCm 19.224 driver. Benchmark application: cuBLAS/rocBLAS SGEMM N=M=K=5760. AMD NVIDIA Tesla V100 PCIe TFLOPS = 13.106. AMD Radeon Instinct MI60 TFLOPS = 14.047. Server manufacturers may vary configurations, yielding different results. Performance may vary based on use of latest drivers and optimizations. ROM-03: Testing performed by AMD Engineering as of October 2018 using AMD reference system with a preproduction “Rome” engineering sample, where “Rome” scored approximately 2x higher compared to “Naples” System. Actual results with production silicon may vary. ROM-04: Estimated generational increase based upon AMD internal design specifications for “Zen 2” compared to “Zen 1”. “Zen 2” has 2X the core density of “Zen 1”, and when multiplied by 2X peak FLOPs per core, at the same frequency, results in 4X the FLOPs in throughput. Actual results with production silicon may vary. ROM-04
  31. 31. 32 RICE OIL & GAS HPC CONFERENCE | MARCH 4, 2019 The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. The information contained herein is for informational purposes only, and is subject to change without notice. Timelines, roadmaps, and/or product release dates shown in these slides are plans only and subject to change. [“Naples”, “Rome” ] are codenames for AMD architectures, and are not product names. GD-122. ATTRIBUTION © 2019 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, EYPC, Radeon, Radeon Instinct and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Microsoft is a registered trademark of Microsoft Corporation in the US and other jurisdictions. Other names are for informational purposes only and may be trademarks of their respective owners. DISCLAIMER & ATTRIBUTION

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