Unit3 input


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Unit3 input

  1. 1. Computer organization
  2. 2. I / O
  3. 3. interrupts <ul><li>Interrupt is a signal ; on receiving this signal, the processor suspends the execution of the program that it currently executing and transfers control to an interrupt handling program </li></ul><ul><li>At least one of the bus control lines called the interrupt request line should be dedicated for carrying the signal </li></ul><ul><li>The routine executed in response to an interrupt is called interrupt service routine </li></ul>
  4. 4. interrupts <ul><li>On handling the request , the processor must inform the device that made the request. </li></ul><ul><li>This is done by sending a interrupt acknowledge signal </li></ul><ul><li>The time delay between the interrupt request and execution of interrupt service routine is called interrupt latency </li></ul>
  5. 5. interrupts <ul><li>Basic execution of an interrupt </li></ul><ul><ul><li>The device raises an interrupt </li></ul></ul><ul><ul><li>The processor interrupts the program it currently being executed </li></ul></ul><ul><ul><li>Interrupts are disabled by changing the control bits in the processor status register </li></ul></ul><ul><ul><li>The action requested by the interrupt is performed by the ISR Interrupts are enabled and execution of interrupted program is resumed </li></ul></ul>
  6. 6. interrupts <ul><li>Types of interrupts </li></ul><ul><ul><li>External interrupts </li></ul></ul><ul><ul><li>Internal interrupts </li></ul></ul><ul><ul><li>Software interrupts </li></ul></ul>
  7. 7. interrupts <ul><li>External interrupts come from I/O devices, from timing device, from circuit monitoring the power supply etc. </li></ul><ul><li>Internal interrupts arise from illegal use of an instruction or data. </li></ul><ul><li>Internal interrupts are also called as traps. </li></ul><ul><li>The service program that processes the internal interrupt determines the corrective measure to be taken </li></ul>
  8. 8. interrupts <ul><li>The internal interrupt is initiated by some exceptional condition caused by the program itself rather than by an external event. </li></ul><ul><li>Internal interrupts are synchronous with the program, while external interrupts are asynchronous. ie if the program is rerun, the internal interrupts will occur in the same place each time. External interrupts depend on external conditions that are independent of the program. </li></ul>
  9. 9. interrupts <ul><li>External and internal interrupts are initiated from signals that occur in the hardware </li></ul><ul><li>Software interrupt is initiated by executing an instruction. </li></ul><ul><li>This instruction can be used by the programmer to initiate and interrupt procedure at any desired point in the program </li></ul><ul><li>The most common s/w interrupt used is an supervisor call , which is used for switching from a user mode to supervisor mode </li></ul>
  10. 10. Modes of data transfer <ul><li>Information received from an external device is stored in the memory later for later processing </li></ul><ul><li>Information is transferred to and from the memory involves can happen in different modes </li></ul><ul><li>In certain transfers , the CPU acts as an intermediate path ,and in other ones the transfer take place between the memory and external devices directly </li></ul><ul><li>The different modes are </li></ul><ul><ul><li>Programmed I/O </li></ul></ul><ul><ul><li>Interrupt initiated I/O </li></ul></ul><ul><ul><li>Direct Memory access </li></ul></ul>
  11. 11. Modes of data transfer <ul><li>programmed I/O </li></ul><ul><li>The i/o devices have no direct access to memory </li></ul><ul><li>CPU registers act as an intermediate storage </li></ul><ul><li>The operations are the result of i/o instruction written in the computer program </li></ul><ul><li>Once a data transfer is required , the CPU is required to monitor the interface to see when a transfer can again be made </li></ul><ul><li>The programmed instructions has to take care of everything that is taking place in the interface unit and the I/O device </li></ul>
  12. 12. IO mapped i/o Data valid Address bus i/o bus CPU Status F register IO device interface Data register Data accepted Data bus I/o read I/o write
  13. 13. Modes of data transfer <ul><li>programmed I/O </li></ul><ul><li>The device transfers data one at a time </li></ul><ul><li>When data is available the device places it in i/o bus and enable data valid line </li></ul><ul><li>Interface accepts the byte into data register and enables data accepted line </li></ul><ul><li>Interface sets the flag and disable data valid line </li></ul><ul><li>CPU checks stats flag and if it is sets, CPU reads data and flag is cleared either by CPU or interface </li></ul><ul><li>Data accepted line is set invalid </li></ul>
  14. 14. Modes of data transfer <ul><li>I/O addressing </li></ul><ul><li>In systems using programmed i/o the CPU ,M and IO devices usually communicate through system bus </li></ul><ul><li>The address lines of the system bus that are used to select memory locations can be used to select I/O devices. </li></ul><ul><li>An i/o device is connected to the bus through an i/o port, which from the CPU’s perspective , is an addressable data register like a memory location </li></ul>
  15. 15. Modes of data transfer <ul><li>If a part of the main memory address space is assigned to IO ports, then the technique is called memory-mapped IO </li></ul><ul><li>An instruction that causes data to be fetched from or stored at address X becomes an IO instruction if X is made the address of an I/O port </li></ul>
  16. 16. Modes of data transfer <ul><li>If the memory and IO address spaces are separate , then the arrangement is called IO-mapped IO </li></ul><ul><li>A memory referencing instruction activates the read or write M control line which does not affect the I/O devices </li></ul><ul><li>The CPU must execute separate instructions for Read or write IO </li></ul><ul><li>When the processor repeatedly checks the status of the I/O in operation for to achieve required synchronization between the processor and i/o device, we say the processor polls the device </li></ul>
  17. 17. Memory mapped i/o data Address read write Main memory CPU IO port 1 IO port 2 IO port 3 IO device A IO device B
  18. 18. IO mapped i/o data Address Read M write Main memory CPU IO port 1 IO port 2 IO port 3 IO device A IO device B Write M Read IO Write IO
  19. 19. Modes of data transfer <ul><li>Interrupt driven I/O </li></ul><ul><li>In programmed IO method , the CPU stays in a program loop until the IO indicates that it is ready for data transfer </li></ul><ul><li>This is a time consuming process </li></ul><ul><li>it can be avoided by using an interrupt facility and special command to inform the interface to issue an interrupt request signal when the data is available from the device </li></ul>
  20. 20. Modes of data transfer <ul><li>In the meantime, processor can proceed to execute another program </li></ul><ul><li>The interface will keep monitoring the device and generate the signal when the device is ready </li></ul><ul><li>The CPU will suspend the current task and process the IO transfer </li></ul>
  21. 21. Modes of data transfer <ul><li>When the flag is set, the CPU is interrupted and is ready to handle I/O </li></ul><ul><li>After transfer is completed CPU will return to the previous process </li></ul><ul><li>The CPU responds to the interrupt signal by storing the return address to a memory stack and control branches to a service routine that process the I/O transfer </li></ul>
  22. 22. Modes of data transfer <ul><li>There are two methods called vectored and non vectored interrupts for collecting the branch address </li></ul><ul><li>In non vectored interrupt , the branch address is assigned to a fixed location in the memory </li></ul><ul><li>In vectored interrupt, the source that interrupt supplies the branch address </li></ul><ul><li>This information is called interrupt vector </li></ul>
  23. 23. Modes of data transfer <ul><li>Handling multiple I/O request </li></ul><ul><li>Priority interrupt system – this system checks which request should be served first if two or more request comes at the same time </li></ul><ul><li>Higher priority levels are assigned to requests which if delayed or interrupted could have serious consequences </li></ul>
  24. 24. Modes of data transfer <ul><li>Handling multiple I/O request </li></ul><ul><li>The polling procedure can be used to identify the highest-priority </li></ul><ul><li>In Polling the status registers , the priority is determined by the way in which the devices are polled </li></ul><ul><li>The highest priority source is tested first , if interrupt signal is on ,control branches to its ISR. </li></ul><ul><li>When vectored interrupts are used, we must ensure that only one device is selected to send its interrupt vector code </li></ul>
  25. 25. Modes of data transfer <ul><li>DMA </li></ul><ul><li>In Direct Memory Address (DMA) , the interface transfers data into and out of the memory unit through the memory bus without continuous intervention by processor </li></ul><ul><li>This is done to transfer large block of data at high speed </li></ul><ul><li>DMA transfers are performed by a control circuit that is a part of I/O interface, called as DMA controller </li></ul><ul><li>For each word transferred ,it provides memory address and signals that control data transfer </li></ul>
  26. 26. Modes of data transfer <ul><li>The operation of DMA controller is under the supervision of a program executed by the processor </li></ul><ul><li>To initiate a transfer , processor sends the starting address and number of blocks and direction of transfer </li></ul><ul><li>When the entire block is transferred, the controller informs the processor by raising an interrupt </li></ul><ul><li>Two registers are used for storing the starting address and word count. Third register contains the control flags </li></ul>
  27. 27. Modes of data transfer -DMA Processor Main memory Disk/DMA controller DMA controller Printer Keyboard Network interface disk disk System bus
  28. 28. Modes of data transfer <ul><li>To start DMA , the program writes the address and word count into registers and also provides information to identify data for future retrieval </li></ul><ul><li>Controller performs required operation and on completion, it set the bits of status line </li></ul><ul><li>The status register can keep information about errors etc. </li></ul><ul><li>Request by DMA devices are given priority than processor requests for using the bus </li></ul>
  29. 29. Modes of data transfer <ul><li>The processor generates memory access cycles, and DMA controller can be said to steal memory cycles from the processor. This process is called cycle stealing </li></ul><ul><li>DMA controller is given exclusive access to the main memory to transfer a block of data without interruption. This is known as block or burst mode </li></ul>
  30. 30. Modes of data transfer <ul><li>If two DMA controllers try to access bus at same time, an arbitration procedure is necessary and is called as bus arbitration </li></ul><ul><li>The device that is allowed to initiate data transfers on the bus at any given time is known as bus master </li></ul><ul><li>When current master relinquishes control, another device can become bus master </li></ul><ul><li>Bus arbitration is the process by which the next device to become bus master is selected and control is transferred to it. </li></ul>