Tuning Word Retiming of a Digitally-Controlled Oscillator Using RF Built-In Self Test

892 views

Published on

This paper represents an innovative solution to
reduce phase noise present on the GMSK modulated spectrum in
an all-digital RF transmitter employing a discrete-time oscillator.
The root cause of this issue is the improper timing of oscillator
tuning word update with respect to the digitally-controlled
oscillator (DCO) capacitor state. Using the built-in self test (BIST)
circuit in the all-digital PLL (ADPLL), the DCO tuning word
update timing is calibrated such that the impact on the phase
noise is compensated and desired modulated spectrum margin
from the specification is achieved.

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
892
On SlideShare
0
From Embeds
0
Number of Embeds
7
Actions
Shares
0
Downloads
0
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Tuning Word Retiming of a Digitally-Controlled Oscillator Using RF Built-In Self Test

  1. 1. 1 Tuning Word Retiming of a Digitally-Controlled Oscillator Using RF Built-In Self Test Imran Bashir, Robert Bogdan Staszewski, and Oren Eliezer Texas Instruments, Dallas, TX 75243, USA email: imran.bashir@ti.com that changing the tuning control input of an oscillator, in Abstract— This paper represents an innovative solution to reduce phase noise present on the GMSK modulated spectrum in order to adjust its phase/frequency in a normal PLL operation, an all-digital RF transmitter employing a discrete-time oscillator. is quite a disturbing event that reveals itself as jitter or The root cause of this issue is the improper timing of oscillator phase noise [3]. This is especially noticeable in case of a tuning word update with respect to the digitally-controlled sample-mode oscillator, such as the DCO, where its oscillating oscillator (DCO) capacitor state. Using the built-in self test (BIST) frequency is commanded to change at discrete times. Since the circuit in the all-digital PLL (ADPLL), the DCO tuning word update timing is calibrated such that the impact on the phase oscillating frequency of an LC tank is controlled by a voltage- noise is compensated and desired modulated spectrum margin to-capacitance conversion device, i.e., varactor, the instances from the specification is achieved. when the oscillating energy is fully stored in a capacitor are the worst moments to change the capacitance. The total I. PRINCIPLE OF SYNCHRONOUSLY-OPTIMAL DCO charge must be preserved, so changing the capacitance at those TUNING WORD RETIMING moments causes the electrical potential to exhibit the largest change (∆V = Q/∆C), as shown plot in Fig. 2-a. These DCO perturbations are then AM-to-PM translated by the oscillator Oscillator CKV circuit into timing jitter. Changing the varactor capacitance at tuning word ÷2 times when it is fully discharged will hardly affect its voltage (OTW) and thus hardly contribute to the oscillating jitter (Fig. 2-b). The solution is to control the timing moments when the Delay line adjustment varactor capacitance change is allowed to occur, thus minimiz- VDD ing jitter due to the tuning word update. This is implemented ÷N by feeding the delayed oscillator edge transitions back as the clock input to the synchronous register retiming stage, as shown in Fig. 1. The retiming stage ensures that the input Fig. 1. Synchronously-optimal sampling and timing adjustment of the DCO control data, as seen by the oscillator, is allowed to change at input. precise and optimal time after the oscillator zero-crossings. The actual delay control could be accomplished by a V(t) voltage-controlled delay line, such as a long string of inverters Q/∆C while externally controlling their VDD supply voltage. The allowed range of the delay line VDD voltage is quite limited (from 0.9 V to about 1.4 V) so the delay change contribution t per inverter is not very significant. However, the delay mul- tiplied by the total number of inverters can exceed the DCO Capacitance change clock cycle, thus guaranteeing the full 360 degree coverage. (a) V(t) A fully-digital delay control method, which is preferred over the analog control, is described in Sec. II. t II. FLYBACK DELAY REALIZATION In our implementation, the DCO flyback delay is controlled digitally as shown in Fig. 3. The CKV clock gets edge divided (b) Capacitance change by a factor of 2 and then passed to the string of seven buffers. The multiplexer connected to the buffer string selects one of Fig. 2. Waveforms for capacitance change of an LC-tank oscillator. the eight delays with the granularity of one buffer delay that is Fig. 1 illustrates the principle of synchronously-optimal approximately equal to the two inverter delays. The sampling digitally-controlled oscillator (DCO) input tuning word retim- instances of the oscillator tuning word (OTW) are controlled ing method [1] [2]. This idea is based on the observation digitally with the 3-bits nominal range of 1110–1460 ps.
  2. 2. 2 1 DCO Oscillator CKV 0.8 tuning word ÷2 Waveform and its delayed version (OTW) 0.6 0.4 ÷2 0.2 0 7 1 0 Delay line −0.2 adjustment −0.4 Fig. 3. Digital flyback delay adjustment. The nominal average round-trip −0.6 delay of 1300 ps is about five times the period of the center resonant frequency. −0.8 −1 0 1 2 3 4 5 Toggling activity of the OTW fractional part is programmable Time [T ] 0 to mimic the Σ∆ dithering clock operation at CKV divided 1 by 2, 4 or 8. Of course, the OTW integer part toggles at the 0.8 FREF clock rate, which is much smaller that the fractional Waveform and its delayed version 0.6 part. 0.4 III. EFFECT OF OPERATING FREQUENCY 0.2 The total delay around the DCO has a strong effect on 0 the sampling phase variability of the input tuning word as −0.2 a function of the carrier frequency. For the zero round trip delay, the tuning word instances would be always optimal −0.4 and independent of the carrier frequency. The zero-crossings −0.6 of the sinusoidal LC-tank waveform would instantly produce −0.8 rising edges of the clock used to sample the tuning word flip- −1 flops so that the varactor updates would happen when the 0 1 2 3 4 5 Time [T ] varactor charge is the lowest. For the round trip delays being 0 exact multiples of the LC-tank oscillating period, the input Fig. 4. Simulated effect of the multi-cycle flyback delay on the input phase. tuning word timing instances are ideal but this relationship The period is (1 − 1/8)T0 and the delay changes by the discrete multiples of would only hold at these specific frequencies. If the round trip T0 . Since the frequency change is not linear to the period change, ε = 1/9. delay is equal to the DCO core period T0 at one frequency f0 = 1/T0 , the input timing will change by the amount of the period change ∆T = T1 − T0 . Similarly, if the round trip Fig. 5 shows the analysis in more detail. The analysis delay is multiple of the DCO core period N · T0 , changing the incorporates the divide-by-2 of the CKV clock, which bears frequency by f0 · (1 + ε) will move the input sampling point no effect on the results. by T1 · ε · N . This is illustrated in Fig. 4. The mathematical IV. EXPERIMENTAL VALIDATION justification is presented below. Let ω0 be an angular frequency at which the round trip The proposed techniques have been realized in 90 nm delay td = T0 · N is multiple of the clock periods. The phase CMOS single-chip GSM radio whose implementation is de- argument to the sin function is N · 2π, where N = 0, 1, 2, . . .. scribed in [5]. Fig. 6 shows carrier phase noise plot at 1909.8 MHz with v0 (t) = sin(ω0 t − ω0 · N T0 ) (1) different flyback delays. The notable difference is the close- Let the frequency increases by factor ε such that the new in phase noise around 10 kHz. Although, the phase noise at frequency is ω1 = ω0 (1 + ε). Since the absolute delay is 400 kHz, which is the most critical close-in frequency offset constant, it will no longer be the multiple of the new clock from the carrier in the GSM specification, does not show a lot periods and a timing adjustment ∆td = ε · T0 · N is required of variation with flyback delay but when the carrier undergoes to maintain the ideal sampling instances. frequency modulation through a DCO in a two point modula- tion system, the contributions at all offsets can contribute to the v1 (t) = sin (ω0 (1 + ε)t − ω0 (1 + ε) · N T0 + ∆td ) (2) degradation 400 kHz offset. This is illustrated in Fig. 7 which Another words, in order to maintain the optimal sampling shows measurement of GMSK modulated spectrum with and instances of the DCO, the period change by ∆T = −T0 /(1 + without flyback delay compensation. The spectrum at close-in ε) will result in the needed delay adjustment of ∆td = ε·N T0 . offset is dominated by the GMSK modulation but at 400 kHz Using the typical numbers of T0 = 280 ps, td = 1300 ps we there is a spectral growth due to the effect described earlier. obtain N ≈ 5. Consequently, each additional 50 ps delay step Fig. 8 shows the measurement of 400 kHz phase noise at will compensate a 10 ps addition in the oscillating period. three different DCO core periods and three different tem-
  3. 3. 3 T0 −10 Uncompensated Flyback Delay Compensated Flyback Delay Spec T0+∆T −20 0T0 1T0 Flyback delay 2T0 −30 3T0 4T0 5T0 Power [dBm] −40 6T0 7T0 8T0 −50 9T0 −60 Fig. 5. Analysis based on tracking of the rising edges. T0 is the initial DCO core period, such that the flyback delay is N · T0 . T1 = T0 + ∆T is the second clock period. The analysis incorporates the divide-by-2 of the CKV −70 clock. −80 1909.3 1909.4 1909.5 1909.6 1909.7 1909.8 1909.9 1910 1910.1 1910.2 1910.3 Frequency [MHz] Fig. 7. GMSK modulated spectrum at 1909.8 MHz with and without flyback delay compensation. It is important to increase the sensitivity of the system to the AM-to-PM perturbation due to un-calibrated flyback delay thus making the effects more visible at PHE. To do this, the ADPLL is operated without modulation so that the DCO gain estimation error is eliminated. Also, the AM-to-PM perturbations are visible in the carrier phase noise spectrum at close-in offsets as shown in Fig. 6. Hence narrowing the ADPLL loop band-width will amplify these perturbations. This is illustrated in Fig. 11. Fig. 6. Carrier phase noise at 1909.8 MHz with different flyback delays. Under these settings, the flyback delay can be calibrated for the optimal performance at the various frequencies in the TX band. Based on this calibration, the frequency compensation of peratures. Both frequency and temperature effect the total flyback delay over the band can be performed. For temperature flyback delay. In all these figures, the duration of the peak compensation, the variation in inverter delay over temperature is approximately 2 delays that is 2 × 50 ps = 100 ps. Fig. 9 resulting in optimum fly-back delay setting shift will be captures similar effect in a 3D plot. tracked by the equation discussed in Section 3. Fig. 10 shows the measured and estimated phase error performance. The estimated phase error is determined using the ADPLL RF-BIST system that monitors the PHE signal VI. CONCLUSION at the output of the phase detector [4]. The built-in base- We have presented a novel approach for calibration and band processor captures these samples and performs the root- compensation of fly-back delay to properly time the DCO mean-square operation on these samples to report the mean tuning word update in order to compensate for any excess RMS phase error for each flyback delay code at the desired noise caused by AM-to-PM perturbations in the DCO core. frequency. The proposed approach is a practical application of Digital RF Processor with a base-band processor that also utilizes V. CALIBRATION AND COMPENSATION OF FLYBACK RF-BIST of the ADPLL for calibration purposes. DELAY REFERENCES An efficient and reliable calibration and compensation can be designed if the effect of fly-back delay on modulated [1] R. B. Staszewski, D. Leipold, K Muhammad, and P. T. Balsara, “Dig- spectrum and phase error is understood. From Fig. 8 it itally controlled oscillator (DCO)-based architecture for RF frequency is clear that only 2 out of 8 delay settings result in bad synthesis in a deep-submicrometer CMOS process,” IEEE Trans. on Circuits and Systems II, vol. 50, no. 11, pp. 815–828, Nov. 2003. performance. Therefore the sample space of events resulting in [2] C.-M. Hung, R. B. Staszewski, N. Barton, M.-C. Lee, and D. Leipold, bad performance is smaller than the sample space resulting in “A digitally controlled oscillator system for SAW-less transmitters in good performance. Also, the measurement is more repeatable cellular handsets,” IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp. 1160–1170, May 2006. in presence of excess noise. It makes sense to scan for the [3] A. Hajimiri, T. H. Lee, “A general theory of phase noise in electrical worse fly-back setting than determining the optimum fly-back oscillators,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 326– setting. 336, Feb. 1998.
  4. 4. 4 −54 1710.2MHz = 292ps 1747.4MHz = 287ps 1784.8MHz = 280ps −56 −58 400kHz Phase Noise [dB] −60 −62 −64 −66 −68 1 2 3 4 5 6 7 8 Flyback Delay −54 1710.2MHz = 292ps 1747.4MHz = 287ps 1784.8MHz = 280ps −56 Fig. 9. Measured effect of fly-back delay setting on 400 kHz modulated −58 spectrum over temperature and frequency. 400kHz Phase Noise [dB] −60 −62 2 Measured −64 1.8 Computed −66 1.6 1.4 −68 RMS phase error 1 2 3 4 5 6 7 8 Flyback Delay 1.2 −54 1710.2MHz = 292ps 1747.4MHz = 287ps 1 1784.8MHz = 280ps −56 0.8 −58 0.6 400kHz Phase Noise [dB] 0.4 −60 0.2 −62 0 0 1 2 3 4 5 6 7 Flyback delay −64 Fig. 10. Measured and calculated values of the rms phase error versus flyback −66 delay. Carrier frequency is 1909.8 MHz. −68 1 2 3 4 5 6 7 8 Flyback Delay Fig. 8. Effect of the flyback delay on the modulated spectrum at 400 kHz offset. Measured at (top) -40C, (middle) +25C and (bottom) +85C. It confirms the theoretical analysis in the text. The GSM specification is -60 dB. [4] I. Bashir, R. B. Staszewski, O. Eliezer, and E. de-Obaldia, “Built-in self testing (BIST) of RF performance in a system-on-chip (SoC),” Proc. of 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS-05), pp. 215–218, Oct. 2005, Dallas, TX. [5] R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-digital PLL and transmitter for mobile phones,” IEEE Journal of Solid-State Circuits, vol. 40, iss. 12, pp. 2469–2482, Dec. 2005. Fig. 11. Modulated spectrum at 400 kHz vs. RMS phase error. This plot shows how the sensitivity of the system is enhanced by narrowing the ADPLL loop bandwidth.

×