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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.

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  1. 1. G.Arunkumar, A.Prakash, R.Subramanian / International Journal of Engineering Researchand Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.128-132128 | P a g eA Simplified Topology for Seven Level Modified MultilevelInverter with Reduced Switch Count TechniqueG.Arunkumar*, A.Prakash**, R.Subramanian****Department of Electrical and Electronics Engineering, Akshaya College of Engineering & Tech.,Coimbatore-109** Department of Electrical and Electronics Engineering, Akshaya College of Engineering & Tech.,Coimbatore-109*** Department of Electrical and Electronics Engineering, Akshaya College of Engineering & Tech.,Coimbatore-109ABSTRACTIn this paper, a seven level modifiedcascaded multilevel inverter is proposed forindustrial drive applications. Apart fromselecting the conventional level inverters, Multilevel inverters has been chosen for the industrialdrive applications as it reduces the totalharmonic distortion. The involvement of highernumber of switches increases the complexity ofthe system, which leads to losses in switching,producing huge harmonics and in the end, itentirely reduces the efficiency of the system. Thecascaded multilevel inverter involves only fewerswitches, where it reduces the complexity of thesystem which in turn reduces the harmonics andreduces the complexity of the system and in totalit reduces the total harmonics distortion.Keywords – Cascaded Multilevel Inverter,Insulated Gate Bipolar Transistor, Pulse WidthModulation, Total Harmonic Distortion.I. INTRODUCTIONIn recent years, huge industrial applicationsrequire high power rating apparatus to improve theefficiency of the system. In conventional two levelinverter, it is found that there are many problems inaccordance with the high power applications. Owingto this, the implementation of Multi level inverterstakes place, which in turn reduces the total harmonicdistortion of the entire system. The multi levelinverters can be operated at higher switchingfrequencies while producing lower order harmoniccomponents. In this technique, a H-bridge inverter isintroduced (full bridge inverter). The total outputvoltage is the sum of the outputs produced at eachH-bridge cell. For a single phase system, only oneH-bridge cell is required, which involves one switchand a diode for each voltage source.II. CASCADED MULTI LEVEL INVERTERFor a single phase system, the generalstructure of cascaded multilevel inverter is shown inFigure 1. In this structure, each voltage source isconnected in cascade with other sources (Vdc1, Vdc2,and Vdc3) via a H-bridge circuit. Here each H-bridgecircuit consists of four active switching elements,which in turn decides whether the output is to be ofpositive or negative polarity. The MLI invertertopology employs three voltage sources of equalmagnitudes, where it is easy to generalize thenumber of distinct levels.Based on the number of stages or sources, theassociated number of output level can be written asfollows:Nlevel = 2S+1 ------------------- (1)As the proposed level is the seven level multilevelinverter, the value for „S‟ is taken as 3 and the outputvoltage levels can be identified as 3Vdc, 2Vdc, 1Vdcand 0.In this topology, the numbers of controlled switchesare given by the equationNswitch = 4S--------------------- (2)The output voltage is given by V0 =A1+A2+A3where A1, A2 and A3 are the DC voltage sources.The cascaded multilevel inverter is well known forits excellent layout and its packing. The onlydisadvantage of this topology is that each H-bridgecircuit requires separate DC source, which finallyleads to high number of semi conductor switches.The output voltage waveform of a seven levelcascaded inverter with separate DC source is givenin Figure 2.Figure 1. Topology of Cascaded Multilevel Inverter
  2. 2. G.Arunkumar, A.Prakash, R.Subramanian / International Journal of Engineering Researchand Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.128-132129 | P a g eIII. MODIFIED CASCADED MULTI LEVELINVERTERThe modified cascaded multilevel inverteris a combination of a multi conversion cell and a H-bridge. The proposed multilevel inverter is shown inFigure 3. Here the multi conversion cell consists ofthree separate voltage sources (Vdc1, Vdc2, and Vdc3).With the help of one active switching element and adiode, each voltage source is connected in cascadewith the other source, which leads to the outputvoltage only in the positive level with several levels.A different control pattern is followed in thistopology. First the switch S1 is turned on to obtainthe voltage level of +1Vdc. At this instant switch S2and S3 are turned off. Similarly, the switches S1 andS2 are turned on to obtain the voltage level of +2Vdc.Now the switch S3 is turned off. Now the switchedS1, S2 and S3 are turned on to obtain the voltagelevel of +3Vdc. Apart from producing all the voltagelevels at the output stage, a unique procedure ofcalculating the required dc voltage source isproposed. Pulse Width Modulation is proposed inthis topology.The main advantage of this proposed multi levelinverter is obtaining seven level with reducesnumber of switches.Based upon the number of DC Sources taken and theassociated number output level can be calculated byusing the equationNlevel = 2S+1---------------- (3)As the proposed multilevel inverter is designed forseven level, taking S=3, the output will have sevenlevels as follows: 3Vdc, 2Vdc, 1Vdc and 0In this topology, the numbers of controlled switchesare given by the equationNswitch = 2S+4-------------- (4)The output voltage is given by V0 =A1+A2+A3where A1, A2 and A3 are the DC voltage sources.Figure 2. Typical Output Waveform for CascadedMultilevel InverterIV. REDUCTION OF HARMONICS BY PULSEWIDTH MODULATION TECHNIQUEThe most extensively used method forreducing the harmonics in the inverters is the PulseWidth Modulation Technique. In this control, theselected switches are turned ON and OFF severaltimes during the half cycle and the output voltage iscontrolled by varying the pulse width. Among theexisting modulation techniques, sinusoidal PWM isthe most widely used method in controlling themotor and inverter application. In order to verify theproposed multilevel inverter topology, programmedSPWM technique is applied in order to determinethe required switching angles. This method isapplied in order to synthesize the output voltage withdesired amplitude and to obtain better harmonicspectrum. It is clearly evident that in order to controlthe fundamental output voltage and to eliminate theharmonics, „n+1‟ equations are needed.Figure 3. Proposed Topology of the ModifiedCascaded Multilevel InverterV. TOTAL HARMONIC DISTORTIONGenerally harmonics have frequencies thatare integer multiples of the waveform‟s fundamentalfrequency. The ideal sine wave has zero harmoniccomponents. The Total Harmonic Distortion is thesummation of all harmonic components of thevoltage or current waveform compared against thefundamental component of the voltage or currentwaveform. The general equation for THD is givenbyVI. SIMULATION RESULT ANALYSIS
  3. 3. G.Arunkumar, A.Prakash, R.Subramanian / International Journal of Engineering Researchand Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.128-132130 | P a g eThe proposed modified multilevel inverterfor induction motor drive is simulated usingMATLAB. The simulated diagram for the inductionmotor drive using MATLAB is shown in Figure 4.The switching pulse sequence for single phase isgiven in Figure 5. The output voltage waveform ofthree phase line to ground voltage and line to linevoltages are given in 6a and 6b. For the proposedinverter, the phase voltage is 212 V and line voltageis 370 V. Figure 7a and 7b shows the outputwaveform of speed and torque curve of inductionmotor. It is seen that the motor attains the ratedspeed at 0.8 msec and the torque gets settled down at0.5 msec. Figure 8 shows the detailed simulinkdiagram for an individual phase. The output isobtained for the permanent magnet asynchronousmachine. Figure 9 shows the FFT analysis. From theFFT analysis it is seen that when the number oflevels are getting increased, the harmonics and thetotal harmonic distortion is reduced. At loadconditions, the THD value of the proposed inverteris found to be 33.58%.Figure 4. Simulation of the Modified CascadedMultilevel InverterVII. CONCLUSIONFrom the above inferences, it is clear thatthe proposed multilevel inverter topology can beused for induction motor drive applications, whichinvolves less number of switches, which in turnreduces the complexity of the system. As theconventional seven level inverter involves twelveswitches, it increases the complexity of the circuit,increases switching losses and cost of the circuit isalso increased. But in the proposed topology, thesame seven levels is obtained with only sevenswitches, which reduces the harmonics, circuitcomplexity, reduces the cost and moreover it reducesthe total harmonic distortion.Figure 5. Switching Pulse Sequence of R-PhaseFigure 6(a) Output Voltage Waveform for ThreePhase Line to groundFigure 6(b) Output Voltage Waveform for ThreePhase Line to Line
  4. 4. G.Arunkumar, A.Prakash, R.Subramanian / International Journal of Engineering Researchand Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.128-132131 | P a g eFigure 7 (a) Modified Cascaded Multilevel Inverter– Speed CurveFigure 7 (b) Modified Cascaded Multilevel Inverter– Torque CurveFigure 8. Detailed Model for Individual PhaseFigure 9 Modified Cascaded Multilevel Inverter –FFT Analysis.REFERENCES[1] Franquelo, L.G., (2008), “The age ofmultilevel converter arrives”, IEEEIndustrial Electronics Magazine, Vol.2,No.2, 28-39.[2] Rodriguez, J., Lai, J.S. & Peng, F.Z.,(2002) “Multilevel Inverters: Survey oftopologies, controls, and applications”,IEEE Trans. Ind. Appl. Vol.49, No.4, 724-738.[3] Corzine, K.A., Wielebski, M.W., Peng, F.Z& Wang, J., (2004), “Control of cascadedmultilevel inverters”, IEEE Trans. PowerElectron. Vol.19, No.3, 732-738.[4] Chiasson, J.N. Tobert, L.M., McKenzie,K.J. & Du, Z., (2004), “A UnifiedApproach to Solving the HarmonicElimination Equations in MultilevelConverters”, IEEE Trans. Power Electron,Vol.19, No.2, pp. 478-490.[5] Patel, H.S. & Hoft, R.G., (1973),“Generalized Techniques of HarmonicElimination and Voltage Control inThyristor Inverters: Part I – HarmonicElimination”, IEEE Trans. Ind. Appl., 3, pp.310-317.[6] B. Ismail, S. T. “Development of a SinglePhase SPWM Microcontroller-BasedInverter” First International Power andEnergy Conference PEC, Putrajaya,Malaysia: IEEE, Nov, 28 -29, 2006.[7] Fang Zheng Peng “A GeneralizedMultilevel Inverter Topology with SelfVoltage Balancing”, IEEE Trans. Ind .Appl.,Vol.37, No.2, March/April 2001.[8] Z.Du, L.m.Tolbert, J.N.Chiasson, andB.Opineci, “A cascaded multilevel inverterusing a single dc power source”, in Proc.IEEE APEC, pp.426-430, 2006.[9] W.Menzies, P.Steimer, and J.K.Steinke,“Five level GTO inverters for largeinduction motor drives,” IEEE Transactionson Industry Applications, Vol.30, No.4,pp.938-944, July 1994.[10] Martin Veenstra, INVESTIGATION ANDCONTROL OF A HYBRIDASYMMETRIC MULTI-LEVELINVERTER FOR MEDIUM-VOLTAGEAPPLICATIONS, 2003, Lausanne, EPFL.
  5. 5. G.Arunkumar, A.Prakash, R.Subramanian / International Journal of Engineering Researchand Applications (IJERA) ISSN: 2248-9622 www.ijera.comVol. 3, Issue 3, May-Jun 2013, pp.128-132132 | P a g eG.Arunkumar received the B.Edegree in Electrical andElectronics Engineering fromKarpagam College of Engineeringin the year 2006 and M.E inEmbedded System Technologiesfrom Anna University in the year2009. He is currently pursuingPh.D in the area of Power Quality and he is currentlyworking as Assistant Professor at Akshaya Collegeof Engineering & Technology, Coimbatore. Hisresearch interests are Power Quality and FACTS. Heis a professional member of IEEE and a LifeMember in ISTE.A.Prakash received the B.Edegree in Electrical andElectronics Engineering from SriNandhanam College ofEngineering and Technology inthe year 2005 and M.Tech degreein Power Electronics and Drivesfrom PRIST University, Tanjore in the year 2011.He is currently working as an Assistant Professor inthe Department of Electrical and ElectronicsEngineering at Akshaya College of Engineering andTechnology, Coimbatore. His research interests arePower System Modeling and Analysis and PowerElectronic applications to Power Systems. He is aLife Member in ISTE.R.Subramanian received the B.Edegree in Electrical andElectronics Engineering fromCoimbatore Institute ofTechnology in the year 2005 andM.E degree in Power SystemsEngineering from GovernmentCollege of Technology, Coimbatore in the year2007. He is currently doing PhD in the area ofPower system control and operation under AnnaUniversity. Presently he is working as an Associateprofessor in the Department of Electrical andElectronics Engineering at Akshaya College ofEngineering and Technology, Coimbatore. Hisresearch interests are power system analysis, powersystem control and operation, mathematicalcomputations, optimization and Soft ComputingTechniques. He is a professional member of IEEEand a Life Member in ISTE.